tegra_i2c.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * NVIDIA Tegra I2C controller
  4. *
  5. * Copyright 2010-2011 NVIDIA Corporation
  6. */
  7. #ifndef _TEGRA_I2C_H_
  8. #define _TEGRA_I2C_H_
  9. #include <asm/types.h>
  10. struct udevice;
  11. enum {
  12. I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
  13. I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
  14. };
  15. enum i2c_transaction_flags {
  16. I2C_IS_WRITE = 0x1, /* for I2C write operation */
  17. I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
  18. I2C_USE_REPEATED_START = 0x4, /* for repeat start */
  19. I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
  20. I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
  21. I2C_NO_STOP = 0x20,
  22. };
  23. /* Contians the I2C transaction details */
  24. struct i2c_trans_info {
  25. /* flags to indicate the transaction details */
  26. enum i2c_transaction_flags flags;
  27. u32 address; /* I2C slave device address */
  28. u32 num_bytes; /* number of bytes to be transferred */
  29. /*
  30. * Send/receive buffer. For the I2C send operation this buffer should
  31. * be filled with the data to be sent to the slave device. For the I2C
  32. * receive operation this buffer is filled with the data received from
  33. * the slave device.
  34. */
  35. u8 *buf;
  36. int is_10bit_address;
  37. };
  38. struct i2c_control {
  39. u32 tx_fifo;
  40. u32 rx_fifo;
  41. u32 packet_status;
  42. u32 fifo_control;
  43. u32 fifo_status;
  44. u32 int_mask;
  45. u32 int_status;
  46. };
  47. struct dvc_ctlr {
  48. u32 ctrl1; /* 00: DVC_CTRL_REG1 */
  49. u32 ctrl2; /* 04: DVC_CTRL_REG2 */
  50. u32 ctrl3; /* 08: DVC_CTRL_REG3 */
  51. u32 status; /* 0C: DVC_STATUS_REG */
  52. u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
  53. u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
  54. u32 reserved_0[2]; /* 18: */
  55. u32 req; /* 20: DVC_REQ_REGISTER */
  56. u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
  57. u32 reserved_1[6]; /* 28: */
  58. u32 cnfg; /* 40: DVC_I2C_CNFG */
  59. u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
  60. u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
  61. u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
  62. u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
  63. u32 reserved_2[2]; /* 54: */
  64. u32 i2c_status; /* 5C: DVC_I2C_STATUS */
  65. struct i2c_control control; /* 60 ~ 78 */
  66. };
  67. struct i2c_ctlr {
  68. u32 cnfg; /* 00: I2C_I2C_CNFG */
  69. u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
  70. u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
  71. u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
  72. u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
  73. u32 reserved_0[2]; /* 14: */
  74. u32 status; /* 1C: I2C_I2C_STATUS */
  75. u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
  76. u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
  77. u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
  78. u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
  79. u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
  80. u32 reserved_1[2]; /* 34: */
  81. u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
  82. u32 reserved_2[4]; /* 40: */
  83. struct i2c_control control; /* 50 ~ 68 */
  84. u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
  85. };
  86. /* bit fields definitions for IO Packet Header 1 format */
  87. #define PKT_HDR1_PROTOCOL_SHIFT 4
  88. #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
  89. #define PKT_HDR1_CTLR_ID_SHIFT 12
  90. #define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
  91. #define PKT_HDR1_PKT_ID_SHIFT 16
  92. #define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
  93. #define PROTOCOL_TYPE_I2C 1
  94. /* bit fields definitions for IO Packet Header 2 format */
  95. #define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
  96. #define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
  97. /* bit fields definitions for IO Packet Header 3 format */
  98. #define PKT_HDR3_READ_MODE_SHIFT 19
  99. #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
  100. #define PKT_HDR3_REPEAT_START_SHIFT 16
  101. #define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
  102. #define PKT_HDR3_SLAVE_ADDR_SHIFT 0
  103. #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
  104. #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
  105. #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
  106. (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
  107. /* I2C_CNFG */
  108. #define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
  109. #define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
  110. #define I2C_CNFG_PACKET_MODE_SHIFT 10
  111. #define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
  112. /* I2C_SL_CNFG */
  113. #define I2C_SL_CNFG_NEWSL_SHIFT 2
  114. #define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
  115. /* I2C_FIFO_STATUS */
  116. #define TX_FIFO_FULL_CNT_SHIFT 0
  117. #define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
  118. #define TX_FIFO_EMPTY_CNT_SHIFT 4
  119. #define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
  120. /* I2C_INTERRUPT_STATUS */
  121. #define I2C_INT_XFER_COMPLETE_SHIFT 7
  122. #define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
  123. #define I2C_INT_NO_ACK_SHIFT 3
  124. #define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
  125. #define I2C_INT_ARBITRATION_LOST_SHIFT 2
  126. #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
  127. /* I2C_CLK_DIVISOR_REGISTER */
  128. #define CLK_DIV_STD_FAST_MODE 0x19
  129. #define CLK_DIV_HS_MODE 1
  130. #define CLK_MULT_STD_FAST_MODE 8
  131. /**
  132. * Returns the bus number of the DVC controller
  133. *
  134. * @return number of bus, or -1 if there is no DVC active
  135. */
  136. int tegra_i2c_get_dvc_bus(struct udevice **busp);
  137. #endif /* _TEGRA_I2C_H_ */