clock.h 3.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #ifndef _ASM_ARCH_CLOCK_H
  6. #define _ASM_ARCH_CLOCK_H
  7. struct udevice;
  8. /* define pll mode */
  9. #define RKCLK_PLL_MODE_SLOW 0
  10. #define RKCLK_PLL_MODE_NORMAL 1
  11. #define RKCLK_PLL_MODE_DEEP 2
  12. enum {
  13. ROCKCHIP_SYSCON_NOC,
  14. ROCKCHIP_SYSCON_GRF,
  15. ROCKCHIP_SYSCON_SGRF,
  16. ROCKCHIP_SYSCON_PMU,
  17. ROCKCHIP_SYSCON_PMUGRF,
  18. ROCKCHIP_SYSCON_PMUSGRF,
  19. ROCKCHIP_SYSCON_CIC,
  20. ROCKCHIP_SYSCON_MSCH,
  21. };
  22. /* Standard Rockchip clock numbers */
  23. enum rk_clk_id {
  24. CLK_OSC,
  25. CLK_ARM,
  26. CLK_DDR,
  27. CLK_CODEC,
  28. CLK_GENERAL,
  29. CLK_NEW,
  30. CLK_COUNT,
  31. };
  32. #define PLL(_type, _id, _con, _mode, _mshift, \
  33. _lshift, _pflags, _rtable) \
  34. { \
  35. .id = _id, \
  36. .type = _type, \
  37. .con_offset = _con, \
  38. .mode_offset = _mode, \
  39. .mode_shift = _mshift, \
  40. .lock_shift = _lshift, \
  41. .pll_flags = _pflags, \
  42. .rate_table = _rtable, \
  43. }
  44. #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
  45. _postdiv2, _dsmpd, _frac) \
  46. { \
  47. .rate = _rate##U, \
  48. .fbdiv = _fbdiv, \
  49. .postdiv1 = _postdiv1, \
  50. .refdiv = _refdiv, \
  51. .postdiv2 = _postdiv2, \
  52. .dsmpd = _dsmpd, \
  53. .frac = _frac, \
  54. }
  55. struct rockchip_pll_rate_table {
  56. unsigned long rate;
  57. unsigned int nr;
  58. unsigned int nf;
  59. unsigned int no;
  60. unsigned int nb;
  61. /* for RK3036/RK3399 */
  62. unsigned int fbdiv;
  63. unsigned int postdiv1;
  64. unsigned int refdiv;
  65. unsigned int postdiv2;
  66. unsigned int dsmpd;
  67. unsigned int frac;
  68. };
  69. enum rockchip_pll_type {
  70. pll_rk3036,
  71. pll_rk3066,
  72. pll_rk3328,
  73. pll_rk3366,
  74. pll_rk3399,
  75. };
  76. struct rockchip_pll_clock {
  77. unsigned int id;
  78. unsigned int con_offset;
  79. unsigned int mode_offset;
  80. unsigned int mode_shift;
  81. unsigned int lock_shift;
  82. enum rockchip_pll_type type;
  83. unsigned int pll_flags;
  84. struct rockchip_pll_rate_table *rate_table;
  85. unsigned int mode_mask;
  86. };
  87. struct rockchip_cpu_rate_table {
  88. unsigned long rate;
  89. unsigned int aclk_div;
  90. unsigned int pclk_div;
  91. };
  92. int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
  93. void __iomem *base, ulong clk_id,
  94. ulong drate);
  95. ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
  96. void __iomem *base, ulong clk_id);
  97. const struct rockchip_cpu_rate_table *
  98. rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
  99. ulong rate);
  100. static inline int rk_pll_id(enum rk_clk_id clk_id)
  101. {
  102. return clk_id - 1;
  103. }
  104. struct sysreset_reg {
  105. unsigned int glb_srst_fst_value;
  106. unsigned int glb_srst_snd_value;
  107. };
  108. /**
  109. * clk_get_divisor() - Calculate the required clock divisior
  110. *
  111. * Given an input rate and a required output_rate, calculate the Rockchip
  112. * divisor needed to achieve this.
  113. *
  114. * @input_rate: Input clock rate in Hz
  115. * @output_rate: Output clock rate in Hz
  116. * @return divisor register value to use
  117. */
  118. static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  119. {
  120. uint clk_div;
  121. clk_div = input_rate / output_rate;
  122. clk_div = (clk_div + 1) & 0xfffe;
  123. return clk_div;
  124. }
  125. /**
  126. * rockchip_get_cru() - get a pointer to the clock/reset unit registers
  127. *
  128. * @return pointer to registers, or -ve error on error
  129. */
  130. void *rockchip_get_cru(void);
  131. /**
  132. * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
  133. *
  134. * @return pointer to registers, or -ve error on error
  135. */
  136. void *rockchip_get_pmucru(void);
  137. struct rockchip_cru;
  138. struct rk3288_grf;
  139. void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
  140. int rockchip_get_clk(struct udevice **devp);
  141. /*
  142. * rockchip_reset_bind() - Bind soft reset device as child of clock device
  143. *
  144. * @pdev: clock udevice
  145. * @reg_offset: the first offset in cru for softreset registers
  146. * @reg_number: the reg numbers of softreset registers
  147. * @return 0 success, or error value
  148. */
  149. int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
  150. #endif