generic.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/mc_cgm_regs.h>
  15. #include <asm/arch/mc_me_regs.h>
  16. #include <asm/arch/mc_rgm_regs.h>
  17. #include <netdev.h>
  18. #include <div64.h>
  19. #include <errno.h>
  20. u32 get_cpu_rev(void)
  21. {
  22. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
  23. u32 cpu = readl(&mscmir->cpxtype);
  24. return cpu;
  25. }
  26. DECLARE_GLOBAL_DATA_PTR;
  27. static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
  28. u32 pllfd, u32 selected_output)
  29. {
  30. u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
  31. u32 plldv_rfdphi_div = 0, fout = 0;
  32. u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
  33. if (selected_output > DFS_MAXNUMBER) {
  34. return -1;
  35. }
  36. plldv_prediv =
  37. (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
  38. plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
  39. pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
  40. plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
  41. /* The formula for VCO is from TR manual, rev. D */
  42. vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
  43. if (selected_output != 0) {
  44. /* Determine the RFDPHI for PHI1 */
  45. plldv_rfdphi_div =
  46. (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
  47. PLLDIG_PLLDV_RFDPHI1_OFFSET;
  48. plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
  49. if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
  50. dfs_portn =
  51. readl(DFS_DVPORTn(pll, selected_output - 1));
  52. dfs_mfi =
  53. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  54. DFS_DVPORTn_MFI_OFFSET;
  55. dfs_mfn =
  56. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  57. DFS_DVPORTn_MFI_OFFSET;
  58. fout = vco / (dfs_mfi + (dfs_mfn / 256));
  59. } else {
  60. fout = vco / plldv_rfdphi_div;
  61. }
  62. } else {
  63. /* Determine the RFDPHI for PHI0 */
  64. plldv_rfdphi_div =
  65. (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
  66. PLLDIG_PLLDV_RFDPHI_OFFSET;
  67. fout = vco / plldv_rfdphi_div;
  68. }
  69. return fout;
  70. }
  71. /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
  72. static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
  73. u32 selected_output)
  74. {
  75. u32 plldv, pllfd;
  76. plldv = readl(PLLDIG_PLLDV(pll));
  77. pllfd = readl(PLLDIG_PLLFD(pll));
  78. return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
  79. }
  80. static u32 get_mcu_main_clk(void)
  81. {
  82. u32 coreclk_div;
  83. u32 sysclk_sel;
  84. u32 freq = 0;
  85. sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  86. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  87. coreclk_div =
  88. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
  89. coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  90. coreclk_div += 1;
  91. switch (sysclk_sel) {
  92. case MC_CGM_SC_SEL_FIRC:
  93. freq = FIRC_CLK_FREQ;
  94. break;
  95. case MC_CGM_SC_SEL_XOSC:
  96. freq = XOSC_CLK_FREQ;
  97. break;
  98. case MC_CGM_SC_SEL_ARMPLL:
  99. /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
  100. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
  101. break;
  102. case MC_CGM_SC_SEL_CLKDISABLE:
  103. printf("Sysclk is disabled\n");
  104. break;
  105. default:
  106. printf("unsupported system clock select\n");
  107. }
  108. return freq / coreclk_div;
  109. }
  110. static u32 get_sys_clk(u32 number)
  111. {
  112. u32 sysclk_div, sysclk_div_number;
  113. u32 sysclk_sel;
  114. u32 freq = 0;
  115. switch (number) {
  116. case 3:
  117. sysclk_div_number = 0;
  118. break;
  119. case 6:
  120. sysclk_div_number = 1;
  121. break;
  122. default:
  123. printf("unsupported system clock \n");
  124. return -1;
  125. }
  126. sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  127. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  128. sysclk_div =
  129. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
  130. MC_CGM_SC_DCn_PREDIV_MASK;
  131. sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  132. sysclk_div += 1;
  133. switch (sysclk_sel) {
  134. case MC_CGM_SC_SEL_FIRC:
  135. freq = FIRC_CLK_FREQ;
  136. break;
  137. case MC_CGM_SC_SEL_XOSC:
  138. freq = XOSC_CLK_FREQ;
  139. break;
  140. case MC_CGM_SC_SEL_ARMPLL:
  141. /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
  142. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
  143. break;
  144. case MC_CGM_SC_SEL_CLKDISABLE:
  145. printf("Sysclk is disabled\n");
  146. break;
  147. default:
  148. printf("unsupported system clock select\n");
  149. }
  150. return freq / sysclk_div;
  151. }
  152. static u32 get_peripherals_clk(void)
  153. {
  154. u32 aux5clk_div;
  155. u32 freq = 0;
  156. aux5clk_div =
  157. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
  158. MC_CGM_ACn_DCm_PREDIV_MASK;
  159. aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  160. aux5clk_div += 1;
  161. freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
  162. return freq / aux5clk_div;
  163. }
  164. static u32 get_uart_clk(void)
  165. {
  166. u32 auxclk3_div, auxclk3_sel, freq = 0;
  167. auxclk3_sel =
  168. readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
  169. auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
  170. auxclk3_div =
  171. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
  172. MC_CGM_ACn_DCm_PREDIV_MASK;
  173. auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  174. auxclk3_div += 1;
  175. switch (auxclk3_sel) {
  176. case MC_CGM_ACn_SEL_FIRC:
  177. freq = FIRC_CLK_FREQ;
  178. break;
  179. case MC_CGM_ACn_SEL_XOSC:
  180. freq = XOSC_CLK_FREQ;
  181. break;
  182. case MC_CGM_ACn_SEL_PERPLLDIVX:
  183. freq = get_peripherals_clk() / 3;
  184. break;
  185. case MC_CGM_ACn_SEL_SYSCLK:
  186. freq = get_sys_clk(6);
  187. break;
  188. default:
  189. printf("unsupported system clock select\n");
  190. }
  191. return freq / auxclk3_div;
  192. }
  193. static u32 get_fec_clk(void)
  194. {
  195. u32 aux2clk_div;
  196. u32 freq = 0;
  197. aux2clk_div =
  198. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
  199. MC_CGM_ACn_DCm_PREDIV_MASK;
  200. aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  201. aux2clk_div += 1;
  202. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
  203. return freq / aux2clk_div;
  204. }
  205. static u32 get_usdhc_clk(void)
  206. {
  207. u32 aux15clk_div;
  208. u32 freq = 0;
  209. aux15clk_div =
  210. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
  211. MC_CGM_ACn_DCm_PREDIV_MASK;
  212. aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  213. aux15clk_div += 1;
  214. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
  215. return freq / aux15clk_div;
  216. }
  217. static u32 get_i2c_clk(void)
  218. {
  219. return get_peripherals_clk();
  220. }
  221. /* return clocks in Hz */
  222. unsigned int mxc_get_clock(enum mxc_clock clk)
  223. {
  224. switch (clk) {
  225. case MXC_ARM_CLK:
  226. return get_mcu_main_clk();
  227. case MXC_PERIPHERALS_CLK:
  228. return get_peripherals_clk();
  229. case MXC_UART_CLK:
  230. return get_uart_clk();
  231. case MXC_FEC_CLK:
  232. return get_fec_clk();
  233. case MXC_I2C_CLK:
  234. return get_i2c_clk();
  235. case MXC_USDHC_CLK:
  236. return get_usdhc_clk();
  237. default:
  238. break;
  239. }
  240. printf("Error: Unsupported function to read the frequency! \
  241. Please define it correctly!");
  242. return -1;
  243. }
  244. /* Not yet implemented - int soc_clk_dump(); */
  245. #if defined(CONFIG_DISPLAY_CPUINFO)
  246. static char *get_reset_cause(void)
  247. {
  248. u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
  249. switch (cause) {
  250. case F_SWT4:
  251. return "WDOG";
  252. case F_JTAG:
  253. return "JTAG";
  254. case F_FCCU_SOFT:
  255. return "FCCU soft reaction";
  256. case F_FCCU_HARD:
  257. return "FCCU hard reaction";
  258. case F_SOFT_FUNC:
  259. return "Software Functional reset";
  260. case F_ST_DONE:
  261. return "Self Test done reset";
  262. case F_EXT_RST:
  263. return "External reset";
  264. default:
  265. return "unknown reset";
  266. }
  267. }
  268. #define SRC_SCR_SW_RST (1<<12)
  269. void reset_cpu(ulong addr)
  270. {
  271. printf("Feature not supported.\n");
  272. };
  273. int print_cpuinfo(void)
  274. {
  275. printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
  276. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  277. printf("Reset cause: %s\n", get_reset_cause());
  278. return 0;
  279. }
  280. #endif
  281. int cpu_eth_init(struct bd_info * bis)
  282. {
  283. int rc = -ENODEV;
  284. #if defined(CONFIG_FEC_MXC)
  285. rc = fecmxc_initialize(bis);
  286. #endif
  287. return rc;
  288. }
  289. int get_clocks(void)
  290. {
  291. #ifdef CONFIG_FSL_ESDHC_IMX
  292. gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
  293. #endif
  294. return 0;
  295. }