mp.c 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <image.h>
  8. #include <log.h>
  9. #include <asm/cache.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/system.h>
  13. #include <asm/arch/mp.h>
  14. #include <asm/arch/soc.h>
  15. #include <linux/delay.h>
  16. #include "cpu.h"
  17. #include <asm/arch-fsl-layerscape/soc.h>
  18. #include <efi_loader.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. void *get_spin_tbl_addr(void)
  21. {
  22. /* the spin table is at the beginning */
  23. return secondary_boot_code_start;
  24. }
  25. void update_os_arch_secondary_cores(uint8_t os_arch)
  26. {
  27. u64 *table = get_spin_tbl_addr();
  28. int i;
  29. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  30. if (os_arch == IH_ARCH_DEFAULT)
  31. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  32. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  33. else
  34. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  35. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  36. }
  37. }
  38. #ifdef CONFIG_FSL_LSCH3
  39. static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  40. {
  41. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  42. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  43. u32 mpidr = 0;
  44. mpidr = ((cluster << 8) | core);
  45. /*
  46. * mpidr_el1 register value of core which needs to be released
  47. * is written to scratchrw[6] register
  48. */
  49. gur_out32(&gur->scratchrw[6], mpidr);
  50. asm volatile("dsb st" : : : "memory");
  51. rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  52. asm volatile("dsb st" : : : "memory");
  53. /*
  54. * scratchrw[6] register value is polled
  55. * when the value becomes zero, this means that this core is up
  56. * and running, next core can be released now
  57. */
  58. while (gur_in32(&gur->scratchrw[6]) != 0)
  59. ;
  60. }
  61. #endif
  62. int fsl_layerscape_wake_seconday_cores(void)
  63. {
  64. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  65. #ifdef CONFIG_FSL_LSCH3
  66. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  67. u32 svr, ver, cluster, type;
  68. int j = 0, cluster_cores = 0;
  69. #elif defined(CONFIG_FSL_LSCH2)
  70. struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  71. #endif
  72. u32 cores, cpu_up_mask = 1;
  73. int i, timeout = 10;
  74. u64 *table;
  75. #ifdef CONFIG_EFI_LOADER
  76. u64 reloc_addr = U32_MAX;
  77. efi_status_t ret;
  78. #endif
  79. #ifdef COUNTER_FREQUENCY_REAL
  80. /* update for secondary cores */
  81. __real_cntfrq = COUNTER_FREQUENCY_REAL;
  82. flush_dcache_range((unsigned long)&__real_cntfrq,
  83. (unsigned long)&__real_cntfrq + 8);
  84. #endif
  85. #ifdef CONFIG_EFI_LOADER
  86. /*
  87. * EFI will reserve 64kb for its runtime services. This will probably
  88. * overlap with our spin table code, which is why we have to relocate
  89. * it.
  90. * Keep this after the __real_cntfrq update, so we have it when we
  91. * copy the complete section here.
  92. */
  93. ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
  94. EFI_RESERVED_MEMORY_TYPE,
  95. efi_size_in_pages(secondary_boot_code_size),
  96. &reloc_addr);
  97. if (ret == EFI_SUCCESS) {
  98. debug("Relocating spin table from %llx to %llx (size %lx)\n",
  99. (u64)secondary_boot_code_start, reloc_addr,
  100. secondary_boot_code_size);
  101. memcpy((void *)reloc_addr, secondary_boot_code_start,
  102. secondary_boot_code_size);
  103. flush_dcache_range(reloc_addr,
  104. reloc_addr + secondary_boot_code_size);
  105. /* set new entry point for secondary cores */
  106. secondary_boot_addr += (void *)reloc_addr -
  107. secondary_boot_code_start;
  108. flush_dcache_range((unsigned long)&secondary_boot_addr,
  109. (unsigned long)&secondary_boot_addr + 8);
  110. /* this will be used to reserve the memory */
  111. secondary_boot_code_start = (void *)reloc_addr;
  112. }
  113. #endif
  114. cores = cpu_mask();
  115. /* Clear spin table so that secondary processors
  116. * observe the correct value after waking up from wfe.
  117. */
  118. table = get_spin_tbl_addr();
  119. memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  120. flush_dcache_range((unsigned long)table,
  121. (unsigned long)table +
  122. (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  123. debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
  124. #ifdef CONFIG_FSL_LSCH3
  125. gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
  126. gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
  127. svr = gur_in32(&gur->svr);
  128. ver = SVR_SOC_VER(svr);
  129. if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
  130. gur_out32(&gur->scratchrw[6], 1);
  131. asm volatile("dsb st" : : : "memory");
  132. rst->brrl = cores;
  133. asm volatile("dsb st" : : : "memory");
  134. } else {
  135. /*
  136. * Release the cores out of reset one-at-a-time to avoid
  137. * power spikes
  138. */
  139. i = 0;
  140. cluster = in_le32(&gur->tp_cluster[i].lower);
  141. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  142. type = initiator_type(cluster, j);
  143. if (type &&
  144. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  145. cluster_cores++;
  146. }
  147. do {
  148. cluster = in_le32(&gur->tp_cluster[i].lower);
  149. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  150. type = initiator_type(cluster, j);
  151. if (type &&
  152. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  153. wake_secondary_core_n(i, j,
  154. cluster_cores);
  155. }
  156. i++;
  157. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  158. }
  159. #elif defined(CONFIG_FSL_LSCH2)
  160. scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
  161. scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
  162. asm volatile("dsb st" : : : "memory");
  163. gur_out32(&gur->brrl, cores);
  164. asm volatile("dsb st" : : : "memory");
  165. /* Bootup online cores */
  166. scfg_out32(&scfg->corebcr, cores);
  167. #endif
  168. /* This is needed as a precautionary measure.
  169. * If some code before this has accidentally released the secondary
  170. * cores then the pre-bootloader code will trap them in a "wfe" unless
  171. * the scratchrw[6] is set. In this case we need a sev here to get these
  172. * cores moving again.
  173. */
  174. asm volatile("sev");
  175. while (timeout--) {
  176. flush_dcache_range((unsigned long)table, (unsigned long)table +
  177. CONFIG_MAX_CPUS * 64);
  178. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  179. if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  180. SPIN_TABLE_ELEM_STATUS_IDX])
  181. cpu_up_mask |= 1 << i;
  182. }
  183. if (hweight32(cpu_up_mask) == hweight32(cores))
  184. break;
  185. udelay(10);
  186. }
  187. if (timeout <= 0) {
  188. printf("CPU: Failed to bring up some cores (mask 0x%x)\n",
  189. cores ^ cpu_up_mask);
  190. return 1;
  191. }
  192. printf("CPU: %d cores online\n", hweight32(cores));
  193. return 0;
  194. }
  195. int is_core_valid(unsigned int core)
  196. {
  197. return !!((1 << core) & cpu_mask());
  198. }
  199. static int is_pos_valid(unsigned int pos)
  200. {
  201. return !!((1 << pos) & cpu_pos_mask());
  202. }
  203. int is_core_online(u64 cpu_id)
  204. {
  205. u64 *table = get_spin_tbl_addr();
  206. int pos = id_to_core(cpu_id);
  207. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  208. return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
  209. }
  210. int cpu_reset(u32 nr)
  211. {
  212. puts("Feature is not implemented.\n");
  213. return 0;
  214. }
  215. int cpu_disable(u32 nr)
  216. {
  217. puts("Feature is not implemented.\n");
  218. return 0;
  219. }
  220. static int core_to_pos(int nr)
  221. {
  222. u32 cores = cpu_pos_mask();
  223. int i, count = 0;
  224. if (nr == 0) {
  225. return 0;
  226. } else if (nr >= hweight32(cores)) {
  227. puts("Not a valid core number.\n");
  228. return -1;
  229. }
  230. for (i = 1; i < 32; i++) {
  231. if (is_pos_valid(i)) {
  232. count++;
  233. if (count == nr)
  234. break;
  235. }
  236. }
  237. if (count != nr)
  238. return -1;
  239. return i;
  240. }
  241. int cpu_status(u32 nr)
  242. {
  243. u64 *table = get_spin_tbl_addr();
  244. int pos;
  245. if (nr == 0) {
  246. printf("table base @ 0x%p\n", table);
  247. } else {
  248. pos = core_to_pos(nr);
  249. if (pos < 0)
  250. return -1;
  251. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  252. printf("table @ 0x%p\n", table);
  253. printf(" addr - 0x%016llx\n",
  254. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
  255. printf(" status - 0x%016llx\n",
  256. table[SPIN_TABLE_ELEM_STATUS_IDX]);
  257. printf(" lpid - 0x%016llx\n",
  258. table[SPIN_TABLE_ELEM_LPID_IDX]);
  259. }
  260. return 0;
  261. }
  262. int cpu_release(u32 nr, int argc, char *const argv[])
  263. {
  264. u64 boot_addr;
  265. u64 *table = get_spin_tbl_addr();
  266. int pos;
  267. pos = core_to_pos(nr);
  268. if (pos <= 0)
  269. return -1;
  270. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  271. boot_addr = simple_strtoull(argv[0], NULL, 16);
  272. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
  273. flush_dcache_range((unsigned long)table,
  274. (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
  275. asm volatile("dsb st");
  276. /*
  277. * The secondary CPUs polling the spin-table above for a non-zero
  278. * value. To save power "wfe" is called. Thus call "sev" here to
  279. * wake the CPUs and let them check the spin-table again (see
  280. * slave_cpu loop in lowlevel.S)
  281. */
  282. asm volatile("sev");
  283. return 0;
  284. }