cache_v8.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. *
  6. * (C) Copyright 2016
  7. * Alexander Graf <agraf@suse.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <hang.h>
  12. #include <log.h>
  13. #include <asm/cache.h>
  14. #include <asm/global_data.h>
  15. #include <asm/system.h>
  16. #include <asm/armv8/mmu.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  19. /*
  20. * With 4k page granule, a virtual address is split into 4 lookup parts
  21. * spanning 9 bits each:
  22. *
  23. * _______________________________________________
  24. * | | | | | | |
  25. * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
  26. * |_______|_______|_______|_______|_______|_______|
  27. * 63-48 47-39 38-30 29-21 20-12 11-00
  28. *
  29. * mask page size
  30. *
  31. * Lv0: FF8000000000 --
  32. * Lv1: 7FC0000000 1G
  33. * Lv2: 3FE00000 2M
  34. * Lv3: 1FF000 4K
  35. * off: FFF
  36. */
  37. u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
  38. {
  39. u64 max_addr = 0;
  40. u64 ips, va_bits;
  41. u64 tcr;
  42. int i;
  43. /* Find the largest address we need to support */
  44. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  45. max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  46. /* Calculate the maximum physical (and thus virtual) address */
  47. if (max_addr > (1ULL << 44)) {
  48. ips = 5;
  49. va_bits = 48;
  50. } else if (max_addr > (1ULL << 42)) {
  51. ips = 4;
  52. va_bits = 44;
  53. } else if (max_addr > (1ULL << 40)) {
  54. ips = 3;
  55. va_bits = 42;
  56. } else if (max_addr > (1ULL << 36)) {
  57. ips = 2;
  58. va_bits = 40;
  59. } else if (max_addr > (1ULL << 32)) {
  60. ips = 1;
  61. va_bits = 36;
  62. } else {
  63. ips = 0;
  64. va_bits = 32;
  65. }
  66. if (el == 1) {
  67. tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  68. } else if (el == 2) {
  69. tcr = TCR_EL2_RSVD | (ips << 16);
  70. } else {
  71. tcr = TCR_EL3_RSVD | (ips << 16);
  72. }
  73. /* PTWs cacheable, inner/outer WBWA and inner shareable */
  74. tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
  75. tcr |= TCR_T0SZ(va_bits);
  76. if (pips)
  77. *pips = ips;
  78. if (pva_bits)
  79. *pva_bits = va_bits;
  80. return tcr;
  81. }
  82. #define MAX_PTE_ENTRIES 512
  83. static int pte_type(u64 *pte)
  84. {
  85. return *pte & PTE_TYPE_MASK;
  86. }
  87. /* Returns the LSB number for a PTE on level <level> */
  88. static int level2shift(int level)
  89. {
  90. /* Page is 12 bits wide, every level translates 9 bits */
  91. return (12 + 9 * (3 - level));
  92. }
  93. static u64 *find_pte(u64 addr, int level)
  94. {
  95. int start_level = 0;
  96. u64 *pte;
  97. u64 idx;
  98. u64 va_bits;
  99. int i;
  100. debug("addr=%llx level=%d\n", addr, level);
  101. get_tcr(0, NULL, &va_bits);
  102. if (va_bits < 39)
  103. start_level = 1;
  104. if (level < start_level)
  105. return NULL;
  106. /* Walk through all page table levels to find our PTE */
  107. pte = (u64*)gd->arch.tlb_addr;
  108. for (i = start_level; i < 4; i++) {
  109. idx = (addr >> level2shift(i)) & 0x1FF;
  110. pte += idx;
  111. debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
  112. /* Found it */
  113. if (i == level)
  114. return pte;
  115. /* PTE is no table (either invalid or block), can't traverse */
  116. if (pte_type(pte) != PTE_TYPE_TABLE)
  117. return NULL;
  118. /* Off to the next level */
  119. pte = (u64*)(*pte & 0x0000fffffffff000ULL);
  120. }
  121. /* Should never reach here */
  122. return NULL;
  123. }
  124. /* Returns and creates a new full table (512 entries) */
  125. static u64 *create_table(void)
  126. {
  127. u64 *new_table = (u64*)gd->arch.tlb_fillptr;
  128. u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
  129. /* Allocate MAX_PTE_ENTRIES pte entries */
  130. gd->arch.tlb_fillptr += pt_len;
  131. if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
  132. panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
  133. "Please increase the size in get_page_table_size()",
  134. gd->arch.tlb_fillptr - gd->arch.tlb_addr,
  135. gd->arch.tlb_size);
  136. /* Mark all entries as invalid */
  137. memset(new_table, 0, pt_len);
  138. return new_table;
  139. }
  140. static void set_pte_table(u64 *pte, u64 *table)
  141. {
  142. /* Point *pte to the new table */
  143. debug("Setting %p to addr=%p\n", pte, table);
  144. *pte = PTE_TYPE_TABLE | (ulong)table;
  145. }
  146. /* Splits a block PTE into table with subpages spanning the old block */
  147. static void split_block(u64 *pte, int level)
  148. {
  149. u64 old_pte = *pte;
  150. u64 *new_table;
  151. u64 i = 0;
  152. /* level describes the parent level, we need the child ones */
  153. int levelshift = level2shift(level + 1);
  154. if (pte_type(pte) != PTE_TYPE_BLOCK)
  155. panic("PTE %p (%llx) is not a block. Some driver code wants to "
  156. "modify dcache settings for an range not covered in "
  157. "mem_map.", pte, old_pte);
  158. new_table = create_table();
  159. debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
  160. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  161. new_table[i] = old_pte | (i << levelshift);
  162. /* Level 3 block PTEs have the table type */
  163. if ((level + 1) == 3)
  164. new_table[i] |= PTE_TYPE_TABLE;
  165. debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
  166. }
  167. /* Set the new table into effect */
  168. set_pte_table(pte, new_table);
  169. }
  170. /* Add one mm_region map entry to the page tables */
  171. static void add_map(struct mm_region *map)
  172. {
  173. u64 *pte;
  174. u64 virt = map->virt;
  175. u64 phys = map->phys;
  176. u64 size = map->size;
  177. u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
  178. u64 blocksize;
  179. int level;
  180. u64 *new_table;
  181. while (size) {
  182. pte = find_pte(virt, 0);
  183. if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
  184. debug("Creating table for virt 0x%llx\n", virt);
  185. new_table = create_table();
  186. set_pte_table(pte, new_table);
  187. }
  188. for (level = 1; level < 4; level++) {
  189. pte = find_pte(virt, level);
  190. if (!pte)
  191. panic("pte not found\n");
  192. blocksize = 1ULL << level2shift(level);
  193. debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
  194. virt, size, blocksize);
  195. if (size >= blocksize && !(virt & (blocksize - 1))) {
  196. /* Page fits, create block PTE */
  197. debug("Setting PTE %p to block virt=%llx\n",
  198. pte, virt);
  199. if (level == 3)
  200. *pte = phys | attrs | PTE_TYPE_PAGE;
  201. else
  202. *pte = phys | attrs;
  203. virt += blocksize;
  204. phys += blocksize;
  205. size -= blocksize;
  206. break;
  207. } else if (pte_type(pte) == PTE_TYPE_FAULT) {
  208. /* Page doesn't fit, create subpages */
  209. debug("Creating subtable for virt 0x%llx blksize=%llx\n",
  210. virt, blocksize);
  211. new_table = create_table();
  212. set_pte_table(pte, new_table);
  213. } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
  214. debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
  215. virt, blocksize);
  216. split_block(pte, level);
  217. }
  218. }
  219. }
  220. }
  221. enum pte_type {
  222. PTE_INVAL,
  223. PTE_BLOCK,
  224. PTE_LEVEL,
  225. };
  226. /*
  227. * This is a recursively called function to count the number of
  228. * page tables we need to cover a particular PTE range. If you
  229. * call this with level = -1 you basically get the full 48 bit
  230. * coverage.
  231. */
  232. static int count_required_pts(u64 addr, int level, u64 maxaddr)
  233. {
  234. int levelshift = level2shift(level);
  235. u64 levelsize = 1ULL << levelshift;
  236. u64 levelmask = levelsize - 1;
  237. u64 levelend = addr + levelsize;
  238. int r = 0;
  239. int i;
  240. enum pte_type pte_type = PTE_INVAL;
  241. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
  242. struct mm_region *map = &mem_map[i];
  243. u64 start = map->virt;
  244. u64 end = start + map->size;
  245. /* Check if the PTE would overlap with the map */
  246. if (max(addr, start) <= min(levelend, end)) {
  247. start = max(addr, start);
  248. end = min(levelend, end);
  249. /* We need a sub-pt for this level */
  250. if ((start & levelmask) || (end & levelmask)) {
  251. pte_type = PTE_LEVEL;
  252. break;
  253. }
  254. /* Lv0 can not do block PTEs, so do levels here too */
  255. if (level <= 0) {
  256. pte_type = PTE_LEVEL;
  257. break;
  258. }
  259. /* PTE is active, but fits into a block */
  260. pte_type = PTE_BLOCK;
  261. }
  262. }
  263. /*
  264. * Block PTEs at this level are already covered by the parent page
  265. * table, so we only need to count sub page tables.
  266. */
  267. if (pte_type == PTE_LEVEL) {
  268. int sublevel = level + 1;
  269. u64 sublevelsize = 1ULL << level2shift(sublevel);
  270. /* Account for the new sub page table ... */
  271. r = 1;
  272. /* ... and for all child page tables that one might have */
  273. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  274. r += count_required_pts(addr, sublevel, maxaddr);
  275. addr += sublevelsize;
  276. if (addr >= maxaddr) {
  277. /*
  278. * We reached the end of address space, no need
  279. * to look any further.
  280. */
  281. break;
  282. }
  283. }
  284. }
  285. return r;
  286. }
  287. /* Returns the estimated required size of all page tables */
  288. __weak u64 get_page_table_size(void)
  289. {
  290. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  291. u64 size = 0;
  292. u64 va_bits;
  293. int start_level = 0;
  294. get_tcr(0, NULL, &va_bits);
  295. if (va_bits < 39)
  296. start_level = 1;
  297. /* Account for all page tables we would need to cover our memory map */
  298. size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
  299. /*
  300. * We need to duplicate our page table once to have an emergency pt to
  301. * resort to when splitting page tables later on
  302. */
  303. size *= 2;
  304. /*
  305. * We may need to split page tables later on if dcache settings change,
  306. * so reserve up to 4 (random pick) page tables for that.
  307. */
  308. size += one_pt * 4;
  309. return size;
  310. }
  311. void setup_pgtables(void)
  312. {
  313. int i;
  314. if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
  315. panic("Page table pointer not setup.");
  316. /*
  317. * Allocate the first level we're on with invalidate entries.
  318. * If the starting level is 0 (va_bits >= 39), then this is our
  319. * Lv0 page table, otherwise it's the entry Lv1 page table.
  320. */
  321. create_table();
  322. /* Now add all MMU table entries one after another to the table */
  323. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  324. add_map(&mem_map[i]);
  325. }
  326. static void setup_all_pgtables(void)
  327. {
  328. u64 tlb_addr = gd->arch.tlb_addr;
  329. u64 tlb_size = gd->arch.tlb_size;
  330. /* Reset the fill ptr */
  331. gd->arch.tlb_fillptr = tlb_addr;
  332. /* Create normal system page tables */
  333. setup_pgtables();
  334. /* Create emergency page tables */
  335. gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
  336. (uintptr_t)gd->arch.tlb_addr;
  337. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  338. setup_pgtables();
  339. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  340. gd->arch.tlb_addr = tlb_addr;
  341. gd->arch.tlb_size = tlb_size;
  342. }
  343. /* to activate the MMU we need to set up virtual memory */
  344. __weak void mmu_setup(void)
  345. {
  346. int el;
  347. /* Set up page tables only once */
  348. if (!gd->arch.tlb_fillptr)
  349. setup_all_pgtables();
  350. el = current_el();
  351. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  352. MEMORY_ATTRIBUTES);
  353. /* enable the mmu */
  354. set_sctlr(get_sctlr() | CR_M);
  355. }
  356. /*
  357. * Performs a invalidation of the entire data cache at all levels
  358. */
  359. void invalidate_dcache_all(void)
  360. {
  361. __asm_invalidate_dcache_all();
  362. __asm_invalidate_l3_dcache();
  363. }
  364. /*
  365. * Performs a clean & invalidation of the entire data cache at all levels.
  366. * This function needs to be inline to avoid using stack.
  367. * __asm_flush_l3_dcache return status of timeout
  368. */
  369. inline void flush_dcache_all(void)
  370. {
  371. int ret;
  372. __asm_flush_dcache_all();
  373. ret = __asm_flush_l3_dcache();
  374. if (ret)
  375. debug("flushing dcache returns 0x%x\n", ret);
  376. else
  377. debug("flushing dcache successfully.\n");
  378. }
  379. #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
  380. /*
  381. * Invalidates range in all levels of D-cache/unified cache
  382. */
  383. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  384. {
  385. __asm_invalidate_dcache_range(start, stop);
  386. }
  387. /*
  388. * Flush range(clean & invalidate) from all levels of D-cache/unified cache
  389. */
  390. void flush_dcache_range(unsigned long start, unsigned long stop)
  391. {
  392. __asm_flush_dcache_range(start, stop);
  393. }
  394. #else
  395. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  396. {
  397. }
  398. void flush_dcache_range(unsigned long start, unsigned long stop)
  399. {
  400. }
  401. #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
  402. void dcache_enable(void)
  403. {
  404. /* The data cache is not active unless the mmu is enabled */
  405. if (!(get_sctlr() & CR_M)) {
  406. invalidate_dcache_all();
  407. __asm_invalidate_tlb_all();
  408. mmu_setup();
  409. }
  410. set_sctlr(get_sctlr() | CR_C);
  411. }
  412. void dcache_disable(void)
  413. {
  414. uint32_t sctlr;
  415. sctlr = get_sctlr();
  416. /* if cache isn't enabled no need to disable */
  417. if (!(sctlr & CR_C))
  418. return;
  419. set_sctlr(sctlr & ~(CR_C|CR_M));
  420. flush_dcache_all();
  421. __asm_invalidate_tlb_all();
  422. }
  423. int dcache_status(void)
  424. {
  425. return (get_sctlr() & CR_C) != 0;
  426. }
  427. u64 *__weak arch_get_page_table(void) {
  428. puts("No page table offset defined\n");
  429. return NULL;
  430. }
  431. static bool is_aligned(u64 addr, u64 size, u64 align)
  432. {
  433. return !(addr & (align - 1)) && !(size & (align - 1));
  434. }
  435. /* Use flag to indicate if attrs has more than d-cache attributes */
  436. static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
  437. {
  438. int levelshift = level2shift(level);
  439. u64 levelsize = 1ULL << levelshift;
  440. u64 *pte = find_pte(start, level);
  441. /* Can we can just modify the current level block PTE? */
  442. if (is_aligned(start, size, levelsize)) {
  443. if (flag) {
  444. *pte &= ~PMD_ATTRMASK;
  445. *pte |= attrs & PMD_ATTRMASK;
  446. } else {
  447. *pte &= ~PMD_ATTRINDX_MASK;
  448. *pte |= attrs & PMD_ATTRINDX_MASK;
  449. }
  450. debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
  451. return levelsize;
  452. }
  453. /* Unaligned or doesn't fit, maybe split block into table */
  454. debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
  455. /* Maybe we need to split the block into a table */
  456. if (pte_type(pte) == PTE_TYPE_BLOCK)
  457. split_block(pte, level);
  458. /* And then double-check it became a table or already is one */
  459. if (pte_type(pte) != PTE_TYPE_TABLE)
  460. panic("PTE %p (%llx) for addr=%llx should be a table",
  461. pte, *pte, start);
  462. /* Roll on to the next page table level */
  463. return 0;
  464. }
  465. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  466. enum dcache_option option)
  467. {
  468. u64 attrs = PMD_ATTRINDX(option >> 2);
  469. u64 real_start = start;
  470. u64 real_size = size;
  471. debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
  472. if (!gd->arch.tlb_emerg)
  473. panic("Emergency page table not setup.");
  474. /*
  475. * We can not modify page tables that we're currently running on,
  476. * so we first need to switch to the "emergency" page tables where
  477. * we can safely modify our primary page tables and then switch back
  478. */
  479. __asm_switch_ttbr(gd->arch.tlb_emerg);
  480. /*
  481. * Loop through the address range until we find a page granule that fits
  482. * our alignment constraints, then set it to the new cache attributes
  483. */
  484. while (size > 0) {
  485. int level;
  486. u64 r;
  487. for (level = 1; level < 4; level++) {
  488. /* Set d-cache attributes only */
  489. r = set_one_region(start, size, attrs, false, level);
  490. if (r) {
  491. /* PTE successfully replaced */
  492. size -= r;
  493. start += r;
  494. break;
  495. }
  496. }
  497. }
  498. /* We're done modifying page tables, switch back to our primary ones */
  499. __asm_switch_ttbr(gd->arch.tlb_addr);
  500. /*
  501. * Make sure there's nothing stale in dcache for a region that might
  502. * have caches off now
  503. */
  504. flush_dcache_range(real_start, real_start + real_size);
  505. }
  506. /*
  507. * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
  508. * The procecess is break-before-make. The target region will be marked as
  509. * invalid during the process of changing.
  510. */
  511. void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
  512. {
  513. int level;
  514. u64 r, size, start;
  515. start = addr;
  516. size = siz;
  517. /*
  518. * Loop through the address range until we find a page granule that fits
  519. * our alignment constraints, then set it to "invalid".
  520. */
  521. while (size > 0) {
  522. for (level = 1; level < 4; level++) {
  523. /* Set PTE to fault */
  524. r = set_one_region(start, size, PTE_TYPE_FAULT, true,
  525. level);
  526. if (r) {
  527. /* PTE successfully invalidated */
  528. size -= r;
  529. start += r;
  530. break;
  531. }
  532. }
  533. }
  534. flush_dcache_range(gd->arch.tlb_addr,
  535. gd->arch.tlb_addr + gd->arch.tlb_size);
  536. __asm_invalidate_tlb_all();
  537. /*
  538. * Loop through the address range until we find a page granule that fits
  539. * our alignment constraints, then set it to the new cache attributes
  540. */
  541. start = addr;
  542. size = siz;
  543. while (size > 0) {
  544. for (level = 1; level < 4; level++) {
  545. /* Set PTE to new attributes */
  546. r = set_one_region(start, size, attrs, true, level);
  547. if (r) {
  548. /* PTE successfully updated */
  549. size -= r;
  550. start += r;
  551. break;
  552. }
  553. }
  554. }
  555. flush_dcache_range(gd->arch.tlb_addr,
  556. gd->arch.tlb_addr + gd->arch.tlb_size);
  557. __asm_invalidate_tlb_all();
  558. }
  559. #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  560. /*
  561. * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
  562. * running however really wants to have dcache and the MMU active. Check that
  563. * everything is sane and give the developer a hint if it isn't.
  564. */
  565. #ifndef CONFIG_SPL_BUILD
  566. #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
  567. #endif
  568. void invalidate_dcache_all(void)
  569. {
  570. }
  571. void flush_dcache_all(void)
  572. {
  573. }
  574. void dcache_enable(void)
  575. {
  576. }
  577. void dcache_disable(void)
  578. {
  579. }
  580. int dcache_status(void)
  581. {
  582. return 0;
  583. }
  584. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  585. enum dcache_option option)
  586. {
  587. }
  588. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  589. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  590. void icache_enable(void)
  591. {
  592. invalidate_icache_all();
  593. set_sctlr(get_sctlr() | CR_I);
  594. }
  595. void icache_disable(void)
  596. {
  597. set_sctlr(get_sctlr() & ~CR_I);
  598. }
  599. int icache_status(void)
  600. {
  601. return (get_sctlr() & CR_I) != 0;
  602. }
  603. void invalidate_icache_all(void)
  604. {
  605. __asm_invalidate_icache_all();
  606. __asm_invalidate_l3_icache();
  607. }
  608. #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  609. void icache_enable(void)
  610. {
  611. }
  612. void icache_disable(void)
  613. {
  614. }
  615. int icache_status(void)
  616. {
  617. return 0;
  618. }
  619. void invalidate_icache_all(void)
  620. {
  621. }
  622. #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  623. /*
  624. * Enable dCache & iCache, whether cache is actually enabled
  625. * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  626. */
  627. void __weak enable_caches(void)
  628. {
  629. icache_enable();
  630. dcache_enable();
  631. }