generic.c 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/cache.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/mach-imx/sys_proto.h>
  18. #include <env.h>
  19. #include <netdev.h>
  20. #ifdef CONFIG_FSL_ESDHC_IMX
  21. #include <fsl_esdhc_imx.h>
  22. #endif
  23. #ifdef CONFIG_FSL_ESDHC_IMX
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #endif
  26. static char soc_type[] = "xx0";
  27. #ifdef CONFIG_MXC_OCOTP
  28. void enable_ocotp_clk(unsigned char enable)
  29. {
  30. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  31. u32 reg;
  32. reg = readl(&ccm->ccgr6);
  33. if (enable)
  34. reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
  35. else
  36. reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
  37. writel(reg, &ccm->ccgr6);
  38. }
  39. #endif
  40. static u32 get_mcu_main_clk(void)
  41. {
  42. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  43. u32 ccm_ccsr, ccm_cacrr, armclk_div;
  44. u32 sysclk_sel, pll_pfd_sel = 0;
  45. u32 freq = 0;
  46. ccm_ccsr = readl(&ccm->ccsr);
  47. sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
  48. sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
  49. ccm_cacrr = readl(&ccm->cacrr);
  50. armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
  51. armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
  52. armclk_div += 1;
  53. switch (sysclk_sel) {
  54. case 0:
  55. freq = FASE_CLK_FREQ;
  56. break;
  57. case 1:
  58. freq = SLOW_CLK_FREQ;
  59. break;
  60. case 2:
  61. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
  62. pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
  63. if (pll_pfd_sel == 0)
  64. freq = PLL2_MAIN_FREQ;
  65. else if (pll_pfd_sel == 1)
  66. freq = PLL2_PFD1_FREQ;
  67. else if (pll_pfd_sel == 2)
  68. freq = PLL2_PFD2_FREQ;
  69. else if (pll_pfd_sel == 3)
  70. freq = PLL2_PFD3_FREQ;
  71. else if (pll_pfd_sel == 4)
  72. freq = PLL2_PFD4_FREQ;
  73. break;
  74. case 3:
  75. freq = PLL2_MAIN_FREQ;
  76. break;
  77. case 4:
  78. pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
  79. pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
  80. if (pll_pfd_sel == 0)
  81. freq = PLL1_MAIN_FREQ;
  82. else if (pll_pfd_sel == 1)
  83. freq = PLL1_PFD1_FREQ;
  84. else if (pll_pfd_sel == 2)
  85. freq = PLL1_PFD2_FREQ;
  86. else if (pll_pfd_sel == 3)
  87. freq = PLL1_PFD3_FREQ;
  88. else if (pll_pfd_sel == 4)
  89. freq = PLL1_PFD4_FREQ;
  90. break;
  91. case 5:
  92. freq = PLL3_MAIN_FREQ;
  93. break;
  94. default:
  95. printf("unsupported system clock select\n");
  96. }
  97. return freq / armclk_div;
  98. }
  99. static u32 get_bus_clk(void)
  100. {
  101. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  102. u32 ccm_cacrr, busclk_div;
  103. ccm_cacrr = readl(&ccm->cacrr);
  104. busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
  105. busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
  106. busclk_div += 1;
  107. return get_mcu_main_clk() / busclk_div;
  108. }
  109. static u32 get_ipg_clk(void)
  110. {
  111. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  112. u32 ccm_cacrr, ipgclk_div;
  113. ccm_cacrr = readl(&ccm->cacrr);
  114. ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
  115. ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
  116. ipgclk_div += 1;
  117. return get_bus_clk() / ipgclk_div;
  118. }
  119. static u32 get_uart_clk(void)
  120. {
  121. return get_ipg_clk();
  122. }
  123. static u32 get_sdhc_clk(void)
  124. {
  125. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  126. u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
  127. u32 freq = 0;
  128. ccm_cscmr1 = readl(&ccm->cscmr1);
  129. sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
  130. sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
  131. ccm_cscdr2 = readl(&ccm->cscdr2);
  132. sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
  133. sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
  134. sdhc_clk_div += 1;
  135. switch (sdhc_clk_sel) {
  136. case 0:
  137. freq = PLL3_MAIN_FREQ;
  138. break;
  139. case 1:
  140. freq = PLL3_PFD3_FREQ;
  141. break;
  142. case 2:
  143. freq = PLL1_PFD3_FREQ;
  144. break;
  145. case 3:
  146. freq = get_bus_clk();
  147. break;
  148. }
  149. return freq / sdhc_clk_div;
  150. }
  151. u32 get_fec_clk(void)
  152. {
  153. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  154. u32 ccm_cscmr2, rmii_clk_sel;
  155. u32 freq = 0;
  156. ccm_cscmr2 = readl(&ccm->cscmr2);
  157. rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
  158. rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
  159. switch (rmii_clk_sel) {
  160. case 0:
  161. freq = ENET_EXTERNAL_CLK;
  162. break;
  163. case 1:
  164. freq = AUDIO_EXTERNAL_CLK;
  165. break;
  166. case 2:
  167. freq = PLL5_MAIN_FREQ;
  168. break;
  169. case 3:
  170. freq = PLL5_MAIN_FREQ / 2;
  171. break;
  172. }
  173. return freq;
  174. }
  175. static u32 get_i2c_clk(void)
  176. {
  177. return get_ipg_clk();
  178. }
  179. static u32 get_dspi_clk(void)
  180. {
  181. return get_ipg_clk();
  182. }
  183. u32 get_lpuart_clk(void)
  184. {
  185. return get_uart_clk();
  186. }
  187. unsigned int mxc_get_clock(enum mxc_clock clk)
  188. {
  189. switch (clk) {
  190. case MXC_ARM_CLK:
  191. return get_mcu_main_clk();
  192. case MXC_BUS_CLK:
  193. return get_bus_clk();
  194. case MXC_IPG_CLK:
  195. return get_ipg_clk();
  196. case MXC_UART_CLK:
  197. return get_uart_clk();
  198. case MXC_ESDHC_CLK:
  199. return get_sdhc_clk();
  200. case MXC_FEC_CLK:
  201. return get_fec_clk();
  202. case MXC_I2C_CLK:
  203. return get_i2c_clk();
  204. case MXC_DSPI_CLK:
  205. return get_dspi_clk();
  206. default:
  207. break;
  208. }
  209. return -1;
  210. }
  211. /* Dump some core clocks */
  212. int do_vf610_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  213. char *const argv[])
  214. {
  215. printf("\n");
  216. printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  217. printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
  218. printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
  219. return 0;
  220. }
  221. U_BOOT_CMD(
  222. clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
  223. "display clocks",
  224. ""
  225. );
  226. #ifdef CONFIG_FEC_MXC
  227. __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  228. {
  229. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  230. struct fuse_bank *bank = &ocotp->bank[4];
  231. struct fuse_bank4_regs *fuse =
  232. (struct fuse_bank4_regs *)bank->fuse_regs;
  233. u32 value = readl(&fuse->mac_addr0);
  234. mac[0] = (value >> 8);
  235. mac[1] = value;
  236. value = readl(&fuse->mac_addr1);
  237. mac[2] = value >> 24;
  238. mac[3] = value >> 16;
  239. mac[4] = value >> 8;
  240. mac[5] = value;
  241. }
  242. #endif
  243. u32 get_cpu_rev(void)
  244. {
  245. return MXC_CPU_VF610 << 12;
  246. }
  247. #if defined(CONFIG_DISPLAY_CPUINFO)
  248. static char *get_reset_cause(void)
  249. {
  250. u32 cause;
  251. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  252. cause = readl(&src_regs->srsr);
  253. writel(cause, &src_regs->srsr);
  254. if (cause & SRC_SRSR_POR_RST)
  255. return "POWER ON RESET";
  256. else if (cause & SRC_SRSR_WDOG_A5)
  257. return "WDOG A5";
  258. else if (cause & SRC_SRSR_WDOG_M4)
  259. return "WDOG M4";
  260. else if (cause & SRC_SRSR_JTAG_RST)
  261. return "JTAG HIGH-Z";
  262. else if (cause & SRC_SRSR_SW_RST)
  263. return "SW RESET";
  264. else if (cause & SRC_SRSR_RESETB)
  265. return "EXTERNAL RESET";
  266. else
  267. return "unknown reset";
  268. }
  269. int print_cpuinfo(void)
  270. {
  271. printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
  272. soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
  273. printf("Reset cause: %s\n", get_reset_cause());
  274. return 0;
  275. }
  276. #endif
  277. int arch_cpu_init(void)
  278. {
  279. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  280. soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
  281. soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
  282. return 0;
  283. }
  284. #ifdef CONFIG_ARCH_MISC_INIT
  285. int arch_misc_init(void)
  286. {
  287. char soc[6];
  288. strcpy(soc, "vf");
  289. strcat(soc, soc_type);
  290. env_set("soc", soc);
  291. return 0;
  292. }
  293. #endif
  294. int cpu_eth_init(struct bd_info *bis)
  295. {
  296. int rc = -ENODEV;
  297. #if defined(CONFIG_FEC_MXC)
  298. rc = fecmxc_initialize(bis);
  299. #endif
  300. return rc;
  301. }
  302. #ifdef CONFIG_FSL_ESDHC_IMX
  303. int cpu_mmc_init(struct bd_info *bis)
  304. {
  305. return fsl_esdhc_mmc_init(bis);
  306. }
  307. #endif
  308. int get_clocks(void)
  309. {
  310. #ifdef CONFIG_FSL_ESDHC_IMX
  311. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  312. #endif
  313. return 0;
  314. }
  315. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  316. void enable_caches(void)
  317. {
  318. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  319. enum dcache_option option = DCACHE_WRITETHROUGH;
  320. #else
  321. enum dcache_option option = DCACHE_WRITEBACK;
  322. #endif
  323. dcache_enable();
  324. icache_enable();
  325. /* Enable caching on OCRAM */
  326. mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
  327. }
  328. #endif
  329. #ifdef CONFIG_SYS_I2C_MXC
  330. /* i2c_num can be from 0 - 3 */
  331. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  332. {
  333. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  334. switch (i2c_num) {
  335. case 0:
  336. clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,
  337. CCM_CCGR4_I2C0_CTRL_MASK);
  338. case 2:
  339. clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
  340. CCM_CCGR10_I2C2_CTRL_MASK);
  341. break;
  342. default:
  343. return -EINVAL;
  344. }
  345. return 0;
  346. }
  347. #endif