pinmux.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <asm/io.h>
  7. #include <asm/arch/stv0991_creg.h>
  8. #include <asm/arch/stv0991_periph.h>
  9. #include <asm/arch/hardware.h>
  10. static struct stv0991_creg *const stv0991_creg = \
  11. (struct stv0991_creg *)CREG_BASE_ADDR;
  12. int stv0991_pinmux_config(int peripheral)
  13. {
  14. switch (peripheral) {
  15. case UART_GPIOC_30_31:
  16. /* SSDA/SSCL pad muxing to UART Rx/Dx */
  17. writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
  18. CFG_GPIOC_31_UART_RX,
  19. &stv0991_creg->mux12);
  20. writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
  21. CFG_GPIOC_30_UART_TX,
  22. &stv0991_creg->mux12);
  23. /* SSDA/SSCL pad config to push pull*/
  24. writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
  25. CFG_GPIOC_31_MODE_PP,
  26. &stv0991_creg->cfg_pad6);
  27. writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
  28. CFG_GPIOC_30_MODE_HIGH,
  29. &stv0991_creg->cfg_pad6);
  30. break;
  31. case UART_GPIOB_16_17:
  32. /* ethernet rx_6/7 to UART Rx/Dx */
  33. writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
  34. CFG_GPIOB_17_UART_RX,
  35. &stv0991_creg->mux7);
  36. writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
  37. CFG_GPIOB_16_UART_TX,
  38. &stv0991_creg->mux7);
  39. break;
  40. case ETH_GPIOB_10_31_C_0_4:
  41. writel(readl(&stv0991_creg->mux6) & 0x000000FF,
  42. &stv0991_creg->mux6);
  43. writel(0x00000000, &stv0991_creg->mux7);
  44. writel(0x00000000, &stv0991_creg->mux8);
  45. writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
  46. &stv0991_creg->mux9);
  47. /* Ethernet Voltage configuration to 1.8V*/
  48. writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
  49. ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
  50. writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
  51. ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
  52. break;
  53. case QSPI_CS_CLK_PAD:
  54. writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
  55. CFG_FLASH_CS_NC, &stv0991_creg->mux13);
  56. writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
  57. CFG_FLASH_CLK, &stv0991_creg->mux13);
  58. default:
  59. break;
  60. }
  61. return 0;
  62. }