clock.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <asm/io.h>
  7. #include <asm/arch/hardware.h>
  8. #include <asm/arch/stv0991_cgu.h>
  9. #include<asm/arch/stv0991_periph.h>
  10. static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
  11. (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
  12. void enable_pll1(void)
  13. {
  14. /* pll1 already configured for 1000Mhz, just need to enable it */
  15. writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
  16. &stv0991_cgu_regs->pll1_ctrl);
  17. }
  18. void clock_setup(int peripheral)
  19. {
  20. switch (peripheral) {
  21. case UART_CLOCK_CFG:
  22. writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
  23. break;
  24. case ETH_CLOCK_CFG:
  25. enable_pll1();
  26. writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
  27. /* Clock selection for ethernet tx_clk & rx_clk*/
  28. writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
  29. | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
  30. break;
  31. case QSPI_CLOCK_CFG:
  32. writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
  33. break;
  34. default:
  35. break;
  36. }
  37. }