cpu.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Nexell
  4. * Hyunseok, Jung <hsjung@nexell.co.kr>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <asm/system.h>
  9. #include <asm/cache.h>
  10. #include <asm/global_data.h>
  11. #include <asm/sections.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/nexell.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/reset.h>
  16. #include <asm/arch/tieoff.h>
  17. #include <cpu_func.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #ifndef CONFIG_ARCH_CPU_INIT
  21. #error must be define the macro "CONFIG_ARCH_CPU_INIT"
  22. #endif
  23. void s_init(void)
  24. {
  25. }
  26. static void cpu_soc_init(void)
  27. {
  28. /*
  29. * NOTE> ALIVE Power Gate must enable for Alive register access.
  30. * must be clear wfi jump address
  31. */
  32. writel(1, ALIVEPWRGATEREG);
  33. writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
  34. /* write 0xf0 on alive scratchpad reg for boot success check */
  35. writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
  36. /* set l2 cache tieoff */
  37. nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
  38. nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
  39. }
  40. #ifdef CONFIG_PL011_SERIAL
  41. static void serial_device_init(void)
  42. {
  43. char dev[10];
  44. int id;
  45. sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
  46. id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
  47. struct clk *clk = clk_get((const char *)dev);
  48. /* reset control: Low active ___|--- */
  49. nx_rstcon_setrst(id, RSTCON_ASSERT);
  50. udelay(10);
  51. nx_rstcon_setrst(id, RSTCON_NEGATE);
  52. udelay(10);
  53. /* set clock */
  54. clk_disable(clk);
  55. clk_set_rate(clk, CONFIG_PL011_CLOCK);
  56. clk_enable(clk);
  57. }
  58. #endif
  59. int arch_cpu_init(void)
  60. {
  61. flush_dcache_all();
  62. cpu_soc_init();
  63. clk_init();
  64. if (IS_ENABLED(CONFIG_PL011_SERIAL))
  65. serial_device_init();
  66. return 0;
  67. }
  68. #if defined(CONFIG_DISPLAY_CPUINFO)
  69. int print_cpuinfo(void)
  70. {
  71. return 0;
  72. }
  73. #endif
  74. void reset_cpu(ulong ignored)
  75. {
  76. void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
  77. const u32 sw_rst_enb_bitpos = 3;
  78. const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
  79. const u32 sw_rst_bitpos = 12;
  80. const u32 sw_rst_mask = 1 << sw_rst_bitpos;
  81. int pwrcont = 0x224;
  82. int pwrmode = 0x228;
  83. u32 read_value;
  84. read_value = readl((void *)(clkpwr_reg + pwrcont));
  85. read_value &= ~sw_rst_enb_mask;
  86. read_value |= 1 << sw_rst_enb_bitpos;
  87. writel(read_value, (void *)(clkpwr_reg + pwrcont));
  88. writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
  89. }
  90. void enable_caches(void)
  91. {
  92. /* Enable D-cache. I-cache is already enabled in start.S */
  93. dcache_enable();
  94. }
  95. #if defined(CONFIG_ARCH_MISC_INIT)
  96. int arch_misc_init(void)
  97. {
  98. return 0;
  99. }
  100. #endif /* CONFIG_ARCH_MISC_INIT */