fdt.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <net.h>
  8. #include <asm/global_data.h>
  9. #include <linux/libfdt.h>
  10. #include <fdt_support.h>
  11. #include <asm/io.h>
  12. #include <asm/processor.h>
  13. #include <asm/arch/clock.h>
  14. #include <linux/ctype.h>
  15. #ifdef CONFIG_FSL_ESDHC
  16. #include <fsl_esdhc.h>
  17. #endif
  18. #include <tsec.h>
  19. #include <asm/arch/immap_ls102xa.h>
  20. #include <fsl_sec.h>
  21. #include <dm.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. void ft_fixup_enet_phy_connect_type(void *fdt)
  24. {
  25. #ifdef CONFIG_DM_ETH
  26. struct udevice *dev;
  27. #else
  28. struct eth_device *dev;
  29. #endif
  30. struct tsec_private *priv;
  31. const char *enet_path, *phy_path;
  32. char enet[16];
  33. char phy[16];
  34. int phy_node;
  35. int i = 0;
  36. uint32_t ph;
  37. #ifdef CONFIG_DM_ETH
  38. char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  39. "ethernet@2d90000" };
  40. #else
  41. char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  42. #endif
  43. for (; i < ARRAY_SIZE(name); i++) {
  44. dev = eth_get_dev_by_name(name[i]);
  45. if (dev) {
  46. sprintf(enet, "ethernet%d", i);
  47. sprintf(phy, "enet%d_rgmii_phy", i);
  48. } else {
  49. continue;
  50. }
  51. #ifdef CONFIG_DM_ETH
  52. priv = dev_get_priv(dev);
  53. #else
  54. priv = dev->priv;
  55. #endif
  56. if (priv->flags & TSEC_SGMII)
  57. continue;
  58. enet_path = fdt_get_alias(fdt, enet);
  59. if (!enet_path)
  60. continue;
  61. phy_path = fdt_get_alias(fdt, phy);
  62. if (!phy_path)
  63. continue;
  64. phy_node = fdt_path_offset(fdt, phy_path);
  65. if (phy_node < 0)
  66. continue;
  67. ph = fdt_create_phandle(fdt, phy_node);
  68. if (ph)
  69. do_fixup_by_path_u32(fdt, enet_path,
  70. "phy-handle", ph, 1);
  71. do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  72. phy_string_for_interface(
  73. PHY_INTERFACE_MODE_RGMII_ID),
  74. strlen(phy_string_for_interface(
  75. PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  76. 1);
  77. }
  78. }
  79. void ft_cpu_setup(void *blob, struct bd_info *bd)
  80. {
  81. int off;
  82. int val;
  83. const char *sysclk_path;
  84. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  85. unsigned int svr;
  86. svr = in_be32(&gur->svr);
  87. unsigned long busclk = get_bus_freq(0);
  88. /* delete crypto node if not on an E-processor */
  89. if (!IS_E_PROCESSOR(svr))
  90. fdt_fixup_crypto_node(blob, 0);
  91. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  92. else {
  93. ccsr_sec_t __iomem *sec;
  94. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  95. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  96. }
  97. #endif
  98. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  99. while (off != -FDT_ERR_NOTFOUND) {
  100. val = gd->cpu_clk;
  101. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  102. off = fdt_node_offset_by_prop_value(blob, off,
  103. "device_type", "cpu", 4);
  104. }
  105. do_fixup_by_prop_u32(blob, "device_type", "soc",
  106. 4, "bus-frequency", busclk, 1);
  107. ft_fixup_enet_phy_connect_type(blob);
  108. #ifdef CONFIG_SYS_NS16550
  109. do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
  110. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  111. #endif
  112. sysclk_path = fdt_get_alias(blob, "sysclk");
  113. if (sysclk_path)
  114. do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
  115. CONFIG_SYS_CLK_FREQ, 1);
  116. do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
  117. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  118. #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
  119. #define UBOOT_HEAD_LEN 0x1000
  120. /*
  121. * Reserved memory in SD boot deep sleep case.
  122. * Second stage uboot binary and malloc space should be reserved.
  123. * If the memory they occupied has not been reserved, then this
  124. * space would be used by kernel and overwritten in uboot when
  125. * deep sleep resume, which cause deep sleep failed.
  126. * Since second uboot binary has a head, that space need to be
  127. * reserved either(assuming its size is less than 0x1000).
  128. */
  129. off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
  130. CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
  131. UBOOT_HEAD_LEN);
  132. if (off < 0)
  133. printf("Failed to reserve memory for SD boot deep sleep: %s\n",
  134. fdt_strerror(off));
  135. #endif
  136. #if defined(CONFIG_FSL_ESDHC)
  137. fdt_fixup_esdhc(blob, bd);
  138. #endif
  139. /*
  140. * platform bus clock = system bus clock/2
  141. * Here busclk = system bus clock
  142. * We are using the platform bus clock as 1588 Timer reference
  143. * clock source select
  144. */
  145. do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
  146. "timer-frequency", busclk / 2, 1);
  147. /*
  148. * clock-freq should change to clock-frequency and
  149. * flexcan-v1.0 should change to p1010-flexcan respectively
  150. * in the future.
  151. */
  152. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  153. "clock_freq", busclk / 2, 1);
  154. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  155. "clock-frequency", busclk / 2, 1);
  156. do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
  157. "clock-frequency", busclk / 2, 1);
  158. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  159. off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
  160. CONFIG_SYS_IFC_ADDR);
  161. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  162. #else
  163. off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
  164. QSPI0_BASE_ADDR);
  165. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  166. off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
  167. DSPI1_BASE_ADDR);
  168. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  169. #endif
  170. }