cpu.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <vsprintf.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/immap_ls102xa.h>
  14. #include <asm/cache.h>
  15. #include <asm/system.h>
  16. #include <tsec.h>
  17. #include <netdev.h>
  18. #include <fsl_esdhc.h>
  19. #include <config.h>
  20. #include <fsl_wdog.h>
  21. #include <linux/delay.h>
  22. #include "fsl_epu.h"
  23. #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
  24. #define DCSR_RCPM2_CPMFSMCR0 0x400
  25. #define DCSR_RCPM2_CPMFSMSR0 0x404
  26. #define DCSR_RCPM2_CPMFSMCR1 0x414
  27. #define DCSR_RCPM2_CPMFSMSR1 0x418
  28. #define CPMFSMSR_FSM_STATE_MASK 0x7f
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  31. /*
  32. * Bit[1] of the descriptor indicates the descriptor type,
  33. * and bit[0] indicates whether the descriptor is valid.
  34. */
  35. #define PMD_TYPE_TABLE 0x3
  36. #define PMD_TYPE_SECT 0x1
  37. /* AttrIndx[2:0] */
  38. #define PMD_ATTRINDX(t) ((t) << 2)
  39. /* Section */
  40. #define PMD_SECT_AF (1 << 10)
  41. #define BLOCK_SIZE_L1 (1UL << 30)
  42. #define BLOCK_SIZE_L2 (1UL << 21)
  43. /* TTBCR flags */
  44. #define TTBCR_EAE (1 << 31)
  45. #define TTBCR_T0SZ(x) ((x) << 0)
  46. #define TTBCR_T1SZ(x) ((x) << 16)
  47. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  48. #define TTBCR_IRGN0_NC (0 << 8)
  49. #define TTBCR_IRGN0_WBWA (1 << 8)
  50. #define TTBCR_IRGN0_WT (2 << 8)
  51. #define TTBCR_IRGN0_WBNWA (3 << 8)
  52. #define TTBCR_IRGN0_MASK (3 << 8)
  53. #define TTBCR_ORGN0_NC (0 << 10)
  54. #define TTBCR_ORGN0_WBWA (1 << 10)
  55. #define TTBCR_ORGN0_WT (2 << 10)
  56. #define TTBCR_ORGN0_WBNWA (3 << 10)
  57. #define TTBCR_ORGN0_MASK (3 << 10)
  58. #define TTBCR_SHARED_NON (0 << 12)
  59. #define TTBCR_SHARED_OUTER (2 << 12)
  60. #define TTBCR_SHARED_INNER (3 << 12)
  61. #define TTBCR_EPD0 (0 << 7)
  62. #define TTBCR (TTBCR_SHARED_NON | \
  63. TTBCR_ORGN0_NC | \
  64. TTBCR_IRGN0_NC | \
  65. TTBCR_USING_TTBR0 | \
  66. TTBCR_EAE)
  67. /*
  68. * Memory region attributes for LPAE (defined in pgtable):
  69. *
  70. * n = AttrIndx[2:0]
  71. *
  72. * n MAIR
  73. * UNCACHED 000 00000000
  74. * BUFFERABLE 001 01000100
  75. * DEV_WC 001 01000100
  76. * WRITETHROUGH 010 10101010
  77. * WRITEBACK 011 11101110
  78. * DEV_CACHED 011 11101110
  79. * DEV_SHARED 100 00000100
  80. * DEV_NONSHARED 100 00000100
  81. * unused 101
  82. * unused 110
  83. * WRITEALLOC 111 11111111
  84. */
  85. #define MT_MAIR0 0xeeaa4400
  86. #define MT_MAIR1 0xff000004
  87. #define MT_STRONLY_ORDER 0
  88. #define MT_NORMAL_NC 1
  89. #define MT_DEVICE_MEM 4
  90. #define MT_NORMAL 7
  91. /* The phy_addr must be aligned to 4KB */
  92. static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
  93. {
  94. u32 value = phy_addr | PMD_TYPE_TABLE;
  95. page_table[2 * index] = value;
  96. page_table[2 * index + 1] = 0;
  97. }
  98. /* The phy_addr must be aligned to 4KB */
  99. static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
  100. u32 memory_type)
  101. {
  102. u64 value;
  103. value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
  104. value |= PMD_ATTRINDX(memory_type);
  105. page_table[2 * index] = value & 0xFFFFFFFF;
  106. page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
  107. }
  108. /*
  109. * Start MMU after DDR is available, we create MMU table in DRAM.
  110. * The base address of TTLB is gd->arch.tlb_addr. We use two
  111. * levels of translation tables here to cover 40-bit address space.
  112. *
  113. * The TTLBs are located at PHY 2G~4G.
  114. *
  115. * VA mapping:
  116. *
  117. * ------- <---- 0GB
  118. * | |
  119. * | |
  120. * |-------| <---- 0x24000000
  121. * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
  122. * |-------| <---- 0x300000000
  123. * | |
  124. * |-------| <---- 0x34000000
  125. * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
  126. * |-------| <---- 0x40000000
  127. * | |
  128. * |-------| <---- 0x80000000 DDR0 space start
  129. * |\\\\\\\|
  130. *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
  131. * |\\\\\\\|
  132. * ------- <---- 4GB DDR0 space end
  133. */
  134. static void mmu_setup(void)
  135. {
  136. u32 *level0_table = (u32 *)gd->arch.tlb_addr;
  137. u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
  138. u64 va_start = 0;
  139. u32 reg;
  140. int i;
  141. /* Level 0 Table 2-3 are used to map DDR */
  142. set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
  143. set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
  144. /* Level 0 Table 1 is used to map device */
  145. set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
  146. /* Level 0 Table 0 is used to map device including PCIe MEM */
  147. set_pgtable(level0_table, 0, (u32)level1_table);
  148. /* Level 1 has 512 entries */
  149. for (i = 0; i < 512; i++) {
  150. /* Mapping for PCIe 1 */
  151. if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
  152. va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
  153. CONFIG_SYS_PCIE_MMAP_SIZE))
  154. set_pgsection(level1_table, i,
  155. CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
  156. MT_DEVICE_MEM);
  157. /* Mapping for PCIe 2 */
  158. else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
  159. va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
  160. CONFIG_SYS_PCIE_MMAP_SIZE))
  161. set_pgsection(level1_table, i,
  162. CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
  163. MT_DEVICE_MEM);
  164. else
  165. set_pgsection(level1_table, i,
  166. va_start,
  167. MT_DEVICE_MEM);
  168. va_start += BLOCK_SIZE_L2;
  169. }
  170. asm volatile("dsb sy;isb");
  171. asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
  172. : : "r" (TTBCR) : "memory");
  173. asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
  174. : : "r" ((u32)level0_table), "r" (0) : "memory");
  175. asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
  176. : : "r" (MT_MAIR0) : "memory");
  177. asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
  178. : : "r" (MT_MAIR1) : "memory");
  179. /* Set the access control to all-supervisor */
  180. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  181. : : "r" (~0));
  182. /* Enable the mmu */
  183. reg = get_cr();
  184. set_cr(reg | CR_M);
  185. }
  186. /*
  187. * This function is called from lib/board.c. It recreates MMU
  188. * table in main memory. MMU and i/d-cache are enabled here.
  189. */
  190. void enable_caches(void)
  191. {
  192. /* Invalidate all TLB */
  193. mmu_page_table_flush(gd->arch.tlb_addr,
  194. gd->arch.tlb_addr + gd->arch.tlb_size);
  195. /* Set up and enable mmu */
  196. mmu_setup();
  197. /* Invalidate & Enable d-cache */
  198. invalidate_dcache_all();
  199. set_cr(get_cr() | CR_C);
  200. }
  201. #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  202. uint get_svr(void)
  203. {
  204. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  205. return in_be32(&gur->svr);
  206. }
  207. #if defined(CONFIG_DISPLAY_CPUINFO)
  208. int print_cpuinfo(void)
  209. {
  210. char buf1[32], buf2[32];
  211. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  212. unsigned int svr, major, minor, ver, i;
  213. svr = in_be32(&gur->svr);
  214. major = SVR_MAJ(svr);
  215. minor = SVR_MIN(svr);
  216. puts("CPU: Freescale LayerScape ");
  217. ver = SVR_SOC_VER(svr);
  218. switch (ver) {
  219. case SOC_VER_SLS1020:
  220. puts("SLS1020");
  221. break;
  222. case SOC_VER_LS1020:
  223. puts("LS1020");
  224. break;
  225. case SOC_VER_LS1021:
  226. puts("LS1021");
  227. break;
  228. case SOC_VER_LS1022:
  229. puts("LS1022");
  230. break;
  231. default:
  232. puts("Unknown");
  233. break;
  234. }
  235. if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
  236. puts("E");
  237. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  238. puts("Clock Configuration:");
  239. printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
  240. printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
  241. printf("DDR:%-4s MHz (%s MT/s data rate), ",
  242. strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
  243. puts("\n");
  244. /* Display the RCW, so that no one gets confused as to what RCW
  245. * we're actually using for this boot.
  246. */
  247. puts("Reset Configuration Word (RCW):");
  248. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  249. u32 rcw = in_be32(&gur->rcwsr[i]);
  250. if ((i % 4) == 0)
  251. printf("\n %08x:", i * 4);
  252. printf(" %08x", rcw);
  253. }
  254. puts("\n");
  255. return 0;
  256. }
  257. #endif
  258. #ifdef CONFIG_FSL_ESDHC
  259. int cpu_mmc_init(struct bd_info *bis)
  260. {
  261. return fsl_esdhc_mmc_init(bis);
  262. }
  263. #endif
  264. int cpu_eth_init(struct bd_info *bis)
  265. {
  266. #if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
  267. tsec_standard_init(bis);
  268. #endif
  269. return 0;
  270. }
  271. int arch_cpu_init(void)
  272. {
  273. void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  274. void *rcpm2_base =
  275. (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
  276. struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  277. u32 state;
  278. /*
  279. * The RCPM FSM state may not be reset after power-on.
  280. * So, reset them.
  281. */
  282. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
  283. CPMFSMSR_FSM_STATE_MASK;
  284. if (state != 0) {
  285. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
  286. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
  287. }
  288. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
  289. CPMFSMSR_FSM_STATE_MASK;
  290. if (state != 0) {
  291. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
  292. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
  293. }
  294. /*
  295. * After wakeup from deep sleep, Clear EPU registers
  296. * as early as possible to prevent from possible issue.
  297. * It's also safe to clear at normal boot.
  298. */
  299. fsl_epu_clean(epu_base);
  300. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
  301. return 0;
  302. }
  303. #ifdef CONFIG_ARMV7_NONSEC
  304. /* Set the address at which the secondary core starts from.*/
  305. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  306. {
  307. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  308. out_be32(&gur->scratchrw[0], addr);
  309. }
  310. /* Release the secondary core from holdoff state and kick it */
  311. void smp_kick_all_cpus(void)
  312. {
  313. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  314. out_be32(&gur->brrl, 0x2);
  315. /*
  316. * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
  317. * So add a delay to wait bootrom execute WFE.
  318. */
  319. udelay(1);
  320. asm volatile("sev");
  321. }
  322. #endif
  323. void reset_cpu(ulong addr)
  324. {
  325. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  326. clrbits_be16(&wdog->wcr, WCR_SRS);
  327. while (1) {
  328. /*
  329. * Let the watchdog trigger
  330. */
  331. }
  332. }
  333. void arch_preboot_os(void)
  334. {
  335. unsigned long ctrl;
  336. /* Disable PL1 Physical Timer */
  337. asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
  338. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  339. asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
  340. }