mxs.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 common code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <cpu_func.h>
  14. #include <hang.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <asm/global_data.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/mach-imx/dma.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/iomux.h>
  25. #include <asm/arch/imx-regs.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <linux/compiler.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
  30. __weak void lowlevel_init(void) {}
  31. void reset_cpu(ulong ignored) __attribute__((noreturn));
  32. void reset_cpu(ulong ignored)
  33. {
  34. struct mxs_rtc_regs *rtc_regs =
  35. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  36. struct mxs_lcdif_regs *lcdif_regs =
  37. (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  38. /*
  39. * Shut down the LCD controller as it interferes with BootROM boot mode
  40. * pads sampling.
  41. */
  42. writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
  43. /* Wait 1 uS before doing the actual watchdog reset */
  44. writel(1, &rtc_regs->hw_rtc_watchdog);
  45. writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
  46. /* Endless loop, reset will exit from here */
  47. for (;;)
  48. ;
  49. }
  50. /*
  51. * This function will craft a jumptable at 0x0 which will redirect interrupt
  52. * vectoring to proper location of U-Boot in RAM.
  53. *
  54. * The structure of the jumptable will be as follows:
  55. * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
  56. * <destination address> ... for each previous ldr, thus also repeated 8 times
  57. *
  58. * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
  59. * offset 0x18 from current value of PC register. Note that PC is already
  60. * incremented by 4 when computing the offset, so the effective offset is
  61. * actually 0x20, this the associated <destination address>. Loading the PC
  62. * register with an address performs a jump to that address.
  63. */
  64. void mx28_fixup_vt(uint32_t start_addr)
  65. {
  66. /* ldr pc, [pc, #0x18] */
  67. const uint32_t ldr_pc = 0xe59ff018;
  68. /* Jumptable location is 0x0 */
  69. uint32_t *vt = (uint32_t *)0x0;
  70. int i;
  71. for (i = 0; i < 8; i++) {
  72. /* cppcheck-suppress nullPointer */
  73. vt[i] = ldr_pc;
  74. /* cppcheck-suppress nullPointer */
  75. vt[i + 8] = start_addr + (4 * i);
  76. }
  77. }
  78. #ifdef CONFIG_ARCH_MISC_INIT
  79. int arch_misc_init(void)
  80. {
  81. mx28_fixup_vt(gd->relocaddr);
  82. return 0;
  83. }
  84. #endif
  85. int arch_cpu_init(void)
  86. {
  87. struct mxs_clkctrl_regs *clkctrl_regs =
  88. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  89. extern uint32_t _start;
  90. mx28_fixup_vt((uint32_t)&_start);
  91. /*
  92. * Enable NAND clock
  93. */
  94. /* Set bypass bit */
  95. writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
  96. &clkctrl_regs->hw_clkctrl_clkseq_set);
  97. /* Set GPMI clock to ref_xtal / 1 */
  98. clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
  99. while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
  100. ;
  101. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
  102. CLKCTRL_GPMI_DIV_MASK, 1);
  103. udelay(1000);
  104. /*
  105. * Configure GPIO unit
  106. */
  107. mxs_gpio_init();
  108. #ifdef CONFIG_APBH_DMA
  109. /* Start APBH DMA */
  110. mxs_dma_init();
  111. #endif
  112. return 0;
  113. }
  114. u32 get_cpu_rev(void)
  115. {
  116. struct mxs_digctl_regs *digctl_regs =
  117. (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
  118. uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
  119. switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
  120. case HW_DIGCTL_CHIPID_MX23:
  121. switch (rev) {
  122. case 0x0:
  123. case 0x1:
  124. case 0x2:
  125. case 0x3:
  126. case 0x4:
  127. return (MXC_CPU_MX23 << 12) | (rev + 0x10);
  128. default:
  129. return 0;
  130. }
  131. case HW_DIGCTL_CHIPID_MX28:
  132. switch (rev) {
  133. case 0x1:
  134. return (MXC_CPU_MX28 << 12) | 0x12;
  135. default:
  136. return 0;
  137. }
  138. default:
  139. return 0;
  140. }
  141. }
  142. #if defined(CONFIG_DISPLAY_CPUINFO)
  143. const char *get_imx_type(u32 imxtype)
  144. {
  145. switch (imxtype) {
  146. case MXC_CPU_MX23:
  147. return "23";
  148. case MXC_CPU_MX28:
  149. return "28";
  150. default:
  151. return "??";
  152. }
  153. }
  154. int print_cpuinfo(void)
  155. {
  156. u32 cpurev;
  157. struct mxs_spl_data *data = MXS_SPL_DATA;
  158. cpurev = get_cpu_rev();
  159. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  160. get_imx_type((cpurev & 0xFF000) >> 12),
  161. (cpurev & 0x000F0) >> 4,
  162. (cpurev & 0x0000F) >> 0,
  163. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  164. printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
  165. return 0;
  166. }
  167. #endif
  168. int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  169. char *const argv[])
  170. {
  171. printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  172. printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
  173. printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
  174. printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
  175. return 0;
  176. }
  177. /*
  178. * Initializes on-chip ethernet controllers.
  179. */
  180. #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
  181. int cpu_eth_init(struct bd_info *bis)
  182. {
  183. struct mxs_clkctrl_regs *clkctrl_regs =
  184. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  185. /* Turn on ENET clocks */
  186. clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  187. CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
  188. /* Set up ENET PLL for 50 MHz */
  189. /* Power on ENET PLL */
  190. writel(CLKCTRL_PLL2CTRL0_POWER,
  191. &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
  192. udelay(10);
  193. /* Gate on ENET PLL */
  194. writel(CLKCTRL_PLL2CTRL0_CLKGATE,
  195. &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
  196. /* Enable pad output */
  197. setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
  198. return 0;
  199. }
  200. #endif
  201. __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
  202. {
  203. mac[0] = 0x00;
  204. mac[1] = 0x04; /* Use FSL vendor MAC address by default */
  205. if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
  206. mac[5] += 1;
  207. }
  208. #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
  209. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  210. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  211. {
  212. struct mxs_ocotp_regs *ocotp_regs =
  213. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  214. uint32_t data;
  215. memset(mac, 0, 6);
  216. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  217. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  218. MXS_OCOTP_MAX_TIMEOUT)) {
  219. printf("MXS FEC: Can't get MAC from OCOTP\n");
  220. return;
  221. }
  222. data = readl(&ocotp_regs->hw_ocotp_cust0);
  223. mac[2] = (data >> 24) & 0xff;
  224. mac[3] = (data >> 16) & 0xff;
  225. mac[4] = (data >> 8) & 0xff;
  226. mac[5] = data & 0xff;
  227. mx28_adjust_mac(dev_id, mac);
  228. }
  229. #else
  230. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  231. {
  232. memset(mac, 0, 6);
  233. }
  234. #endif
  235. int mxs_dram_init(void)
  236. {
  237. struct mxs_spl_data *data = MXS_SPL_DATA;
  238. if (data->mem_dram_size == 0) {
  239. printf("MXS:\n"
  240. "Error, the RAM size passed up from SPL is 0!\n");
  241. hang();
  242. }
  243. gd->ram_size = data->mem_dram_size;
  244. return 0;
  245. }
  246. U_BOOT_CMD(
  247. clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
  248. "display clocks",
  249. ""
  250. );