generic.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 DENX Software Engineering
  4. * Author: John Rigby <jrigby@gmail.com>
  5. *
  6. * Based on mx27/generic.c:
  7. * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  8. * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
  9. */
  10. #include <common.h>
  11. #include <clock_legacy.h>
  12. #include <div64.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <vsprintf.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <asm/arch-imx/cpu.h>
  20. #include <asm/arch/imx-regs.h>
  21. #include <asm/arch/clock.h>
  22. #ifdef CONFIG_FSL_ESDHC_IMX
  23. #include <fsl_esdhc_imx.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #endif
  26. /*
  27. * get the system pll clock in Hz
  28. *
  29. * mfi + mfn / (mfd +1)
  30. * f = 2 * f_ref * --------------------
  31. * pd + 1
  32. */
  33. static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
  34. {
  35. unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
  36. & CCM_PLL_MFI_MASK;
  37. int mfn = (pll >> CCM_PLL_MFN_SHIFT)
  38. & CCM_PLL_MFN_MASK;
  39. unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
  40. & CCM_PLL_MFD_MASK;
  41. unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
  42. & CCM_PLL_PD_MASK;
  43. mfi = mfi <= 5 ? 5 : mfi;
  44. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  45. mfd += 1;
  46. pd += 1;
  47. return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
  48. mfd * pd);
  49. }
  50. static ulong imx_get_mpllclk(void)
  51. {
  52. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  53. ulong fref = MXC_HCLK;
  54. return imx_decode_pll(readl(&ccm->mpctl), fref);
  55. }
  56. static ulong imx_get_upllclk(void)
  57. {
  58. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  59. ulong fref = MXC_HCLK;
  60. return imx_decode_pll(readl(&ccm->upctl), fref);
  61. }
  62. static ulong imx_get_armclk(void)
  63. {
  64. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  65. ulong cctl = readl(&ccm->cctl);
  66. ulong fref = imx_get_mpllclk();
  67. ulong div;
  68. if (cctl & CCM_CCTL_ARM_SRC)
  69. fref = lldiv((u64) fref * 3, 4);
  70. div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
  71. & CCM_CCTL_ARM_DIV_MASK) + 1;
  72. return fref / div;
  73. }
  74. static ulong imx_get_ahbclk(void)
  75. {
  76. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  77. ulong cctl = readl(&ccm->cctl);
  78. ulong fref = imx_get_armclk();
  79. ulong div;
  80. div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
  81. & CCM_CCTL_AHB_DIV_MASK) + 1;
  82. return fref / div;
  83. }
  84. static ulong imx_get_ipgclk(void)
  85. {
  86. return imx_get_ahbclk() / 2;
  87. }
  88. static ulong imx_get_perclk(int clk)
  89. {
  90. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  91. ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
  92. imx_get_ahbclk();
  93. ulong div;
  94. div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
  95. div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
  96. return fref / div;
  97. }
  98. int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
  99. {
  100. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  101. ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
  102. ulong div = (fref + freq - 1) / freq;
  103. if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
  104. return -EINVAL;
  105. clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
  106. CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
  107. div << CCM_PERCLK_SHIFT(clk));
  108. if (from_upll)
  109. setbits_le32(&ccm->mcr, 1 << clk);
  110. else
  111. clrbits_le32(&ccm->mcr, 1 << clk);
  112. return 0;
  113. }
  114. unsigned int mxc_get_clock(enum mxc_clock clk)
  115. {
  116. if (clk >= MXC_CLK_NUM)
  117. return -1;
  118. switch (clk) {
  119. case MXC_ARM_CLK:
  120. return imx_get_armclk();
  121. case MXC_AHB_CLK:
  122. return imx_get_ahbclk();
  123. case MXC_IPG_CLK:
  124. case MXC_CSPI_CLK:
  125. case MXC_FEC_CLK:
  126. return imx_get_ipgclk();
  127. default:
  128. return imx_get_perclk(clk);
  129. }
  130. }
  131. u32 get_cpu_rev(void)
  132. {
  133. u32 srev;
  134. u32 system_rev = 0x25000;
  135. /* read SREV register from IIM module */
  136. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  137. srev = readl(&iim->iim_srev);
  138. switch (srev) {
  139. case 0x00:
  140. system_rev |= CHIP_REV_1_0;
  141. break;
  142. case 0x01:
  143. system_rev |= CHIP_REV_1_1;
  144. break;
  145. case 0x02:
  146. system_rev |= CHIP_REV_1_2;
  147. break;
  148. default:
  149. system_rev |= 0x8000;
  150. break;
  151. }
  152. return system_rev;
  153. }
  154. #if defined(CONFIG_DISPLAY_CPUINFO)
  155. static char *get_reset_cause(void)
  156. {
  157. /* read RCSR register from CCM module */
  158. struct ccm_regs *ccm =
  159. (struct ccm_regs *)IMX_CCM_BASE;
  160. u32 cause = readl(&ccm->rcsr) & 0x0f;
  161. if (cause == 0)
  162. return "POR";
  163. else if (cause == 1)
  164. return "RST";
  165. else if ((cause & 2) == 2)
  166. return "WDOG";
  167. else if ((cause & 4) == 4)
  168. return "SW RESET";
  169. else if ((cause & 8) == 8)
  170. return "JTAG";
  171. else
  172. return "unknown reset";
  173. }
  174. int print_cpuinfo(void)
  175. {
  176. char buf[32];
  177. u32 cpurev = get_cpu_rev();
  178. printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
  179. (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
  180. ((cpurev & 0x8000) ? " unknown" : ""),
  181. strmhz(buf, imx_get_armclk()));
  182. printf("Reset cause: %s\n", get_reset_cause());
  183. return 0;
  184. }
  185. #endif
  186. #if defined(CONFIG_FEC_MXC)
  187. /*
  188. * Initializes on-chip ethernet controllers.
  189. * to override, implement board_eth_init()
  190. */
  191. int cpu_eth_init(struct bd_info *bis)
  192. {
  193. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  194. ulong val;
  195. val = readl(&ccm->cgr0);
  196. val |= (1 << 23);
  197. writel(val, &ccm->cgr0);
  198. return fecmxc_initialize(bis);
  199. }
  200. #endif
  201. int get_clocks(void)
  202. {
  203. #ifdef CONFIG_FSL_ESDHC_IMX
  204. #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
  205. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  206. #else
  207. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  208. #endif
  209. #endif
  210. return 0;
  211. }
  212. #ifdef CONFIG_FSL_ESDHC_IMX
  213. /*
  214. * Initializes on-chip MMC controllers.
  215. * to override, implement board_mmc_init()
  216. */
  217. int cpu_mmc_init(struct bd_info *bis)
  218. {
  219. return fsl_esdhc_mmc_init(bis);
  220. }
  221. #endif
  222. #ifdef CONFIG_FEC_MXC
  223. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  224. {
  225. int i;
  226. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  227. struct fuse_bank *bank = &iim->bank[0];
  228. struct fuse_bank0_regs *fuse =
  229. (struct fuse_bank0_regs *)bank->fuse_regs;
  230. for (i = 0; i < 6; i++)
  231. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  232. }
  233. #endif /* CONFIG_FEC_MXC */