timer.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <time.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/armada100.h>
  14. #include <asm/global_data.h>
  15. #include <linux/delay.h>
  16. /*
  17. * Timer registers
  18. * Refer Section A.6 in Datasheet
  19. */
  20. struct armd1tmr_registers {
  21. u32 clk_ctrl; /* Timer clk control reg */
  22. u32 match[9]; /* Timer match registers */
  23. u32 count[3]; /* Timer count registers */
  24. u32 status[3];
  25. u32 ie[3];
  26. u32 preload[3]; /* Timer preload value */
  27. u32 preload_ctrl[3];
  28. u32 wdt_match_en;
  29. u32 wdt_match_r;
  30. u32 wdt_val;
  31. u32 wdt_sts;
  32. u32 icr[3];
  33. u32 wdt_icr;
  34. u32 cer; /* Timer count enable reg */
  35. u32 cmr;
  36. u32 ilr[3];
  37. u32 wcr;
  38. u32 wfar;
  39. u32 wsar;
  40. u32 cvwr;
  41. };
  42. #define TIMER 0 /* Use TIMER 0 */
  43. /* Each timer has 3 match registers */
  44. #define MATCH_CMP(x) ((3 * TIMER) + x)
  45. #define TIMER_LOAD_VAL 0xffffffff
  46. #define COUNT_RD_REQ 0x1
  47. DECLARE_GLOBAL_DATA_PTR;
  48. /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
  49. /* For preventing risk of instability in reading counter value,
  50. * first set read request to register cvwr and then read same
  51. * register after it captures counter value.
  52. */
  53. ulong read_timer(void)
  54. {
  55. struct armd1tmr_registers *armd1timers =
  56. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  57. volatile int loop=100;
  58. writel(COUNT_RD_REQ, &armd1timers->cvwr);
  59. while (loop--);
  60. return(readl(&armd1timers->cvwr));
  61. }
  62. static ulong get_timer_masked(void)
  63. {
  64. ulong now = read_timer();
  65. if (now >= gd->arch.tbl) {
  66. /* normal mode */
  67. gd->arch.tbu += now - gd->arch.tbl;
  68. } else {
  69. /* we have an overflow ... */
  70. gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
  71. }
  72. gd->arch.tbl = now;
  73. return gd->arch.tbu;
  74. }
  75. ulong get_timer(ulong base)
  76. {
  77. return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
  78. base);
  79. }
  80. void __udelay(unsigned long usec)
  81. {
  82. ulong delayticks;
  83. ulong endtime;
  84. delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
  85. endtime = get_timer_masked() + delayticks;
  86. while (get_timer_masked() < endtime);
  87. }
  88. /*
  89. * init the Timer
  90. */
  91. int timer_init(void)
  92. {
  93. struct armd1apb1_registers *apb1clkres =
  94. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  95. struct armd1tmr_registers *armd1timers =
  96. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  97. /* Enable Timer clock at 3.25 MHZ */
  98. writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
  99. /* load value into timer */
  100. writel(0x0, &armd1timers->clk_ctrl);
  101. /* Use Timer 0 Match Resiger 0 */
  102. writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
  103. /* Preload value is 0 */
  104. writel(0x0, &armd1timers->preload[TIMER]);
  105. /* Enable match comparator 0 for Timer 0 */
  106. writel(0x1, &armd1timers->preload_ctrl[TIMER]);
  107. /* Enable timer 0 */
  108. writel(0x1, &armd1timers->cer);
  109. /* init the gd->arch.tbu and gd->arch.tbl value */
  110. gd->arch.tbl = read_timer();
  111. gd->arch.tbu = 0;
  112. return 0;
  113. }
  114. #define MPMU_APRR_WDTR (1<<4)
  115. #define TMR_WFAR 0xbaba /* WDT Register First key */
  116. #define TMP_WSAR 0xeb10 /* WDT Register Second key */
  117. /*
  118. * This function uses internal Watchdog Timer
  119. * based reset mechanism.
  120. * Steps to write watchdog registers (protected access)
  121. * 1. Write key value to TMR_WFAR reg.
  122. * 2. Write key value to TMP_WSAR reg.
  123. * 3. Perform write operation.
  124. */
  125. void reset_cpu(unsigned long ignored)
  126. {
  127. struct armd1mpmu_registers *mpmu =
  128. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  129. struct armd1tmr_registers *armd1timers =
  130. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  131. u32 val;
  132. /* negate hardware reset to the WDT after system reset */
  133. val = readl(&mpmu->aprr);
  134. val = val | MPMU_APRR_WDTR;
  135. writel(val, &mpmu->aprr);
  136. /* reset/enable WDT clock */
  137. writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
  138. readl(&mpmu->wdtpcr);
  139. writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
  140. readl(&mpmu->wdtpcr);
  141. /* clear previous WDT status */
  142. writel(TMR_WFAR, &armd1timers->wfar);
  143. writel(TMP_WSAR, &armd1timers->wsar);
  144. writel(0, &armd1timers->wdt_sts);
  145. /* set match counter */
  146. writel(TMR_WFAR, &armd1timers->wfar);
  147. writel(TMP_WSAR, &armd1timers->wsar);
  148. writel(0xf, &armd1timers->wdt_match_r);
  149. /* enable WDT reset */
  150. writel(TMR_WFAR, &armd1timers->wfar);
  151. writel(TMP_WSAR, &armd1timers->wsar);
  152. writel(0x3, &armd1timers->wdt_match_en);
  153. while(1);
  154. }
  155. /*
  156. * This function is derived from PowerPC code (read timebase as long long).
  157. * On ARM it just returns the timer value.
  158. */
  159. unsigned long long get_ticks(void)
  160. {
  161. return get_timer(0);
  162. }
  163. /*
  164. * This function is derived from PowerPC code (timebase clock frequency).
  165. * On ARM it returns the number of timer ticks per second.
  166. */
  167. ulong get_tbclk(void)
  168. {
  169. return (ulong)CONFIG_SYS_HZ;
  170. }