dram.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/armada100.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /*
  15. * ARMADA100 DRAM controller supports upto 8 banks
  16. * for chip select 0 and 1
  17. */
  18. /*
  19. * DDR Memory Control Registers
  20. * Refer Datasheet Appendix A.17
  21. */
  22. struct armd1ddr_map_registers {
  23. u32 cs; /* Memory Address Map Register -CS */
  24. u32 pad[3];
  25. };
  26. struct armd1ddr_registers {
  27. u8 pad[0x100 - 0x000];
  28. struct armd1ddr_map_registers mmap[2];
  29. };
  30. /*
  31. * armd1_sdram_base - reads SDRAM Base Address Register
  32. */
  33. u32 armd1_sdram_base(int chip_sel)
  34. {
  35. struct armd1ddr_registers *ddr_regs =
  36. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  37. u32 result = 0;
  38. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  39. if (!CS_valid)
  40. return 0;
  41. result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
  42. return result;
  43. }
  44. /*
  45. * armd1_sdram_size - reads SDRAM size
  46. */
  47. u32 armd1_sdram_size(int chip_sel)
  48. {
  49. struct armd1ddr_registers *ddr_regs =
  50. (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
  51. u32 result = 0;
  52. u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
  53. if (!CS_valid)
  54. return 0;
  55. result = readl(&ddr_regs->mmap[chip_sel].cs);
  56. result = (result >> 16) & 0xF;
  57. if (result < 0x7) {
  58. printf("Unknown DRAM Size\n");
  59. return -1;
  60. } else {
  61. return ((0x8 << (result - 0x7)) * 1024 * 1024);
  62. }
  63. }
  64. int dram_init(void)
  65. {
  66. int i;
  67. gd->ram_size = 0;
  68. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  69. gd->bd->bi_dram[i].start = armd1_sdram_base(i);
  70. gd->bd->bi_dram[i].size = armd1_sdram_size(i);
  71. /*
  72. * It is assumed that all memory banks are consecutive
  73. * and without gaps.
  74. * If the gap is found, ram_size will be reported for
  75. * consecutive memory only
  76. */
  77. if (gd->bd->bi_dram[i].start != gd->ram_size)
  78. break;
  79. gd->ram_size += gd->bd->bi_dram[i].size;
  80. }
  81. for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  82. /* If above loop terminated prematurely, we need to set
  83. * remaining banks' start address & size as 0. Otherwise other
  84. * u-boot functions and Linux kernel gets wrong values which
  85. * could result in crash */
  86. gd->bd->bi_dram[i].start = 0;
  87. gd->bd->bi_dram[i].size = 0;
  88. }
  89. return 0;
  90. }
  91. /*
  92. * If this function is not defined here,
  93. * board.c alters dram bank zero configuration defined above.
  94. */
  95. int dram_init_banksize(void)
  96. {
  97. dram_init();
  98. return 0;
  99. }