generic.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <div64.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <linux/errno.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/sys_proto.h>
  21. #ifdef CONFIG_FSL_ESDHC_IMX
  22. #include <fsl_esdhc_imx.h>
  23. #endif
  24. #include <netdev.h>
  25. #include <spl.h>
  26. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  27. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  28. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  29. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  30. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  31. #ifdef CONFIG_FSL_ESDHC_IMX
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #endif
  34. static int g_clk_mux_auto[8] = {
  35. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  36. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  37. };
  38. static int g_clk_mux_consumer[16] = {
  39. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  40. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  41. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  42. -1, -1, CLK_CODE(4, 2, 0), -1,
  43. };
  44. static int hsp_div_table[3][16] = {
  45. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  46. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  47. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  48. };
  49. u32 get_cpu_rev(void)
  50. {
  51. int reg;
  52. struct iim_regs *iim =
  53. (struct iim_regs *)IIM_BASE_ADDR;
  54. reg = readl(&iim->iim_srev);
  55. if (!reg) {
  56. reg = readw(ROMPATCH_REV);
  57. reg <<= 4;
  58. } else {
  59. reg += CHIP_REV_1_0;
  60. }
  61. return 0x35000 + (reg & 0xFF);
  62. }
  63. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  64. {
  65. int *pclk_mux;
  66. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  67. pclk_mux = g_clk_mux_consumer +
  68. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  69. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  70. } else {
  71. pclk_mux = g_clk_mux_auto +
  72. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  73. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  74. }
  75. if ((*pclk_mux) == -1)
  76. return -1;
  77. if (fi && fd) {
  78. if (!CLK_CODE_PATH(*pclk_mux)) {
  79. *fi = *fd = 1;
  80. return CLK_CODE_ARM(*pclk_mux);
  81. }
  82. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  83. *fi = 3;
  84. *fd = 4;
  85. } else {
  86. *fi = 2;
  87. *fd = 3;
  88. }
  89. }
  90. return CLK_CODE_ARM(*pclk_mux);
  91. }
  92. static int get_ahb_div(u32 pdr0)
  93. {
  94. int *pclk_mux;
  95. pclk_mux = g_clk_mux_consumer +
  96. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  97. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  98. if ((*pclk_mux) == -1)
  99. return -1;
  100. return CLK_CODE_AHB(*pclk_mux);
  101. }
  102. static u32 decode_pll(u32 reg, u32 infreq)
  103. {
  104. u32 mfi = (reg >> 10) & 0xf;
  105. s32 mfn = reg & 0x3ff;
  106. u32 mfd = (reg >> 16) & 0x3ff;
  107. u32 pd = (reg >> 26) & 0xf;
  108. mfi = mfi <= 5 ? 5 : mfi;
  109. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  110. mfd += 1;
  111. pd += 1;
  112. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  113. mfd * pd);
  114. }
  115. static u32 get_mcu_main_clk(void)
  116. {
  117. u32 arm_div = 0, fi = 0, fd = 0;
  118. struct ccm_regs *ccm =
  119. (struct ccm_regs *)IMX_CCM_BASE;
  120. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  121. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  122. return fi / (arm_div * fd);
  123. }
  124. static u32 get_ipg_clk(void)
  125. {
  126. u32 freq = get_mcu_main_clk();
  127. struct ccm_regs *ccm =
  128. (struct ccm_regs *)IMX_CCM_BASE;
  129. u32 pdr0 = readl(&ccm->pdr0);
  130. return freq / (get_ahb_div(pdr0) * 2);
  131. }
  132. static u32 get_ipg_per_clk(void)
  133. {
  134. u32 freq = get_mcu_main_clk();
  135. struct ccm_regs *ccm =
  136. (struct ccm_regs *)IMX_CCM_BASE;
  137. u32 pdr0 = readl(&ccm->pdr0);
  138. u32 pdr4 = readl(&ccm->pdr4);
  139. u32 div;
  140. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  141. div = CCM_GET_DIVIDER(pdr4,
  142. MXC_CCM_PDR4_PER0_PODF_MASK,
  143. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  144. } else {
  145. div = CCM_GET_DIVIDER(pdr0,
  146. MXC_CCM_PDR0_PER_PODF_MASK,
  147. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  148. div *= get_ahb_div(pdr0);
  149. }
  150. return freq / div;
  151. }
  152. u32 imx_get_uartclk(void)
  153. {
  154. u32 freq;
  155. struct ccm_regs *ccm =
  156. (struct ccm_regs *)IMX_CCM_BASE;
  157. u32 pdr4 = readl(&ccm->pdr4);
  158. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  159. freq = get_mcu_main_clk();
  160. else
  161. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  162. freq /= CCM_GET_DIVIDER(pdr4,
  163. MXC_CCM_PDR4_UART_PODF_MASK,
  164. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  165. return freq;
  166. }
  167. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  168. {
  169. u32 nfc_pdf, hsp_podf;
  170. u32 pll, ret_val = 0, usb_podf;
  171. struct ccm_regs *ccm =
  172. (struct ccm_regs *)IMX_CCM_BASE;
  173. u32 reg = readl(&ccm->pdr0);
  174. u32 reg4 = readl(&ccm->pdr4);
  175. reg |= 0x1;
  176. switch (clk) {
  177. case CPU_CLK:
  178. ret_val = get_mcu_main_clk();
  179. break;
  180. case AHB_CLK:
  181. ret_val = get_mcu_main_clk();
  182. break;
  183. case HSP_CLK:
  184. if (reg & CLKMODE_CONSUMER) {
  185. hsp_podf = (reg >> 20) & 0x3;
  186. pll = get_mcu_main_clk();
  187. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  188. if (hsp_podf > 0) {
  189. ret_val = pll / hsp_podf;
  190. } else {
  191. puts("mismatch HSP with ARM clock setting\n");
  192. ret_val = 0;
  193. }
  194. } else {
  195. ret_val = get_mcu_main_clk();
  196. }
  197. break;
  198. case IPG_CLK:
  199. ret_val = get_ipg_clk();
  200. break;
  201. case IPG_PER_CLK:
  202. ret_val = get_ipg_per_clk();
  203. break;
  204. case NFC_CLK:
  205. nfc_pdf = (reg4 >> 28) & 0xF;
  206. pll = get_mcu_main_clk();
  207. /* AHB/nfc_pdf */
  208. ret_val = pll / (nfc_pdf + 1);
  209. break;
  210. case USB_CLK:
  211. usb_podf = (reg4 >> 22) & 0x3F;
  212. if (reg4 & 0x200)
  213. pll = get_mcu_main_clk();
  214. else
  215. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  216. ret_val = pll / (usb_podf + 1);
  217. break;
  218. default:
  219. printf("Unknown clock: %d\n", clk);
  220. break;
  221. }
  222. return ret_val;
  223. }
  224. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  225. {
  226. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  227. struct ccm_regs *ccm =
  228. (struct ccm_regs *)IMX_CCM_BASE;
  229. u32 mpdr2 = readl(&ccm->pdr2);
  230. u32 mpdr3 = readl(&ccm->pdr3);
  231. u32 mpdr4 = readl(&ccm->pdr4);
  232. switch (clk) {
  233. case UART1_BAUD:
  234. case UART2_BAUD:
  235. case UART3_BAUD:
  236. clk_sel = mpdr3 & (1 << 14);
  237. pdf = (mpdr4 >> 10) & 0x3F;
  238. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  239. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  240. break;
  241. case SSI1_BAUD:
  242. pre_pdf = (mpdr2 >> 24) & 0x7;
  243. pdf = mpdr2 & 0x3F;
  244. clk_sel = mpdr2 & (1 << 6);
  245. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  246. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  247. ((pre_pdf + 1) * (pdf + 1));
  248. break;
  249. case SSI2_BAUD:
  250. pre_pdf = (mpdr2 >> 27) & 0x7;
  251. pdf = (mpdr2 >> 8) & 0x3F;
  252. clk_sel = mpdr2 & (1 << 6);
  253. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  254. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  255. ((pre_pdf + 1) * (pdf + 1));
  256. break;
  257. case CSI_BAUD:
  258. clk_sel = mpdr2 & (1 << 7);
  259. pdf = (mpdr2 >> 16) & 0x3F;
  260. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  261. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  262. break;
  263. case MSHC_CLK:
  264. pre_pdf = readl(&ccm->pdr1);
  265. clk_sel = (pre_pdf & 0x80);
  266. pdf = (pre_pdf >> 22) & 0x3F;
  267. pre_pdf = (pre_pdf >> 28) & 0x7;
  268. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  269. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  270. ((pre_pdf + 1) * (pdf + 1));
  271. break;
  272. case ESDHC1_CLK:
  273. clk_sel = mpdr3 & 0x40;
  274. pdf = mpdr3 & 0x3F;
  275. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  276. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  277. break;
  278. case ESDHC2_CLK:
  279. clk_sel = mpdr3 & 0x40;
  280. pdf = (mpdr3 >> 8) & 0x3F;
  281. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  282. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  283. break;
  284. case ESDHC3_CLK:
  285. clk_sel = mpdr3 & 0x40;
  286. pdf = (mpdr3 >> 16) & 0x3F;
  287. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  288. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  289. break;
  290. case SPDIF_CLK:
  291. clk_sel = mpdr3 & 0x400000;
  292. pre_pdf = (mpdr3 >> 29) & 0x7;
  293. pdf = (mpdr3 >> 23) & 0x3F;
  294. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  295. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  296. ((pre_pdf + 1) * (pdf + 1));
  297. break;
  298. default:
  299. printf("%s(): This clock: %d not supported yet\n",
  300. __func__, clk);
  301. break;
  302. }
  303. return ret_val;
  304. }
  305. unsigned int mxc_get_clock(enum mxc_clock clk)
  306. {
  307. switch (clk) {
  308. case MXC_ARM_CLK:
  309. return get_mcu_main_clk();
  310. case MXC_AHB_CLK:
  311. break;
  312. case MXC_IPG_CLK:
  313. return get_ipg_clk();
  314. case MXC_IPG_PERCLK:
  315. case MXC_I2C_CLK:
  316. return get_ipg_per_clk();
  317. case MXC_UART_CLK:
  318. return imx_get_uartclk();
  319. case MXC_ESDHC1_CLK:
  320. return mxc_get_peri_clock(ESDHC1_CLK);
  321. case MXC_ESDHC2_CLK:
  322. return mxc_get_peri_clock(ESDHC2_CLK);
  323. case MXC_ESDHC3_CLK:
  324. return mxc_get_peri_clock(ESDHC3_CLK);
  325. case MXC_USB_CLK:
  326. return mxc_get_main_clock(USB_CLK);
  327. case MXC_FEC_CLK:
  328. return get_ipg_clk();
  329. case MXC_CSPI_CLK:
  330. return get_ipg_clk();
  331. }
  332. return -1;
  333. }
  334. #ifdef CONFIG_FEC_MXC
  335. /*
  336. * The MX35 has no fuse for MAC, return a NULL MAC
  337. */
  338. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  339. {
  340. memset(mac, 0, 6);
  341. }
  342. u32 imx_get_fecclk(void)
  343. {
  344. return mxc_get_clock(MXC_IPG_CLK);
  345. }
  346. #endif
  347. int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  348. char *const argv[])
  349. {
  350. u32 cpufreq = get_mcu_main_clk();
  351. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  352. printf("ipg clock : %dHz\n", get_ipg_clk());
  353. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  354. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  355. return 0;
  356. }
  357. U_BOOT_CMD(
  358. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  359. "display clocks",
  360. ""
  361. );
  362. #if defined(CONFIG_DISPLAY_CPUINFO)
  363. static char *get_reset_cause(void)
  364. {
  365. /* read RCSR register from CCM module */
  366. struct ccm_regs *ccm =
  367. (struct ccm_regs *)IMX_CCM_BASE;
  368. u32 cause = readl(&ccm->rcsr) & 0x0F;
  369. switch (cause) {
  370. case 0x0000:
  371. return "POR";
  372. case 0x0002:
  373. return "JTAG";
  374. case 0x0004:
  375. return "RST";
  376. case 0x0008:
  377. return "WDOG";
  378. default:
  379. return "unknown reset";
  380. }
  381. }
  382. int print_cpuinfo(void)
  383. {
  384. u32 srev = get_cpu_rev();
  385. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  386. (srev & 0xF0) >> 4, (srev & 0x0F),
  387. get_mcu_main_clk() / 1000000);
  388. printf("Reset cause: %s\n", get_reset_cause());
  389. return 0;
  390. }
  391. #endif
  392. /*
  393. * Initializes on-chip ethernet controllers.
  394. * to override, implement board_eth_init()
  395. */
  396. int cpu_eth_init(struct bd_info *bis)
  397. {
  398. int rc = -ENODEV;
  399. #if defined(CONFIG_FEC_MXC)
  400. rc = fecmxc_initialize(bis);
  401. #endif
  402. return rc;
  403. }
  404. #ifdef CONFIG_FSL_ESDHC_IMX
  405. /*
  406. * Initializes on-chip MMC controllers.
  407. * to override, implement board_mmc_init()
  408. */
  409. int cpu_mmc_init(struct bd_info *bis)
  410. {
  411. return fsl_esdhc_mmc_init(bis);
  412. }
  413. #endif
  414. int get_clocks(void)
  415. {
  416. #ifdef CONFIG_FSL_ESDHC_IMX
  417. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  418. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  419. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  420. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  421. #else
  422. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  423. #endif
  424. #endif
  425. return 0;
  426. }
  427. #define RCSR_MEM_CTL_WEIM 0
  428. #define RCSR_MEM_CTL_NAND 1
  429. #define RCSR_MEM_CTL_ATA 2
  430. #define RCSR_MEM_CTL_EXPANSION 3
  431. #define RCSR_MEM_TYPE_NOR 0
  432. #define RCSR_MEM_TYPE_ONENAND 2
  433. #define RCSR_MEM_TYPE_SD 0
  434. #define RCSR_MEM_TYPE_I2C 2
  435. #define RCSR_MEM_TYPE_SPI 3
  436. u32 spl_boot_device(void)
  437. {
  438. struct ccm_regs *ccm =
  439. (struct ccm_regs *)IMX_CCM_BASE;
  440. u32 rcsr = readl(&ccm->rcsr);
  441. u32 mem_type, mem_ctl;
  442. /* In external mode, no boot device is returned */
  443. if ((rcsr >> 10) & 0x03)
  444. return BOOT_DEVICE_NONE;
  445. mem_ctl = (rcsr >> 25) & 0x03;
  446. mem_type = (rcsr >> 23) & 0x03;
  447. switch (mem_ctl) {
  448. case RCSR_MEM_CTL_WEIM:
  449. switch (mem_type) {
  450. case RCSR_MEM_TYPE_NOR:
  451. return BOOT_DEVICE_NOR;
  452. case RCSR_MEM_TYPE_ONENAND:
  453. return BOOT_DEVICE_ONENAND;
  454. default:
  455. return BOOT_DEVICE_NONE;
  456. }
  457. case RCSR_MEM_CTL_NAND:
  458. return BOOT_DEVICE_NAND;
  459. case RCSR_MEM_CTL_EXPANSION:
  460. switch (mem_type) {
  461. case RCSR_MEM_TYPE_SD:
  462. return BOOT_DEVICE_MMC1;
  463. case RCSR_MEM_TYPE_I2C:
  464. return BOOT_DEVICE_I2C;
  465. case RCSR_MEM_TYPE_SPI:
  466. return BOOT_DEVICE_SPI;
  467. default:
  468. return BOOT_DEVICE_NONE;
  469. }
  470. }
  471. return BOOT_DEVICE_NONE;
  472. }