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  1. /*
  2. * armboot - Startup Code for SA1100 CPU
  3. *
  4. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  5. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  6. * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
  7. * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <asm-offsets.h>
  28. #include <config.h>
  29. #include <version.h>
  30. /*
  31. *************************************************************************
  32. *
  33. * Jump vector table as in table 3.1 in [1]
  34. *
  35. *************************************************************************
  36. */
  37. .globl _start
  38. _start: b reset
  39. ldr pc, _undefined_instruction
  40. ldr pc, _software_interrupt
  41. ldr pc, _prefetch_abort
  42. ldr pc, _data_abort
  43. ldr pc, _not_used
  44. ldr pc, _irq
  45. ldr pc, _fiq
  46. _undefined_instruction: .word undefined_instruction
  47. _software_interrupt: .word software_interrupt
  48. _prefetch_abort: .word prefetch_abort
  49. _data_abort: .word data_abort
  50. _not_used: .word not_used
  51. _irq: .word irq
  52. _fiq: .word fiq
  53. .balignl 16,0xdeadbeef
  54. /*
  55. *************************************************************************
  56. *
  57. * Startup Code (reset vector)
  58. *
  59. * do important init only if we don't start from memory!
  60. * relocate armboot to ram
  61. * setup stack
  62. * jump to second stage
  63. *
  64. *************************************************************************
  65. */
  66. .globl _TEXT_BASE
  67. _TEXT_BASE:
  68. .word CONFIG_SYS_TEXT_BASE
  69. /*
  70. * These are defined in the board-specific linker script.
  71. * Subtracting _start from them lets the linker put their
  72. * relative position in the executable instead of leaving
  73. * them null.
  74. */
  75. .globl _bss_start_ofs
  76. _bss_start_ofs:
  77. .word __bss_start - _start
  78. .globl _bss_end_ofs
  79. _bss_end_ofs:
  80. .word __bss_end__ - _start
  81. .globl _end_ofs
  82. _end_ofs:
  83. .word _end - _start
  84. #ifdef CONFIG_USE_IRQ
  85. /* IRQ stack memory (calculated at run-time) */
  86. .globl IRQ_STACK_START
  87. IRQ_STACK_START:
  88. .word 0x0badc0de
  89. /* IRQ stack memory (calculated at run-time) */
  90. .globl FIQ_STACK_START
  91. FIQ_STACK_START:
  92. .word 0x0badc0de
  93. #endif
  94. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  95. .globl IRQ_STACK_START_IN
  96. IRQ_STACK_START_IN:
  97. .word 0x0badc0de
  98. /*
  99. * the actual reset code
  100. */
  101. reset:
  102. /*
  103. * set the cpu to SVC32 mode
  104. */
  105. mrs r0,cpsr
  106. bic r0,r0,#0x1f
  107. orr r0,r0,#0xd3
  108. msr cpsr,r0
  109. /*
  110. * we do sys-critical inits only at reboot,
  111. * not when booting from ram!
  112. */
  113. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  114. bl cpu_init_crit
  115. #endif
  116. /* Set stackpointer in internal RAM to call board_init_f */
  117. call_board_init_f:
  118. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  119. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  120. ldr r0,=0x00000000
  121. bl board_init_f
  122. /*------------------------------------------------------------------------------*/
  123. /*
  124. * void relocate_code (addr_sp, gd, addr_moni)
  125. *
  126. * This "function" does not return, instead it continues in RAM
  127. * after relocating the monitor code.
  128. *
  129. */
  130. .globl relocate_code
  131. relocate_code:
  132. mov r4, r0 /* save addr_sp */
  133. mov r5, r1 /* save addr of gd */
  134. mov r6, r2 /* save addr of destination */
  135. /* Set up the stack */
  136. stack_setup:
  137. mov sp, r4
  138. adr r0, _start
  139. cmp r0, r6
  140. beq clear_bss /* skip relocation */
  141. mov r1, r6 /* r1 <- scratch for copy_loop */
  142. ldr r3, _bss_start_ofs
  143. add r2, r0, r3 /* r2 <- source end address */
  144. copy_loop:
  145. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  146. stmia r1!, {r9-r10} /* copy to target address [r1] */
  147. cmp r0, r2 /* until source end address [r2] */
  148. blo copy_loop
  149. #ifndef CONFIG_SPL_BUILD
  150. /*
  151. * fix .rel.dyn relocations
  152. */
  153. ldr r0, _TEXT_BASE /* r0 <- Text base */
  154. sub r9, r6, r0 /* r9 <- relocation offset */
  155. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  156. add r10, r10, r0 /* r10 <- sym table in FLASH */
  157. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  158. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  159. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  160. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  161. fixloop:
  162. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  163. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  164. ldr r1, [r2, #4]
  165. and r7, r1, #0xff
  166. cmp r7, #23 /* relative fixup? */
  167. beq fixrel
  168. cmp r7, #2 /* absolute fixup? */
  169. beq fixabs
  170. /* ignore unknown type of fixup */
  171. b fixnext
  172. fixabs:
  173. /* absolute fix: set location to (offset) symbol value */
  174. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  175. add r1, r10, r1 /* r1 <- address of symbol in table */
  176. ldr r1, [r1, #4] /* r1 <- symbol value */
  177. add r1, r1, r9 /* r1 <- relocated sym addr */
  178. b fixnext
  179. fixrel:
  180. /* relative fix: increase location by offset */
  181. ldr r1, [r0]
  182. add r1, r1, r9
  183. fixnext:
  184. str r1, [r0]
  185. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  186. cmp r2, r3
  187. blo fixloop
  188. #endif
  189. clear_bss:
  190. #ifndef CONFIG_SPL_BUILD
  191. ldr r0, _bss_start_ofs
  192. ldr r1, _bss_end_ofs
  193. mov r4, r6 /* reloc addr */
  194. add r0, r0, r4
  195. add r1, r1, r4
  196. mov r2, #0x00000000 /* clear */
  197. clbss_l:str r2, [r0] /* clear loop... */
  198. add r0, r0, #4
  199. cmp r0, r1
  200. bne clbss_l
  201. #endif
  202. /*
  203. * We are done. Do not return, instead branch to second part of board
  204. * initialization, now running from RAM.
  205. */
  206. ldr r0, _board_init_r_ofs
  207. adr r1, _start
  208. add lr, r0, r1
  209. add lr, lr, r9
  210. /* setup parameters for board_init_r */
  211. mov r0, r5 /* gd_t */
  212. mov r1, r6 /* dest_addr */
  213. /* jump to it ... */
  214. mov pc, lr
  215. _board_init_r_ofs:
  216. .word board_init_r - _start
  217. _rel_dyn_start_ofs:
  218. .word __rel_dyn_start - _start
  219. _rel_dyn_end_ofs:
  220. .word __rel_dyn_end - _start
  221. _dynsym_start_ofs:
  222. .word __dynsym_start - _start
  223. /*
  224. *************************************************************************
  225. *
  226. * CPU_init_critical registers
  227. *
  228. * setup important registers
  229. * setup memory timing
  230. *
  231. *************************************************************************
  232. */
  233. /* Interupt-Controller base address */
  234. IC_BASE: .word 0x90050000
  235. #define ICMR 0x04
  236. /* Reset-Controller */
  237. RST_BASE: .word 0x90030000
  238. #define RSRR 0x00
  239. #define RCSR 0x04
  240. /* PWR */
  241. PWR_BASE: .word 0x90020000
  242. #define PSPR 0x08
  243. #define PPCR 0x14
  244. cpuspeed: .word CONFIG_SYS_CPUSPEED
  245. cpu_init_crit:
  246. /*
  247. * mask all IRQs
  248. */
  249. ldr r0, IC_BASE
  250. mov r1, #0x00
  251. str r1, [r0, #ICMR]
  252. /* set clock speed */
  253. ldr r0, PWR_BASE
  254. ldr r1, cpuspeed
  255. str r1, [r0, #PPCR]
  256. /*
  257. * before relocating, we have to setup RAM timing
  258. * because memory timing is board-dependend, you will
  259. * find a lowlevel_init.S in your board directory.
  260. */
  261. mov ip, lr
  262. bl lowlevel_init
  263. mov lr, ip
  264. /*
  265. * disable MMU stuff and enable I-cache
  266. */
  267. mrc p15,0,r0,c1,c0
  268. bic r0, r0, #0x00002000 @ clear bit 13 (X)
  269. bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
  270. orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
  271. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  272. mcr p15,0,r0,c1,c0
  273. /*
  274. * flush v4 I/D caches
  275. */
  276. mov r0, #0
  277. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  278. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  279. mov pc, lr
  280. /*
  281. *************************************************************************
  282. *
  283. * Interrupt handling
  284. *
  285. *************************************************************************
  286. */
  287. @
  288. @ IRQ stack frame.
  289. @
  290. #define S_FRAME_SIZE 72
  291. #define S_OLD_R0 68
  292. #define S_PSR 64
  293. #define S_PC 60
  294. #define S_LR 56
  295. #define S_SP 52
  296. #define S_IP 48
  297. #define S_FP 44
  298. #define S_R10 40
  299. #define S_R9 36
  300. #define S_R8 32
  301. #define S_R7 28
  302. #define S_R6 24
  303. #define S_R5 20
  304. #define S_R4 16
  305. #define S_R3 12
  306. #define S_R2 8
  307. #define S_R1 4
  308. #define S_R0 0
  309. #define MODE_SVC 0x13
  310. #define I_BIT 0x80
  311. /*
  312. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  313. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  314. */
  315. .macro bad_save_user_regs
  316. sub sp, sp, #S_FRAME_SIZE
  317. stmia sp, {r0 - r12} @ Calling r0-r12
  318. add r8, sp, #S_PC
  319. ldr r2, IRQ_STACK_START_IN
  320. ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
  321. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  322. add r5, sp, #S_SP
  323. mov r1, lr
  324. stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
  325. mov r0, sp
  326. .endm
  327. .macro irq_save_user_regs
  328. sub sp, sp, #S_FRAME_SIZE
  329. stmia sp, {r0 - r12} @ Calling r0-r12
  330. add r8, sp, #S_PC
  331. stmdb r8, {sp, lr}^ @ Calling SP, LR
  332. str lr, [r8, #0] @ Save calling PC
  333. mrs r6, spsr
  334. str r6, [r8, #4] @ Save CPSR
  335. str r0, [r8, #8] @ Save OLD_R0
  336. mov r0, sp
  337. .endm
  338. .macro irq_restore_user_regs
  339. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  340. mov r0, r0
  341. ldr lr, [sp, #S_PC] @ Get PC
  342. add sp, sp, #S_FRAME_SIZE
  343. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  344. .endm
  345. .macro get_bad_stack
  346. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  347. str lr, [r13] @ save caller lr / spsr
  348. mrs lr, spsr
  349. str lr, [r13, #4]
  350. mov r13, #MODE_SVC @ prepare SVC-Mode
  351. msr spsr_c, r13
  352. mov lr, pc
  353. movs pc, lr
  354. .endm
  355. .macro get_irq_stack @ setup IRQ stack
  356. ldr sp, IRQ_STACK_START
  357. .endm
  358. .macro get_fiq_stack @ setup FIQ stack
  359. ldr sp, FIQ_STACK_START
  360. .endm
  361. /*
  362. * exception handlers
  363. */
  364. .align 5
  365. undefined_instruction:
  366. get_bad_stack
  367. bad_save_user_regs
  368. bl do_undefined_instruction
  369. .align 5
  370. software_interrupt:
  371. get_bad_stack
  372. bad_save_user_regs
  373. bl do_software_interrupt
  374. .align 5
  375. prefetch_abort:
  376. get_bad_stack
  377. bad_save_user_regs
  378. bl do_prefetch_abort
  379. .align 5
  380. data_abort:
  381. get_bad_stack
  382. bad_save_user_regs
  383. bl do_data_abort
  384. .align 5
  385. not_used:
  386. get_bad_stack
  387. bad_save_user_regs
  388. bl do_not_used
  389. #ifdef CONFIG_USE_IRQ
  390. .align 5
  391. irq:
  392. get_irq_stack
  393. irq_save_user_regs
  394. bl do_irq
  395. irq_restore_user_regs
  396. .align 5
  397. fiq:
  398. get_fiq_stack
  399. /* someone ought to write a more effiction fiq_save_user_regs */
  400. irq_save_user_regs
  401. bl do_fiq
  402. irq_restore_user_regs
  403. #else
  404. .align 5
  405. irq:
  406. get_bad_stack
  407. bad_save_user_regs
  408. bl do_irq
  409. .align 5
  410. fiq:
  411. get_bad_stack
  412. bad_save_user_regs
  413. bl do_fiq
  414. #endif
  415. .align 5
  416. .globl reset_cpu
  417. reset_cpu:
  418. ldr r0, RST_BASE
  419. mov r1, #0x0 @ set bit 3-0 ...
  420. str r1, [r0, #RCSR] @ ... to clear in RCSR
  421. mov r1, #0x1
  422. str r1, [r0, #RSRR] @ and perform reset
  423. b reset_cpu @ silly, but repeat endlessly