start.S 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353
  1. /*
  2. * Startup Code for S3C44B0 CPU-core
  3. *
  4. * (C) Copyright 2004
  5. * DAVE Srl
  6. *
  7. * http://www.dave-tech.it
  8. * http://www.wawnet.biz
  9. * mailto:info@wawnet.biz
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <asm-offsets.h>
  30. #include <config.h>
  31. #include <version.h>
  32. /*
  33. * Jump vector table
  34. */
  35. .globl _start
  36. _start: b reset
  37. add pc, pc, #0x0c000000
  38. add pc, pc, #0x0c000000
  39. add pc, pc, #0x0c000000
  40. add pc, pc, #0x0c000000
  41. add pc, pc, #0x0c000000
  42. add pc, pc, #0x0c000000
  43. add pc, pc, #0x0c000000
  44. .balignl 16,0xdeadbeef
  45. /*
  46. *************************************************************************
  47. *
  48. * Startup Code (reset vector)
  49. *
  50. * do important init only if we don't start from memory!
  51. * relocate u-boot to ram
  52. * setup stack
  53. * jump to second stage
  54. *
  55. *************************************************************************
  56. */
  57. .globl _TEXT_BASE
  58. _TEXT_BASE:
  59. .word CONFIG_SYS_TEXT_BASE
  60. /*
  61. * These are defined in the board-specific linker script.
  62. * Subtracting _start from them lets the linker put their
  63. * relative position in the executable instead of leaving
  64. * them null.
  65. */
  66. .globl _bss_start_ofs
  67. _bss_start_ofs:
  68. .word __bss_start - _start
  69. .globl _bss_end_ofs
  70. _bss_end_ofs:
  71. .word __bss_end__ - _start
  72. .globl _end_ofs
  73. _end_ofs:
  74. .word _end - _start
  75. #ifdef CONFIG_USE_IRQ
  76. /* IRQ stack memory (calculated at run-time) */
  77. .globl IRQ_STACK_START
  78. IRQ_STACK_START:
  79. .word 0x0badc0de
  80. /* IRQ stack memory (calculated at run-time) */
  81. .globl FIQ_STACK_START
  82. FIQ_STACK_START:
  83. .word 0x0badc0de
  84. #endif
  85. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  86. .globl IRQ_STACK_START_IN
  87. IRQ_STACK_START_IN:
  88. .word 0x0badc0de
  89. /*
  90. * the actual reset code
  91. */
  92. reset:
  93. /*
  94. * set the cpu to SVC32 mode
  95. */
  96. mrs r0,cpsr
  97. bic r0,r0,#0x1f
  98. orr r0,r0,#0xd3
  99. msr cpsr,r0
  100. /*
  101. * we do sys-critical inits only at reboot,
  102. * not when booting from ram!
  103. */
  104. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  105. bl cpu_init_crit
  106. /*
  107. * before relocating, we have to setup RAM timing
  108. * because memory timing is board-dependend, you will
  109. * find a lowlevel_init.S in your board directory.
  110. */
  111. bl lowlevel_init
  112. #endif
  113. /* Set stackpointer in internal RAM to call board_init_f */
  114. call_board_init_f:
  115. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  116. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  117. ldr r0,=0x00000000
  118. bl board_init_f
  119. /*------------------------------------------------------------------------------*/
  120. /*
  121. * void relocate_code (addr_sp, gd, addr_moni)
  122. *
  123. * This "function" does not return, instead it continues in RAM
  124. * after relocating the monitor code.
  125. *
  126. */
  127. .globl relocate_code
  128. relocate_code:
  129. mov r4, r0 /* save addr_sp */
  130. mov r5, r1 /* save addr of gd */
  131. mov r6, r2 /* save addr of destination */
  132. /* Set up the stack */
  133. stack_setup:
  134. mov sp, r4
  135. adr r0, _start
  136. cmp r0, r6
  137. beq clear_bss /* skip relocation */
  138. mov r1, r6 /* r1 <- scratch for copy_loop */
  139. ldr r3, _bss_start_ofs
  140. add r2, r0, r3 /* r2 <- source end address */
  141. copy_loop:
  142. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  143. stmia r1!, {r9-r10} /* copy to target address [r1] */
  144. cmp r0, r2 /* until source end address [r2] */
  145. blo copy_loop
  146. #ifndef CONFIG_SPL_BUILD
  147. /*
  148. * fix .rel.dyn relocations
  149. */
  150. ldr r0, _TEXT_BASE /* r0 <- Text base */
  151. sub r9, r6, r0 /* r9 <- relocation offset */
  152. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  153. add r10, r10, r0 /* r10 <- sym table in FLASH */
  154. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  155. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  156. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  157. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  158. fixloop:
  159. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  160. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  161. ldr r1, [r2, #4]
  162. and r7, r1, #0xff
  163. cmp r7, #23 /* relative fixup? */
  164. beq fixrel
  165. cmp r7, #2 /* absolute fixup? */
  166. beq fixabs
  167. /* ignore unknown type of fixup */
  168. b fixnext
  169. fixabs:
  170. /* absolute fix: set location to (offset) symbol value */
  171. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  172. add r1, r10, r1 /* r1 <- address of symbol in table */
  173. ldr r1, [r1, #4] /* r1 <- symbol value */
  174. add r1, r1, r9 /* r1 <- relocated sym addr */
  175. b fixnext
  176. fixrel:
  177. /* relative fix: increase location by offset */
  178. ldr r1, [r0]
  179. add r1, r1, r9
  180. fixnext:
  181. str r1, [r0]
  182. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  183. cmp r2, r3
  184. blo fixloop
  185. #endif
  186. clear_bss:
  187. #ifndef CONFIG_SPL_BUILD
  188. ldr r0, _bss_start_ofs
  189. ldr r1, _bss_end_ofs
  190. mov r4, r6 /* reloc addr */
  191. add r0, r0, r4
  192. add r1, r1, r4
  193. mov r2, #0x00000000 /* clear */
  194. clbss_l:str r2, [r0] /* clear loop... */
  195. add r0, r0, #4
  196. cmp r0, r1
  197. bne clbss_l
  198. bl coloured_LED_init
  199. bl red_LED_on
  200. #endif
  201. /*
  202. * We are done. Do not return, instead branch to second part of board
  203. * initialization, now running from RAM.
  204. */
  205. ldr r0, _board_init_r_ofs
  206. adr r1, _start
  207. add lr, r0, r1
  208. add lr, lr, r9
  209. /* setup parameters for board_init_r */
  210. mov r0, r5 /* gd_t */
  211. mov r1, r6 /* dest_addr */
  212. /* jump to it ... */
  213. mov pc, lr
  214. _board_init_r_ofs:
  215. .word board_init_r - _start
  216. _rel_dyn_start_ofs:
  217. .word __rel_dyn_start - _start
  218. _rel_dyn_end_ofs:
  219. .word __rel_dyn_end - _start
  220. _dynsym_start_ofs:
  221. .word __dynsym_start - _start
  222. /*
  223. *************************************************************************
  224. *
  225. * CPU_init_critical registers
  226. *
  227. * setup important registers
  228. * setup memory timing
  229. *
  230. *************************************************************************
  231. */
  232. #define INTCON (0x01c00000+0x200000)
  233. #define INTMSK (0x01c00000+0x20000c)
  234. #define LOCKTIME (0x01c00000+0x18000c)
  235. #define PLLCON (0x01c00000+0x180000)
  236. #define CLKCON (0x01c00000+0x180004)
  237. #define WTCON (0x01c00000+0x130000)
  238. cpu_init_crit:
  239. /* disable watch dog */
  240. ldr r0, =WTCON
  241. ldr r1, =0x0
  242. str r1, [r0]
  243. /*
  244. * mask all IRQs by clearing all bits in the INTMRs
  245. */
  246. ldr r1,=INTMSK
  247. ldr r0, =0x03fffeff
  248. str r0, [r1]
  249. ldr r1, =INTCON
  250. ldr r0, =0x05
  251. str r0, [r1]
  252. /* Set Clock Control Register */
  253. ldr r1, =LOCKTIME
  254. ldrb r0, =800
  255. strb r0, [r1]
  256. ldr r1, =PLLCON
  257. #if CONFIG_S3C44B0_CLOCK_SPEED==66
  258. ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
  259. #elif CONFIG_S3C44B0_CLOCK_SPEED==75
  260. ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
  261. #else
  262. # error CONFIG_S3C44B0_CLOCK_SPEED undefined
  263. #endif
  264. str r0, [r1]
  265. ldr r1,=CLKCON
  266. ldr r0, =0x7ff8
  267. str r0, [r1]
  268. mov pc, lr
  269. /*************************************************/
  270. /* interrupt vectors */
  271. /*************************************************/
  272. real_vectors:
  273. b reset
  274. b undefined_instruction
  275. b software_interrupt
  276. b prefetch_abort
  277. b data_abort
  278. b not_used
  279. b irq
  280. b fiq
  281. /*************************************************/
  282. undefined_instruction:
  283. mov r6, #3
  284. b reset
  285. software_interrupt:
  286. mov r6, #4
  287. b reset
  288. prefetch_abort:
  289. mov r6, #5
  290. b reset
  291. data_abort:
  292. mov r6, #6
  293. b reset
  294. not_used:
  295. /* we *should* never reach this */
  296. mov r6, #7
  297. b reset
  298. irq:
  299. mov r6, #8
  300. b reset
  301. fiq:
  302. mov r6, #9
  303. b reset