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  1. /* vi: set ts=8 sw=8 noet: */
  2. /*
  3. * u-boot - Startup Code for XScale IXP
  4. *
  5. * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
  6. *
  7. * Based on startup code example contained in the
  8. * Intel IXP4xx Programmer's Guide and past u-boot Start.S
  9. * samples.
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <asm-offsets.h>
  30. #include <config.h>
  31. #include <version.h>
  32. #include <asm/arch/ixp425.h>
  33. #define MMU_Control_M 0x001 /* Enable MMU */
  34. #define MMU_Control_A 0x002 /* Enable address alignment faults */
  35. #define MMU_Control_C 0x004 /* Enable cache */
  36. #define MMU_Control_W 0x008 /* Enable write-buffer */
  37. #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
  38. #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
  39. #define MMU_Control_L 0x040 /* Compatability: */
  40. #define MMU_Control_B 0x080 /* Enable Big-Endian */
  41. #define MMU_Control_S 0x100 /* Enable system protection */
  42. #define MMU_Control_R 0x200 /* Enable ROM protection */
  43. #define MMU_Control_I 0x1000 /* Enable Instruction cache */
  44. #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
  45. #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  46. /*
  47. * Macro definitions
  48. */
  49. /* Delay a bit */
  50. .macro DELAY_FOR cycles, reg0
  51. ldr \reg0, =\cycles
  52. subs \reg0, \reg0, #1
  53. subne pc, pc, #0xc
  54. .endm
  55. /* wait for coprocessor write complete */
  56. .macro CPWAIT reg
  57. mrc p15,0,\reg,c2,c0,0
  58. mov \reg,\reg
  59. sub pc,pc,#4
  60. .endm
  61. .globl _start
  62. _start:
  63. ldr pc, _reset
  64. ldr pc, _undefined_instruction
  65. ldr pc, _software_interrupt
  66. ldr pc, _prefetch_abort
  67. ldr pc, _data_abort
  68. ldr pc, _not_used
  69. ldr pc, _irq
  70. ldr pc, _fiq
  71. _reset: .word reset
  72. _undefined_instruction: .word undefined_instruction
  73. _software_interrupt: .word software_interrupt
  74. _prefetch_abort: .word prefetch_abort
  75. _data_abort: .word data_abort
  76. _not_used: .word not_used
  77. _irq: .word irq
  78. _fiq: .word fiq
  79. .balignl 16,0xdeadbeef
  80. /*
  81. * Startup Code (reset vector)
  82. *
  83. * do important init only if we don't start from memory!
  84. * - relocate armboot to ram
  85. * - setup stack
  86. * - jump to second stage
  87. */
  88. .globl _TEXT_BASE
  89. _TEXT_BASE:
  90. .word CONFIG_SYS_TEXT_BASE
  91. /*
  92. * These are defined in the board-specific linker script.
  93. * Subtracting _start from them lets the linker put their
  94. * relative position in the executable instead of leaving
  95. * them null.
  96. */
  97. .globl _bss_start_ofs
  98. _bss_start_ofs:
  99. .word __bss_start - _start
  100. .globl _bss_end_ofs
  101. _bss_end_ofs:
  102. .word __bss_end__ - _start
  103. .globl _end_ofs
  104. _end_ofs:
  105. .word _end - _start
  106. #ifdef CONFIG_USE_IRQ
  107. /* IRQ stack memory (calculated at run-time) */
  108. .globl IRQ_STACK_START
  109. IRQ_STACK_START:
  110. .word 0x0badc0de
  111. /* IRQ stack memory (calculated at run-time) */
  112. .globl FIQ_STACK_START
  113. FIQ_STACK_START:
  114. .word 0x0badc0de
  115. #endif
  116. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  117. .globl IRQ_STACK_START_IN
  118. IRQ_STACK_START_IN:
  119. .word 0x0badc0de
  120. /*
  121. * the actual reset code
  122. */
  123. reset:
  124. /* disable mmu, set big-endian */
  125. mov r0, #0xf8
  126. mcr p15, 0, r0, c1, c0, 0
  127. CPWAIT r0
  128. /* invalidate I & D caches & BTB */
  129. mcr p15, 0, r0, c7, c7, 0
  130. CPWAIT r0
  131. /* invalidate I & Data TLB */
  132. mcr p15, 0, r0, c8, c7, 0
  133. CPWAIT r0
  134. /* drain write and fill buffers */
  135. mcr p15, 0, r0, c7, c10, 4
  136. CPWAIT r0
  137. /* disable write buffer coalescing */
  138. mrc p15, 0, r0, c1, c0, 1
  139. orr r0, r0, #1
  140. mcr p15, 0, r0, c1, c0, 1
  141. CPWAIT r0
  142. /* set EXP CS0 to the optimum timing */
  143. ldr r1, =CONFIG_SYS_EXP_CS0
  144. ldr r2, =IXP425_EXP_CS0
  145. str r1, [r2]
  146. /* make sure flash is visible at 0 */
  147. mov r1, #CONFIG_SYS_SDR_CONFIG
  148. ldr r2, =IXP425_SDR_CONFIG
  149. str r1, [r2]
  150. /* disable refresh cycles */
  151. mov r1, #0
  152. ldr r3, =IXP425_SDR_REFRESH
  153. str r1, [r3]
  154. /* send nop command */
  155. mov r1, #3
  156. ldr r4, =IXP425_SDR_IR
  157. str r1, [r4]
  158. DELAY_FOR 0x4000, r0
  159. /* set SDRAM internal refresh val */
  160. ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
  161. str r1, [r3]
  162. DELAY_FOR 0x4000, r0
  163. /* send precharge-all command to close all open banks */
  164. mov r1, #2
  165. str r1, [r4]
  166. DELAY_FOR 0x4000, r0
  167. /* provide 8 auto-refresh cycles */
  168. mov r1, #4
  169. mov r5, #8
  170. 111: str r1, [r4]
  171. DELAY_FOR 0x100, r0
  172. subs r5, r5, #1
  173. bne 111b
  174. /* set mode register in sdram */
  175. mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
  176. str r1, [r4]
  177. DELAY_FOR 0x4000, r0
  178. /* send normal operation command */
  179. mov r1, #6
  180. str r1, [r4]
  181. DELAY_FOR 0x4000, r0
  182. /* invalidate I & D caches & BTB */
  183. mcr p15, 0, r0, c7, c7, 0
  184. CPWAIT r0
  185. /* invalidate I & Data TLB */
  186. mcr p15, 0, r0, c8, c7, 0
  187. CPWAIT r0
  188. /* drain write and fill buffers */
  189. mcr p15, 0, r0, c7, c10, 4
  190. CPWAIT r0
  191. /* remove flash mirror at 0x00000000 */
  192. ldr r2, =IXP425_EXP_CFG0
  193. ldr r1, [r2]
  194. bic r1, r1, #0x80000000
  195. str r1, [r2]
  196. /* invalidate I & Data TLB */
  197. mcr p15, 0, r0, c8, c7, 0
  198. CPWAIT r0
  199. /* enable I cache */
  200. mrc p15, 0, r0, c1, c0, 0
  201. orr r0, r0, #MMU_Control_I
  202. mcr p15, 0, r0, c1, c0, 0
  203. CPWAIT r0
  204. mrs r0,cpsr /* set the cpu to SVC32 mode */
  205. bic r0,r0,#0x1f /* (superviser mode, M=10011) */
  206. orr r0,r0,#0x13
  207. msr cpsr,r0
  208. /* Set initial stackpointer in SDRAM to call board_init_f */
  209. call_board_init_f:
  210. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  211. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  212. ldr r0,=0x00000000
  213. bl board_init_f
  214. /*------------------------------------------------------------------------------*/
  215. /*
  216. * void relocate_code (addr_sp, gd, addr_moni)
  217. *
  218. * This "function" does not return, instead it continues in RAM
  219. * after relocating the monitor code.
  220. *
  221. */
  222. .globl relocate_code
  223. relocate_code:
  224. mov r4, r0 /* save addr_sp */
  225. mov r5, r1 /* save addr of gd */
  226. mov r6, r2 /* save addr of destination */
  227. /* Set up the stack */
  228. stack_setup:
  229. mov sp, r4
  230. adr r0, _start
  231. cmp r0, r6
  232. beq clear_bss /* skip relocation */
  233. mov r1, r6 /* r1 <- scratch for copy_loop */
  234. ldr r3, _bss_start_ofs
  235. add r2, r0, r3 /* r2 <- source end address */
  236. copy_loop:
  237. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  238. stmia r1!, {r9-r10} /* copy to target address [r1] */
  239. cmp r0, r2 /* until source end address [r2] */
  240. blo copy_loop
  241. #ifndef CONFIG_SPL_BUILD
  242. /*
  243. * fix .rel.dyn relocations
  244. */
  245. ldr r0, _TEXT_BASE /* r0 <- Text base */
  246. sub r9, r6, r0 /* r9 <- relocation offset */
  247. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  248. add r10, r10, r0 /* r10 <- sym table in FLASH */
  249. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  250. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  251. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  252. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  253. fixloop:
  254. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  255. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  256. ldr r1, [r2, #4]
  257. and r7, r1, #0xff
  258. cmp r7, #23 /* relative fixup? */
  259. beq fixrel
  260. cmp r7, #2 /* absolute fixup? */
  261. beq fixabs
  262. /* ignore unknown type of fixup */
  263. b fixnext
  264. fixabs:
  265. /* absolute fix: set location to (offset) symbol value */
  266. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  267. add r1, r10, r1 /* r1 <- address of symbol in table */
  268. ldr r1, [r1, #4] /* r1 <- symbol value */
  269. add r1, r1, r9 /* r1 <- relocated sym addr */
  270. b fixnext
  271. fixrel:
  272. /* relative fix: increase location by offset */
  273. ldr r1, [r0]
  274. add r1, r1, r9
  275. fixnext:
  276. str r1, [r0]
  277. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  278. cmp r2, r3
  279. blo fixloop
  280. #endif
  281. clear_bss:
  282. #ifndef CONFIG_SPL_BUILD
  283. ldr r0, _bss_start_ofs
  284. ldr r1, _bss_end_ofs
  285. mov r4, r6 /* reloc addr */
  286. add r0, r0, r4
  287. add r1, r1, r4
  288. mov r2, #0x00000000 /* clear */
  289. clbss_l:str r2, [r0] /* clear loop... */
  290. add r0, r0, #4
  291. cmp r0, r1
  292. bne clbss_l
  293. bl coloured_LED_init
  294. bl red_LED_on
  295. #endif
  296. /*
  297. * We are done. Do not return, instead branch to second part of board
  298. * initialization, now running from RAM.
  299. */
  300. ldr r0, _board_init_r_ofs
  301. adr r1, _start
  302. add lr, r0, r1
  303. add lr, lr, r9
  304. /* setup parameters for board_init_r */
  305. mov r0, r5 /* gd_t */
  306. mov r1, r6 /* dest_addr */
  307. /* jump to it ... */
  308. mov pc, lr
  309. _board_init_r_ofs:
  310. .word board_init_r - _start
  311. _rel_dyn_start_ofs:
  312. .word __rel_dyn_start - _start
  313. _rel_dyn_end_ofs:
  314. .word __rel_dyn_end - _start
  315. _dynsym_start_ofs:
  316. .word __dynsym_start - _start
  317. /****************************************************************************/
  318. /* */
  319. /* Interrupt handling */
  320. /* */
  321. /****************************************************************************/
  322. /* IRQ stack frame */
  323. #define S_FRAME_SIZE 72
  324. #define S_OLD_R0 68
  325. #define S_PSR 64
  326. #define S_PC 60
  327. #define S_LR 56
  328. #define S_SP 52
  329. #define S_IP 48
  330. #define S_FP 44
  331. #define S_R10 40
  332. #define S_R9 36
  333. #define S_R8 32
  334. #define S_R7 28
  335. #define S_R6 24
  336. #define S_R5 20
  337. #define S_R4 16
  338. #define S_R3 12
  339. #define S_R2 8
  340. #define S_R1 4
  341. #define S_R0 0
  342. #define MODE_SVC 0x13
  343. /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
  344. .macro bad_save_user_regs
  345. sub sp, sp, #S_FRAME_SIZE
  346. stmia sp, {r0 - r12} /* Calling r0-r12 */
  347. add r8, sp, #S_PC
  348. ldr r2, IRQ_STACK_START_IN
  349. ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
  350. add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
  351. add r5, sp, #S_SP
  352. mov r1, lr
  353. stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
  354. mov r0, sp
  355. .endm
  356. /* use irq_save_user_regs / irq_restore_user_regs for */
  357. /* IRQ/FIQ handling */
  358. .macro irq_save_user_regs
  359. sub sp, sp, #S_FRAME_SIZE
  360. stmia sp, {r0 - r12} /* Calling r0-r12 */
  361. add r8, sp, #S_PC
  362. stmdb r8, {sp, lr}^ /* Calling SP, LR */
  363. str lr, [r8, #0] /* Save calling PC */
  364. mrs r6, spsr
  365. str r6, [r8, #4] /* Save CPSR */
  366. str r0, [r8, #8] /* Save OLD_R0 */
  367. mov r0, sp
  368. .endm
  369. .macro irq_restore_user_regs
  370. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  371. mov r0, r0
  372. ldr lr, [sp, #S_PC] @ Get PC
  373. add sp, sp, #S_FRAME_SIZE
  374. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  375. .endm
  376. .macro get_bad_stack
  377. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  378. str lr, [r13] @ save caller lr / spsr
  379. mrs lr, spsr
  380. str lr, [r13, #4]
  381. mov r13, #MODE_SVC @ prepare SVC-Mode
  382. msr spsr_c, r13
  383. mov lr, pc
  384. movs pc, lr
  385. .endm
  386. .macro get_irq_stack @ setup IRQ stack
  387. ldr sp, IRQ_STACK_START
  388. .endm
  389. .macro get_fiq_stack @ setup FIQ stack
  390. ldr sp, FIQ_STACK_START
  391. .endm
  392. /****************************************************************************/
  393. /* */
  394. /* exception handlers */
  395. /* */
  396. /****************************************************************************/
  397. .align 5
  398. undefined_instruction:
  399. get_bad_stack
  400. bad_save_user_regs
  401. bl do_undefined_instruction
  402. .align 5
  403. software_interrupt:
  404. get_bad_stack
  405. bad_save_user_regs
  406. bl do_software_interrupt
  407. .align 5
  408. prefetch_abort:
  409. get_bad_stack
  410. bad_save_user_regs
  411. bl do_prefetch_abort
  412. .align 5
  413. data_abort:
  414. get_bad_stack
  415. bad_save_user_regs
  416. bl do_data_abort
  417. .align 5
  418. not_used:
  419. get_bad_stack
  420. bad_save_user_regs
  421. bl do_not_used
  422. #ifdef CONFIG_USE_IRQ
  423. .align 5
  424. irq:
  425. get_irq_stack
  426. irq_save_user_regs
  427. bl do_irq
  428. irq_restore_user_regs
  429. .align 5
  430. fiq:
  431. get_fiq_stack
  432. irq_save_user_regs /* someone ought to write a more */
  433. bl do_fiq /* effiction fiq_save_user_regs */
  434. irq_restore_user_regs
  435. #else
  436. .align 5
  437. irq:
  438. get_bad_stack
  439. bad_save_user_regs
  440. bl do_irq
  441. .align 5
  442. fiq:
  443. get_bad_stack
  444. bad_save_user_regs
  445. bl do_fiq
  446. #endif
  447. /****************************************************************************/
  448. /* */
  449. /* Reset function: Use Watchdog to reset */
  450. /* */
  451. /****************************************************************************/
  452. .align 5
  453. .globl reset_cpu
  454. reset_cpu:
  455. ldr r1, =0x482e
  456. ldr r2, =IXP425_OSWK
  457. str r1, [r2]
  458. ldr r1, =0x0fff
  459. ldr r2, =IXP425_OSWT
  460. str r1, [r2]
  461. ldr r1, =0x5
  462. ldr r2, =IXP425_OSWE
  463. str r1, [r2]
  464. b reset_endless
  465. reset_endless:
  466. b reset_endless