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  1. /*
  2. * armboot - Startup Code for ARM926EJS CPU-core
  3. *
  4. * Copyright (c) 2003 Texas Instruments
  5. *
  6. * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  7. *
  8. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  11. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13. * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
  14. *
  15. * See file CREDITS for list of people who contributed to this
  16. * project.
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License as
  20. * published by the Free Software Foundation; either version 2 of
  21. * the License, or (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31. * MA 02111-1307 USA
  32. */
  33. #include <asm-offsets.h>
  34. #include <config.h>
  35. #include <version.h>
  36. /*
  37. *************************************************************************
  38. *
  39. * Jump vector table as in table 3.1 in [1]
  40. *
  41. *************************************************************************
  42. */
  43. .globl _start
  44. _start:
  45. b reset
  46. ldr pc, _undefined_instruction
  47. ldr pc, _software_interrupt
  48. ldr pc, _prefetch_abort
  49. ldr pc, _data_abort
  50. ldr pc, _not_used
  51. ldr pc, _irq
  52. ldr pc, _fiq
  53. _undefined_instruction:
  54. .word undefined_instruction
  55. _software_interrupt:
  56. .word software_interrupt
  57. _prefetch_abort:
  58. .word prefetch_abort
  59. _data_abort:
  60. .word data_abort
  61. _not_used:
  62. .word not_used
  63. _irq:
  64. .word irq
  65. _fiq:
  66. .word fiq
  67. .balignl 16,0xdeadbeef
  68. _vectors_end:
  69. /*
  70. *************************************************************************
  71. *
  72. * Startup Code (reset vector)
  73. *
  74. * do important init only if we don't start from memory!
  75. * setup Memory and board specific bits prior to relocation.
  76. * relocate armboot to ram
  77. * setup stack
  78. *
  79. *************************************************************************
  80. */
  81. .globl _TEXT_BASE
  82. _TEXT_BASE:
  83. .word CONFIG_SYS_TEXT_BASE
  84. /*
  85. * These are defined in the board-specific linker script.
  86. * Subtracting _start from them lets the linker put their
  87. * relative position in the executable instead of leaving
  88. * them null.
  89. */
  90. .globl _bss_start_ofs
  91. _bss_start_ofs:
  92. .word __bss_start - _start
  93. .globl _bss_end_ofs
  94. _bss_end_ofs:
  95. .word __bss_end__ - _start
  96. .globl _end_ofs
  97. _end_ofs:
  98. .word _end - _start
  99. #ifdef CONFIG_USE_IRQ
  100. /* IRQ stack memory (calculated at run-time) */
  101. .globl IRQ_STACK_START
  102. IRQ_STACK_START:
  103. .word 0x0badc0de
  104. /* IRQ stack memory (calculated at run-time) */
  105. .globl FIQ_STACK_START
  106. FIQ_STACK_START:
  107. .word 0x0badc0de
  108. #endif
  109. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  110. .globl IRQ_STACK_START_IN
  111. IRQ_STACK_START_IN:
  112. .word 0x0badc0de
  113. /*
  114. * the actual reset code
  115. */
  116. reset:
  117. /*
  118. * set the cpu to SVC32 mode
  119. */
  120. mrs r0,cpsr
  121. bic r0,r0,#0x1f
  122. orr r0,r0,#0xd3
  123. msr cpsr,r0
  124. /*
  125. * we do sys-critical inits only at reboot,
  126. * not when booting from ram!
  127. */
  128. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  129. bl cpu_init_crit
  130. #endif
  131. /* Set stackpointer in internal RAM to call board_init_f */
  132. call_board_init_f:
  133. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  134. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  135. ldr r0,=0x00000000
  136. bl board_init_f
  137. /*------------------------------------------------------------------------------*/
  138. /*
  139. * void relocate_code (addr_sp, gd, addr_moni)
  140. *
  141. * This "function" does not return, instead it continues in RAM
  142. * after relocating the monitor code.
  143. *
  144. */
  145. .globl relocate_code
  146. relocate_code:
  147. mov r4, r0 /* save addr_sp */
  148. mov r5, r1 /* save addr of gd */
  149. mov r6, r2 /* save addr of destination */
  150. /* Set up the stack */
  151. stack_setup:
  152. mov sp, r4
  153. adr r0, _start
  154. cmp r0, r6
  155. beq clear_bss /* skip relocation */
  156. mov r1, r6 /* r1 <- scratch for copy_loop */
  157. ldr r3, _bss_start_ofs
  158. add r2, r0, r3 /* r2 <- source end address */
  159. copy_loop:
  160. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  161. stmia r1!, {r9-r10} /* copy to target address [r1] */
  162. cmp r0, r2 /* until source end address [r2] */
  163. blo copy_loop
  164. #ifndef CONFIG_SPL_BUILD
  165. /*
  166. * fix .rel.dyn relocations
  167. */
  168. ldr r0, _TEXT_BASE /* r0 <- Text base */
  169. sub r9, r6, r0 /* r9 <- relocation offset */
  170. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  171. add r10, r10, r0 /* r10 <- sym table in FLASH */
  172. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  173. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  174. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  175. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  176. fixloop:
  177. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  178. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  179. ldr r1, [r2, #4]
  180. and r7, r1, #0xff
  181. cmp r7, #23 /* relative fixup? */
  182. beq fixrel
  183. cmp r7, #2 /* absolute fixup? */
  184. beq fixabs
  185. /* ignore unknown type of fixup */
  186. b fixnext
  187. fixabs:
  188. /* absolute fix: set location to (offset) symbol value */
  189. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  190. add r1, r10, r1 /* r1 <- address of symbol in table */
  191. ldr r1, [r1, #4] /* r1 <- symbol value */
  192. add r1, r1, r9 /* r1 <- relocated sym addr */
  193. b fixnext
  194. fixrel:
  195. /* relative fix: increase location by offset */
  196. ldr r1, [r0]
  197. add r1, r1, r9
  198. fixnext:
  199. str r1, [r0]
  200. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  201. cmp r2, r3
  202. blo fixloop
  203. #endif
  204. clear_bss:
  205. #ifndef CONFIG_SPL_BUILD
  206. ldr r0, _bss_start_ofs
  207. ldr r1, _bss_end_ofs
  208. mov r4, r6 /* reloc addr */
  209. add r0, r0, r4
  210. add r1, r1, r4
  211. mov r2, #0x00000000 /* clear */
  212. clbss_l:str r2, [r0] /* clear loop... */
  213. add r0, r0, #4
  214. cmp r0, r1
  215. blo clbss_l
  216. #endif
  217. /*
  218. * We are done. Do not return, instead branch to second part of board
  219. * initialization, now running from RAM.
  220. */
  221. #ifdef CONFIG_NAND_SPL
  222. ldr pc, _nand_boot
  223. _nand_boot: .word nand_boot
  224. #else
  225. ldr r0, _board_init_r_ofs
  226. adr r1, _start
  227. add lr, r0, r1
  228. add lr, lr, r9
  229. /* setup parameters for board_init_r */
  230. mov r0, r5 /* gd_t */
  231. mov r1, r6 /* dest_addr */
  232. /* jump to it ... */
  233. mov pc, lr
  234. _board_init_r_ofs:
  235. .word board_init_r - _start
  236. #endif
  237. _rel_dyn_start_ofs:
  238. .word __rel_dyn_start - _start
  239. _rel_dyn_end_ofs:
  240. .word __rel_dyn_end - _start
  241. _dynsym_start_ofs:
  242. .word __dynsym_start - _start
  243. /*
  244. *************************************************************************
  245. *
  246. * CPU_init_critical registers
  247. *
  248. * setup important registers
  249. * setup memory timing
  250. *
  251. *************************************************************************
  252. */
  253. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  254. cpu_init_crit:
  255. /*
  256. * flush v4 I/D caches
  257. */
  258. mov r0, #0
  259. mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
  260. mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
  261. /*
  262. * disable MMU stuff and caches
  263. */
  264. mrc p15, 0, r0, c1, c0, 0
  265. bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
  266. bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  267. orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
  268. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  269. mcr p15, 0, r0, c1, c0, 0
  270. /*
  271. * Go setup Memory and board specific bits prior to relocation.
  272. */
  273. mov ip, lr /* perserve link reg across call */
  274. bl lowlevel_init /* go setup memory */
  275. mov lr, ip /* restore link */
  276. mov pc, lr /* back to my caller */
  277. #endif
  278. /*
  279. *************************************************************************
  280. *
  281. * Interrupt handling
  282. *
  283. *************************************************************************
  284. */
  285. @
  286. @ IRQ stack frame.
  287. @
  288. #define S_FRAME_SIZE 72
  289. #define S_OLD_R0 68
  290. #define S_PSR 64
  291. #define S_PC 60
  292. #define S_LR 56
  293. #define S_SP 52
  294. #define S_IP 48
  295. #define S_FP 44
  296. #define S_R10 40
  297. #define S_R9 36
  298. #define S_R8 32
  299. #define S_R7 28
  300. #define S_R6 24
  301. #define S_R5 20
  302. #define S_R4 16
  303. #define S_R3 12
  304. #define S_R2 8
  305. #define S_R1 4
  306. #define S_R0 0
  307. #define MODE_SVC 0x13
  308. #define I_BIT 0x80
  309. /*
  310. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  311. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  312. */
  313. .macro bad_save_user_regs
  314. @ carve out a frame on current user stack
  315. sub sp, sp, #S_FRAME_SIZE
  316. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  317. ldr r2, IRQ_STACK_START_IN
  318. @ get values for "aborted" pc and cpsr (into parm regs)
  319. ldmia r2, {r2 - r3}
  320. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  321. add r5, sp, #S_SP
  322. mov r1, lr
  323. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  324. mov r0, sp @ save current stack into r0 (param register)
  325. .endm
  326. .macro irq_save_user_regs
  327. sub sp, sp, #S_FRAME_SIZE
  328. stmia sp, {r0 - r12} @ Calling r0-r12
  329. @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  330. add r8, sp, #S_PC
  331. stmdb r8, {sp, lr}^ @ Calling SP, LR
  332. str lr, [r8, #0] @ Save calling PC
  333. mrs r6, spsr
  334. str r6, [r8, #4] @ Save CPSR
  335. str r0, [r8, #8] @ Save OLD_R0
  336. mov r0, sp
  337. .endm
  338. .macro irq_restore_user_regs
  339. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  340. mov r0, r0
  341. ldr lr, [sp, #S_PC] @ Get PC
  342. add sp, sp, #S_FRAME_SIZE
  343. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  344. .endm
  345. .macro get_bad_stack
  346. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  347. str lr, [r13] @ save caller lr in position 0 of saved stack
  348. mrs lr, spsr @ get the spsr
  349. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  350. mov r13, #MODE_SVC @ prepare SVC-Mode
  351. @ msr spsr_c, r13
  352. msr spsr, r13 @ switch modes, make sure moves will execute
  353. mov lr, pc @ capture return pc
  354. movs pc, lr @ jump to next instruction & switch modes.
  355. .endm
  356. .macro get_irq_stack @ setup IRQ stack
  357. ldr sp, IRQ_STACK_START
  358. .endm
  359. .macro get_fiq_stack @ setup FIQ stack
  360. ldr sp, FIQ_STACK_START
  361. .endm
  362. /*
  363. * exception handlers
  364. */
  365. .align 5
  366. undefined_instruction:
  367. get_bad_stack
  368. bad_save_user_regs
  369. bl do_undefined_instruction
  370. .align 5
  371. software_interrupt:
  372. get_bad_stack
  373. bad_save_user_regs
  374. bl do_software_interrupt
  375. .align 5
  376. prefetch_abort:
  377. get_bad_stack
  378. bad_save_user_regs
  379. bl do_prefetch_abort
  380. .align 5
  381. data_abort:
  382. get_bad_stack
  383. bad_save_user_regs
  384. bl do_data_abort
  385. .align 5
  386. not_used:
  387. get_bad_stack
  388. bad_save_user_regs
  389. bl do_not_used
  390. #ifdef CONFIG_USE_IRQ
  391. .align 5
  392. irq:
  393. get_irq_stack
  394. irq_save_user_regs
  395. bl do_irq
  396. irq_restore_user_regs
  397. .align 5
  398. fiq:
  399. get_fiq_stack
  400. /* someone ought to write a more effiction fiq_save_user_regs */
  401. irq_save_user_regs
  402. bl do_fiq
  403. irq_restore_user_regs
  404. #else
  405. .align 5
  406. irq:
  407. get_bad_stack
  408. bad_save_user_regs
  409. bl do_irq
  410. .align 5
  411. fiq:
  412. get_bad_stack
  413. bad_save_user_regs
  414. bl do_fiq
  415. #endif
  416. # ifdef CONFIG_INTEGRATOR
  417. /* Satisfied by general board level routine */
  418. #else
  419. .align 5
  420. .globl reset_cpu
  421. reset_cpu:
  422. ldr r1, rstctl1 /* get clkm1 reset ctl */
  423. mov r3, #0x0
  424. strh r3, [r1] /* clear it */
  425. mov r3, #0x8
  426. strh r3, [r1] /* force dsp+arm reset */
  427. _loop_forever:
  428. b _loop_forever
  429. rstctl1:
  430. .word 0xfffece10
  431. #endif /* #ifdef CONFIG_INTEGRATOR */