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  1. /*
  2. * armboot - Startup Code for ARM1176 CPU-core
  3. *
  4. * Copyright (c) 2007 Samsung Electronics
  5. *
  6. * Copyright (C) 2008
  7. * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  28. * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  29. * jsgood (jsgood.yang@samsung.com)
  30. * Base codes by scsuh (sc.suh)
  31. */
  32. #include <asm-offsets.h>
  33. #include <config.h>
  34. #include <version.h>
  35. #ifdef CONFIG_ENABLE_MMU
  36. #include <asm/proc/domain.h>
  37. #endif
  38. #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
  39. #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
  40. #endif
  41. /*
  42. *************************************************************************
  43. *
  44. * Jump vector table as in table 3.1 in [1]
  45. *
  46. *************************************************************************
  47. */
  48. .globl _start
  49. _start: b reset
  50. #ifndef CONFIG_NAND_SPL
  51. ldr pc, _undefined_instruction
  52. ldr pc, _software_interrupt
  53. ldr pc, _prefetch_abort
  54. ldr pc, _data_abort
  55. ldr pc, _not_used
  56. ldr pc, _irq
  57. ldr pc, _fiq
  58. _undefined_instruction:
  59. .word undefined_instruction
  60. _software_interrupt:
  61. .word software_interrupt
  62. _prefetch_abort:
  63. .word prefetch_abort
  64. _data_abort:
  65. .word data_abort
  66. _not_used:
  67. .word not_used
  68. _irq:
  69. .word irq
  70. _fiq:
  71. .word fiq
  72. _pad:
  73. .word 0x12345678 /* now 16*4=64 */
  74. #else
  75. . = _start + 64
  76. #endif
  77. .global _end_vect
  78. _end_vect:
  79. .balignl 16,0xdeadbeef
  80. /*
  81. *************************************************************************
  82. *
  83. * Startup Code (reset vector)
  84. *
  85. * do important init only if we don't start from memory!
  86. * setup Memory and board specific bits prior to relocation.
  87. * relocate armboot to ram
  88. * setup stack
  89. *
  90. *************************************************************************
  91. */
  92. .globl _TEXT_BASE
  93. _TEXT_BASE:
  94. .word CONFIG_SYS_TEXT_BASE
  95. /*
  96. * Below variable is very important because we use MMU in U-Boot.
  97. * Without it, we cannot run code correctly before MMU is ON.
  98. * by scsuh.
  99. */
  100. _TEXT_PHY_BASE:
  101. .word CONFIG_SYS_PHY_UBOOT_BASE
  102. /*
  103. * These are defined in the board-specific linker script.
  104. * Subtracting _start from them lets the linker put their
  105. * relative position in the executable instead of leaving
  106. * them null.
  107. */
  108. .globl _bss_start_ofs
  109. _bss_start_ofs:
  110. .word __bss_start - _start
  111. .globl _bss_end_ofs
  112. _bss_end_ofs:
  113. .word __bss_end__ - _start
  114. .globl _end_ofs
  115. _end_ofs:
  116. .word _end - _start
  117. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  118. .globl IRQ_STACK_START_IN
  119. IRQ_STACK_START_IN:
  120. .word 0x0badc0de
  121. /*
  122. * the actual reset code
  123. */
  124. reset:
  125. /*
  126. * set the cpu to SVC32 mode
  127. */
  128. mrs r0, cpsr
  129. bic r0, r0, #0x3f
  130. orr r0, r0, #0xd3
  131. msr cpsr, r0
  132. /*
  133. *************************************************************************
  134. *
  135. * CPU_init_critical registers
  136. *
  137. * setup important registers
  138. * setup memory timing
  139. *
  140. *************************************************************************
  141. */
  142. /*
  143. * we do sys-critical inits only at reboot,
  144. * not when booting from ram!
  145. */
  146. cpu_init_crit:
  147. /*
  148. * When booting from NAND - it has definitely been a reset, so, no need
  149. * to flush caches and disable the MMU
  150. */
  151. #ifndef CONFIG_NAND_SPL
  152. /*
  153. * flush v4 I/D caches
  154. */
  155. mov r0, #0
  156. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  157. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  158. /*
  159. * disable MMU stuff and caches
  160. */
  161. mrc p15, 0, r0, c1, c0, 0
  162. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  163. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  164. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  165. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  166. /* Prepare to disable the MMU */
  167. adr r2, mmu_disable_phys
  168. sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
  169. b mmu_disable
  170. .align 5
  171. /* Run in a single cache-line */
  172. mmu_disable:
  173. mcr p15, 0, r0, c1, c0, 0
  174. nop
  175. nop
  176. mov pc, r2
  177. mmu_disable_phys:
  178. #ifdef CONFIG_DISABLE_TCM
  179. /*
  180. * Disable the TCMs
  181. */
  182. mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
  183. cmp r0, #0
  184. beq skip_tcmdisable
  185. mov r1, #0
  186. mov r2, #1
  187. tst r0, r2
  188. mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
  189. tst r0, r2, LSL #16
  190. mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
  191. skip_tcmdisable:
  192. #endif
  193. #endif
  194. #ifdef CONFIG_PERIPORT_REMAP
  195. /* Peri port setup */
  196. ldr r0, =CONFIG_PERIPORT_BASE
  197. orr r0, r0, #CONFIG_PERIPORT_SIZE
  198. mcr p15,0,r0,c15,c2,4
  199. #endif
  200. /*
  201. * Go setup Memory and board specific bits prior to relocation.
  202. */
  203. bl lowlevel_init /* go setup pll,mux,memory */
  204. /* Set stackpointer in internal RAM to call board_init_f */
  205. call_board_init_f:
  206. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  207. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  208. ldr r0,=0x00000000
  209. bl board_init_f
  210. /*------------------------------------------------------------------------------*/
  211. /*
  212. * void relocate_code (addr_sp, gd, addr_moni)
  213. *
  214. * This "function" does not return, instead it continues in RAM
  215. * after relocating the monitor code.
  216. *
  217. */
  218. .globl relocate_code
  219. relocate_code:
  220. mov r4, r0 /* save addr_sp */
  221. mov r5, r1 /* save addr of gd */
  222. mov r6, r2 /* save addr of destination */
  223. /* Set up the stack */
  224. stack_setup:
  225. mov sp, r4
  226. adr r0, _start
  227. cmp r0, r6
  228. beq clear_bss /* skip relocation */
  229. mov r1, r6 /* r1 <- scratch for copy_loop */
  230. ldr r3, _bss_start_ofs
  231. add r2, r0, r3 /* r2 <- source end address */
  232. copy_loop:
  233. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  234. stmia r1!, {r9-r10} /* copy to target address [r1] */
  235. cmp r0, r2 /* until source end address [r2] */
  236. blo copy_loop
  237. #ifndef CONFIG_SPL_BUILD
  238. /*
  239. * fix .rel.dyn relocations
  240. */
  241. ldr r0, _TEXT_BASE /* r0 <- Text base */
  242. sub r9, r6, r0 /* r9 <- relocation offset */
  243. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  244. add r10, r10, r0 /* r10 <- sym table in FLASH */
  245. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  246. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  247. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  248. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  249. fixloop:
  250. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  251. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  252. ldr r1, [r2, #4]
  253. and r7, r1, #0xff
  254. cmp r7, #23 /* relative fixup? */
  255. beq fixrel
  256. cmp r7, #2 /* absolute fixup? */
  257. beq fixabs
  258. /* ignore unknown type of fixup */
  259. b fixnext
  260. fixabs:
  261. /* absolute fix: set location to (offset) symbol value */
  262. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  263. add r1, r10, r1 /* r1 <- address of symbol in table */
  264. ldr r1, [r1, #4] /* r1 <- symbol value */
  265. add r1, r1, r9 /* r1 <- relocated sym addr */
  266. b fixnext
  267. fixrel:
  268. /* relative fix: increase location by offset */
  269. ldr r1, [r0]
  270. add r1, r1, r9
  271. fixnext:
  272. str r1, [r0]
  273. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  274. cmp r2, r3
  275. blo fixloop
  276. #endif
  277. #ifdef CONFIG_ENABLE_MMU
  278. enable_mmu:
  279. /* enable domain access */
  280. ldr r5, =0x0000ffff
  281. mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
  282. /* Set the TTB register */
  283. ldr r0, _mmu_table_base
  284. ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
  285. ldr r2, =0xfff00000
  286. bic r0, r0, r2
  287. orr r1, r0, r1
  288. mcr p15, 0, r1, c2, c0, 0
  289. /* Enable the MMU */
  290. mrc p15, 0, r0, c1, c0, 0
  291. orr r0, r0, #1 /* Set CR_M to enable MMU */
  292. /* Prepare to enable the MMU */
  293. adr r1, skip_hw_init
  294. and r1, r1, #0x3fc
  295. ldr r2, _TEXT_BASE
  296. ldr r3, =0xfff00000
  297. and r2, r2, r3
  298. orr r2, r2, r1
  299. b mmu_enable
  300. .align 5
  301. /* Run in a single cache-line */
  302. mmu_enable:
  303. mcr p15, 0, r0, c1, c0, 0
  304. nop
  305. nop
  306. mov pc, r2
  307. skip_hw_init:
  308. #endif
  309. clear_bss:
  310. #ifndef CONFIG_SPL_BUILD
  311. ldr r0, _bss_start_ofs
  312. ldr r1, _bss_end_ofs
  313. mov r4, r6 /* reloc addr */
  314. add r0, r0, r4
  315. add r1, r1, r4
  316. mov r2, #0x00000000 /* clear */
  317. clbss_l:str r2, [r0] /* clear loop... */
  318. add r0, r0, #4
  319. cmp r0, r1
  320. bne clbss_l
  321. #ifndef CONFIG_NAND_SPL
  322. bl coloured_LED_init
  323. bl red_LED_on
  324. #endif
  325. #endif
  326. /*
  327. * We are done. Do not return, instead branch to second part of board
  328. * initialization, now running from RAM.
  329. */
  330. #ifdef CONFIG_NAND_SPL
  331. ldr pc, _nand_boot
  332. _nand_boot: .word nand_boot
  333. #else
  334. ldr r0, _board_init_r_ofs
  335. adr r1, _start
  336. add lr, r0, r1
  337. add lr, lr, r9
  338. /* setup parameters for board_init_r */
  339. mov r0, r5 /* gd_t */
  340. mov r1, r6 /* dest_addr */
  341. /* jump to it ... */
  342. mov pc, lr
  343. _board_init_r_ofs:
  344. .word board_init_r - _start
  345. #endif
  346. _rel_dyn_start_ofs:
  347. .word __rel_dyn_start - _start
  348. _rel_dyn_end_ofs:
  349. .word __rel_dyn_end - _start
  350. _dynsym_start_ofs:
  351. .word __dynsym_start - _start
  352. #ifdef CONFIG_ENABLE_MMU
  353. _mmu_table_base:
  354. .word mmu_table
  355. #endif
  356. #ifndef CONFIG_NAND_SPL
  357. /*
  358. * we assume that cache operation is done before. (eg. cleanup_before_linux())
  359. * actually, we don't need to do anything about cache if not use d-cache in
  360. * U-Boot. So, in this function we clean only MMU. by scsuh
  361. *
  362. * void theLastJump(void *kernel, int arch_num, uint boot_params);
  363. */
  364. #ifdef CONFIG_ENABLE_MMU
  365. .globl theLastJump
  366. theLastJump:
  367. mov r9, r0
  368. ldr r3, =0xfff00000
  369. ldr r4, _TEXT_PHY_BASE
  370. adr r5, phy_last_jump
  371. bic r5, r5, r3
  372. orr r5, r5, r4
  373. mov pc, r5
  374. phy_last_jump:
  375. /*
  376. * disable MMU stuff
  377. */
  378. mrc p15, 0, r0, c1, c0, 0
  379. bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
  380. bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  381. orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
  382. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  383. mcr p15, 0, r0, c1, c0, 0
  384. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  385. mov r0, #0
  386. mov pc, r9
  387. #endif
  388. /*
  389. *************************************************************************
  390. *
  391. * Interrupt handling
  392. *
  393. *************************************************************************
  394. */
  395. @
  396. @ IRQ stack frame.
  397. @
  398. #define S_FRAME_SIZE 72
  399. #define S_OLD_R0 68
  400. #define S_PSR 64
  401. #define S_PC 60
  402. #define S_LR 56
  403. #define S_SP 52
  404. #define S_IP 48
  405. #define S_FP 44
  406. #define S_R10 40
  407. #define S_R9 36
  408. #define S_R8 32
  409. #define S_R7 28
  410. #define S_R6 24
  411. #define S_R5 20
  412. #define S_R4 16
  413. #define S_R3 12
  414. #define S_R2 8
  415. #define S_R1 4
  416. #define S_R0 0
  417. #define MODE_SVC 0x13
  418. #define I_BIT 0x80
  419. /*
  420. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  421. */
  422. .macro bad_save_user_regs
  423. /* carve out a frame on current user stack */
  424. sub sp, sp, #S_FRAME_SIZE
  425. /* Save user registers (now in svc mode) r0-r12 */
  426. stmia sp, {r0 - r12}
  427. ldr r2, IRQ_STACK_START_IN
  428. /* get values for "aborted" pc and cpsr (into parm regs) */
  429. ldmia r2, {r2 - r3}
  430. /* grab pointer to old stack */
  431. add r0, sp, #S_FRAME_SIZE
  432. add r5, sp, #S_SP
  433. mov r1, lr
  434. /* save sp_SVC, lr_SVC, pc, cpsr */
  435. stmia r5, {r0 - r3}
  436. /* save current stack into r0 (param register) */
  437. mov r0, sp
  438. .endm
  439. .macro get_bad_stack
  440. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  441. /* save caller lr in position 0 of saved stack */
  442. str lr, [r13]
  443. /* get the spsr */
  444. mrs lr, spsr
  445. /* save spsr in position 1 of saved stack */
  446. str lr, [r13, #4]
  447. /* prepare SVC-Mode */
  448. mov r13, #MODE_SVC
  449. @ msr spsr_c, r13
  450. /* switch modes, make sure moves will execute */
  451. msr spsr, r13
  452. /* capture return pc */
  453. mov lr, pc
  454. /* jump to next instruction & switch modes. */
  455. movs pc, lr
  456. .endm
  457. .macro get_bad_stack_swi
  458. /* space on current stack for scratch reg. */
  459. sub r13, r13, #4
  460. /* save R0's value. */
  461. str r0, [r13]
  462. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  463. /* save caller lr in position 0 of saved stack */
  464. str lr, [r0]
  465. /* get the spsr */
  466. mrs r0, spsr
  467. /* save spsr in position 1 of saved stack */
  468. str lr, [r0, #4]
  469. /* restore r0 */
  470. ldr r0, [r13]
  471. /* pop stack entry */
  472. add r13, r13, #4
  473. .endm
  474. /*
  475. * exception handlers
  476. */
  477. .align 5
  478. undefined_instruction:
  479. get_bad_stack
  480. bad_save_user_regs
  481. bl do_undefined_instruction
  482. .align 5
  483. software_interrupt:
  484. get_bad_stack_swi
  485. bad_save_user_regs
  486. bl do_software_interrupt
  487. .align 5
  488. prefetch_abort:
  489. get_bad_stack
  490. bad_save_user_regs
  491. bl do_prefetch_abort
  492. .align 5
  493. data_abort:
  494. get_bad_stack
  495. bad_save_user_regs
  496. bl do_data_abort
  497. .align 5
  498. not_used:
  499. get_bad_stack
  500. bad_save_user_regs
  501. bl do_not_used
  502. .align 5
  503. irq:
  504. get_bad_stack
  505. bad_save_user_regs
  506. bl do_irq
  507. .align 5
  508. fiq:
  509. get_bad_stack
  510. bad_save_user_regs
  511. bl do_fiq
  512. #endif /* CONFIG_NAND_SPL */