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  1. /*
  2. * armboot - Startup Code for OMP2420/ARM1136 CPU-core
  3. *
  4. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  5. *
  6. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  7. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  8. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  9. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  10. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <asm-offsets.h>
  31. #include <config.h>
  32. #include <version.h>
  33. .globl _start
  34. _start: b reset
  35. #ifdef CONFIG_SPL_BUILD
  36. ldr pc, _hang
  37. ldr pc, _hang
  38. ldr pc, _hang
  39. ldr pc, _hang
  40. ldr pc, _hang
  41. ldr pc, _hang
  42. ldr pc, _hang
  43. _hang:
  44. .word do_hang
  45. .word 0x12345678
  46. .word 0x12345678
  47. .word 0x12345678
  48. .word 0x12345678
  49. .word 0x12345678
  50. .word 0x12345678
  51. .word 0x12345678 /* now 16*4=64 */
  52. #else
  53. ldr pc, _undefined_instruction
  54. ldr pc, _software_interrupt
  55. ldr pc, _prefetch_abort
  56. ldr pc, _data_abort
  57. ldr pc, _not_used
  58. ldr pc, _irq
  59. ldr pc, _fiq
  60. _undefined_instruction: .word undefined_instruction
  61. _software_interrupt: .word software_interrupt
  62. _prefetch_abort: .word prefetch_abort
  63. _data_abort: .word data_abort
  64. _not_used: .word not_used
  65. _irq: .word irq
  66. _fiq: .word fiq
  67. _pad: .word 0x12345678 /* now 16*4=64 */
  68. #endif /* CONFIG_SPL_BUILD */
  69. .global _end_vect
  70. _end_vect:
  71. .balignl 16,0xdeadbeef
  72. /*
  73. *************************************************************************
  74. *
  75. * Startup Code (reset vector)
  76. *
  77. * do important init only if we don't start from memory!
  78. * setup Memory and board specific bits prior to relocation.
  79. * relocate armboot to ram
  80. * setup stack
  81. *
  82. *************************************************************************
  83. */
  84. .globl _TEXT_BASE
  85. _TEXT_BASE:
  86. .word CONFIG_SYS_TEXT_BASE
  87. /*
  88. * These are defined in the board-specific linker script.
  89. * Subtracting _start from them lets the linker put their
  90. * relative position in the executable instead of leaving
  91. * them null.
  92. */
  93. .globl _bss_start_ofs
  94. _bss_start_ofs:
  95. .word __bss_start - _start
  96. .globl _bss_end_ofs
  97. _bss_end_ofs:
  98. .word __bss_end__ - _start
  99. .globl _end_ofs
  100. _end_ofs:
  101. .word _end - _start
  102. #ifdef CONFIG_USE_IRQ
  103. /* IRQ stack memory (calculated at run-time) */
  104. .globl IRQ_STACK_START
  105. IRQ_STACK_START:
  106. .word 0x0badc0de
  107. /* IRQ stack memory (calculated at run-time) */
  108. .globl FIQ_STACK_START
  109. FIQ_STACK_START:
  110. .word 0x0badc0de
  111. #endif
  112. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  113. .globl IRQ_STACK_START_IN
  114. IRQ_STACK_START_IN:
  115. .word 0x0badc0de
  116. /*
  117. * the actual reset code
  118. */
  119. reset:
  120. /*
  121. * set the cpu to SVC32 mode
  122. */
  123. mrs r0,cpsr
  124. bic r0,r0,#0x1f
  125. orr r0,r0,#0xd3
  126. msr cpsr,r0
  127. #ifdef CONFIG_OMAP2420H4
  128. /* Copy vectors to mask ROM indirect addr */
  129. adr r0, _start /* r0 <- current position of code */
  130. add r0, r0, #4 /* skip reset vector */
  131. mov r2, #64 /* r2 <- size to copy */
  132. add r2, r0, r2 /* r2 <- source end address */
  133. mov r1, #SRAM_OFFSET0 /* build vect addr */
  134. mov r3, #SRAM_OFFSET1
  135. add r1, r1, r3
  136. mov r3, #SRAM_OFFSET2
  137. add r1, r1, r3
  138. next:
  139. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  140. stmia r1!, {r3-r10} /* copy to target address [r1] */
  141. cmp r0, r2 /* until source end address [r2] */
  142. bne next /* loop until equal */
  143. bl cpy_clk_code /* put dpll adjust code behind vectors */
  144. #endif
  145. /* the mask ROM code should have PLL and others stable */
  146. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  147. bl cpu_init_crit
  148. #endif
  149. /* Set stackpointer in internal RAM to call board_init_f */
  150. call_board_init_f:
  151. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  152. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  153. ldr r0,=0x00000000
  154. bl board_init_f
  155. /*------------------------------------------------------------------------------*/
  156. /*
  157. * void relocate_code (addr_sp, gd, addr_moni)
  158. *
  159. * This "function" does not return, instead it continues in RAM
  160. * after relocating the monitor code.
  161. *
  162. */
  163. .globl relocate_code
  164. relocate_code:
  165. mov r4, r0 /* save addr_sp */
  166. mov r5, r1 /* save addr of gd */
  167. mov r6, r2 /* save addr of destination */
  168. /* Set up the stack */
  169. stack_setup:
  170. mov sp, r4
  171. adr r0, _start
  172. cmp r0, r6
  173. beq clear_bss /* skip relocation */
  174. mov r1, r6 /* r1 <- scratch for copy_loop */
  175. ldr r3, _bss_start_ofs
  176. add r2, r0, r3 /* r2 <- source end address */
  177. copy_loop:
  178. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  179. stmia r1!, {r9-r10} /* copy to target address [r1] */
  180. cmp r0, r2 /* until source end address [r2] */
  181. blo copy_loop
  182. #ifndef CONFIG_SPL_BUILD
  183. /*
  184. * fix .rel.dyn relocations
  185. */
  186. ldr r0, _TEXT_BASE /* r0 <- Text base */
  187. sub r9, r6, r0 /* r9 <- relocation offset */
  188. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  189. add r10, r10, r0 /* r10 <- sym table in FLASH */
  190. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  191. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  192. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  193. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  194. fixloop:
  195. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  196. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  197. ldr r1, [r2, #4]
  198. and r7, r1, #0xff
  199. cmp r7, #23 /* relative fixup? */
  200. beq fixrel
  201. cmp r7, #2 /* absolute fixup? */
  202. beq fixabs
  203. /* ignore unknown type of fixup */
  204. b fixnext
  205. fixabs:
  206. /* absolute fix: set location to (offset) symbol value */
  207. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  208. add r1, r10, r1 /* r1 <- address of symbol in table */
  209. ldr r1, [r1, #4] /* r1 <- symbol value */
  210. add r1, r1, r9 /* r1 <- relocated sym addr */
  211. b fixnext
  212. fixrel:
  213. /* relative fix: increase location by offset */
  214. ldr r1, [r0]
  215. add r1, r1, r9
  216. fixnext:
  217. str r1, [r0]
  218. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  219. cmp r2, r3
  220. blo fixloop
  221. #endif
  222. clear_bss:
  223. #ifndef CONFIG_SPL_BUILD
  224. ldr r0, _bss_start_ofs
  225. ldr r1, _bss_end_ofs
  226. mov r4, r6 /* reloc addr */
  227. add r0, r0, r4
  228. add r1, r1, r4
  229. mov r2, #0x00000000 /* clear */
  230. clbss_l:str r2, [r0] /* clear loop... */
  231. add r0, r0, #4
  232. cmp r0, r1
  233. bne clbss_l
  234. #endif /* #ifndef CONFIG_SPL_BUILD */
  235. /*
  236. * We are done. Do not return, instead branch to second part of board
  237. * initialization, now running from RAM.
  238. */
  239. #ifdef CONFIG_NAND_SPL
  240. ldr r0, _nand_boot_ofs
  241. mov pc, r0
  242. _nand_boot_ofs:
  243. .word nand_boot
  244. #else
  245. jump_2_ram:
  246. ldr r0, _board_init_r_ofs
  247. ldr r1, _TEXT_BASE
  248. add lr, r0, r1
  249. add lr, lr, r9
  250. /* setup parameters for board_init_r */
  251. mov r0, r5 /* gd_t */
  252. mov r1, r6 /* dest_addr */
  253. /* jump to it ... */
  254. mov pc, lr
  255. _board_init_r_ofs:
  256. .word board_init_r - _start
  257. #endif
  258. _rel_dyn_start_ofs:
  259. .word __rel_dyn_start - _start
  260. _rel_dyn_end_ofs:
  261. .word __rel_dyn_end - _start
  262. _dynsym_start_ofs:
  263. .word __dynsym_start - _start
  264. /*
  265. *************************************************************************
  266. *
  267. * CPU_init_critical registers
  268. *
  269. * setup important registers
  270. * setup memory timing
  271. *
  272. *************************************************************************
  273. */
  274. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  275. cpu_init_crit:
  276. /*
  277. * flush v4 I/D caches
  278. */
  279. mov r0, #0
  280. mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
  281. mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
  282. /*
  283. * disable MMU stuff and caches
  284. */
  285. mrc p15, 0, r0, c1, c0, 0
  286. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  287. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  288. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  289. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  290. mcr p15, 0, r0, c1, c0, 0
  291. /*
  292. * Jump to board specific initialization... The Mask ROM will have already initialized
  293. * basic memory. Go here to bump up clock rate and handle wake up conditions.
  294. */
  295. mov ip, lr /* persevere link reg across call */
  296. bl lowlevel_init /* go setup pll,mux,memory */
  297. mov lr, ip /* restore link */
  298. mov pc, lr /* back to my caller */
  299. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  300. #ifndef CONFIG_SPL_BUILD
  301. /*
  302. *************************************************************************
  303. *
  304. * Interrupt handling
  305. *
  306. *************************************************************************
  307. */
  308. @
  309. @ IRQ stack frame.
  310. @
  311. #define S_FRAME_SIZE 72
  312. #define S_OLD_R0 68
  313. #define S_PSR 64
  314. #define S_PC 60
  315. #define S_LR 56
  316. #define S_SP 52
  317. #define S_IP 48
  318. #define S_FP 44
  319. #define S_R10 40
  320. #define S_R9 36
  321. #define S_R8 32
  322. #define S_R7 28
  323. #define S_R6 24
  324. #define S_R5 20
  325. #define S_R4 16
  326. #define S_R3 12
  327. #define S_R2 8
  328. #define S_R1 4
  329. #define S_R0 0
  330. #define MODE_SVC 0x13
  331. #define I_BIT 0x80
  332. /*
  333. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  334. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  335. */
  336. .macro bad_save_user_regs
  337. sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
  338. stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  339. ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
  340. ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
  341. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  342. add r5, sp, #S_SP
  343. mov r1, lr
  344. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  345. mov r0, sp @ save current stack into r0 (param register)
  346. .endm
  347. .macro irq_save_user_regs
  348. sub sp, sp, #S_FRAME_SIZE
  349. stmia sp, {r0 - r12} @ Calling r0-r12
  350. add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  351. stmdb r8, {sp, lr}^ @ Calling SP, LR
  352. str lr, [r8, #0] @ Save calling PC
  353. mrs r6, spsr
  354. str r6, [r8, #4] @ Save CPSR
  355. str r0, [r8, #8] @ Save OLD_R0
  356. mov r0, sp
  357. .endm
  358. .macro irq_restore_user_regs
  359. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  360. mov r0, r0
  361. ldr lr, [sp, #S_PC] @ Get PC
  362. add sp, sp, #S_FRAME_SIZE
  363. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  364. .endm
  365. .macro get_bad_stack
  366. ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
  367. str lr, [r13] @ save caller lr in position 0 of saved stack
  368. mrs lr, spsr @ get the spsr
  369. str lr, [r13, #4] @ save spsr in position 1 of saved stack
  370. mov r13, #MODE_SVC @ prepare SVC-Mode
  371. @ msr spsr_c, r13
  372. msr spsr, r13 @ switch modes, make sure moves will execute
  373. mov lr, pc @ capture return pc
  374. movs pc, lr @ jump to next instruction & switch modes.
  375. .endm
  376. .macro get_bad_stack_swi
  377. sub r13, r13, #4 @ space on current stack for scratch reg.
  378. str r0, [r13] @ save R0's value.
  379. ldr r0, IRQ_STACK_START_IN @ get data regions start
  380. str lr, [r0] @ save caller lr in position 0 of saved stack
  381. mrs r0, spsr @ get the spsr
  382. str lr, [r0, #4] @ save spsr in position 1 of saved stack
  383. ldr r0, [r13] @ restore r0
  384. add r13, r13, #4 @ pop stack entry
  385. .endm
  386. .macro get_irq_stack @ setup IRQ stack
  387. ldr sp, IRQ_STACK_START
  388. .endm
  389. .macro get_fiq_stack @ setup FIQ stack
  390. ldr sp, FIQ_STACK_START
  391. .endm
  392. #endif /* CONFIG_SPL_BUILD */
  393. /*
  394. * exception handlers
  395. */
  396. #ifdef CONFIG_SPL_BUILD
  397. .align 5
  398. do_hang:
  399. ldr sp, _TEXT_BASE /* use 32 words about stack */
  400. bl hang /* hang and never return */
  401. #else /* !CONFIG_SPL_BUILD */
  402. .align 5
  403. undefined_instruction:
  404. get_bad_stack
  405. bad_save_user_regs
  406. bl do_undefined_instruction
  407. .align 5
  408. software_interrupt:
  409. get_bad_stack_swi
  410. bad_save_user_regs
  411. bl do_software_interrupt
  412. .align 5
  413. prefetch_abort:
  414. get_bad_stack
  415. bad_save_user_regs
  416. bl do_prefetch_abort
  417. .align 5
  418. data_abort:
  419. get_bad_stack
  420. bad_save_user_regs
  421. bl do_data_abort
  422. .align 5
  423. not_used:
  424. get_bad_stack
  425. bad_save_user_regs
  426. bl do_not_used
  427. #ifdef CONFIG_USE_IRQ
  428. .align 5
  429. irq:
  430. get_irq_stack
  431. irq_save_user_regs
  432. bl do_irq
  433. irq_restore_user_regs
  434. .align 5
  435. fiq:
  436. get_fiq_stack
  437. /* someone ought to write a more effiction fiq_save_user_regs */
  438. irq_save_user_regs
  439. bl do_fiq
  440. irq_restore_user_regs
  441. #else
  442. .align 5
  443. irq:
  444. get_bad_stack
  445. bad_save_user_regs
  446. bl do_irq
  447. .align 5
  448. fiq:
  449. get_bad_stack
  450. bad_save_user_regs
  451. bl do_fiq
  452. #endif
  453. .align 5
  454. .global arm1136_cache_flush
  455. arm1136_cache_flush:
  456. #if !defined(CONFIG_SYS_ICACHE_OFF)
  457. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  458. #endif
  459. #if !defined(CONFIG_SYS_DCACHE_OFF)
  460. mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
  461. #endif
  462. mov pc, lr @ back to caller
  463. #endif /* CONFIG_SPL_BUILD */