e1000.c 171 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**************************************************************************
  3. Intel Pro 1000 for ppcboot/das-u-boot
  4. Drivers are port from Intel's Linux driver e1000-4.3.15
  5. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  6. tested on both gig copper and gig fiber boards
  7. ***************************************************************************/
  8. /*******************************************************************************
  9. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  10. Contact Information:
  11. Linux NICS <linux.nics@intel.com>
  12. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  13. *******************************************************************************/
  14. /*
  15. * Copyright (C) Archway Digital Solutions.
  16. *
  17. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  18. * 2/9/2002
  19. *
  20. * Copyright (C) Linux Networx.
  21. * Massive upgrade to work with the new intel gigabit NICs.
  22. * <ebiederman at lnxi dot com>
  23. *
  24. * Copyright 2011 Freescale Semiconductor, Inc.
  25. */
  26. #include <common.h>
  27. #include <command.h>
  28. #include <cpu_func.h>
  29. #include <dm.h>
  30. #include <errno.h>
  31. #include <log.h>
  32. #include <malloc.h>
  33. #include <memalign.h>
  34. #include <net.h>
  35. #include <pci.h>
  36. #include <linux/delay.h>
  37. #include "e1000.h"
  38. #include <asm/cache.h>
  39. #define TOUT_LOOP 100000
  40. #ifdef CONFIG_DM_ETH
  41. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  42. #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
  43. #else
  44. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  45. #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
  46. #endif
  47. #define E1000_DEFAULT_PCI_PBA 0x00000030
  48. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  49. /* NIC specific static variables go here */
  50. /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  51. #define E1000_BUFFER_ALIGN 128
  52. /*
  53. * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  54. * Concurrent receiving on multiple active Ethernet devices will not work.
  55. * Normally U-Boot does not support this anyway. To fix it in this driver,
  56. * move these buffers and the tx/rx pointers to struct e1000_hw.
  57. */
  58. DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  59. DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  60. DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  61. static int tx_tail;
  62. static int rx_tail, rx_last;
  63. #ifdef CONFIG_DM_ETH
  64. static int num_cards; /* Number of E1000 devices seen so far */
  65. #endif
  66. static struct pci_device_id e1000_supported[] = {
  67. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  77. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  78. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  79. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  84. /* E1000 PCIe card */
  85. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
  108. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
  109. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
  110. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
  111. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
  112. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
  113. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
  114. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
  115. {}
  116. };
  117. /* Function forward declarations */
  118. static int e1000_setup_link(struct e1000_hw *hw);
  119. static int e1000_setup_fiber_link(struct e1000_hw *hw);
  120. static int e1000_setup_copper_link(struct e1000_hw *hw);
  121. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  122. static void e1000_config_collision_dist(struct e1000_hw *hw);
  123. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  124. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  125. static int e1000_check_for_link(struct e1000_hw *hw);
  126. static int e1000_wait_autoneg(struct e1000_hw *hw);
  127. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  128. uint16_t * duplex);
  129. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  130. uint16_t * phy_data);
  131. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  132. uint16_t phy_data);
  133. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  134. static int e1000_phy_reset(struct e1000_hw *hw);
  135. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  136. static void e1000_set_media_type(struct e1000_hw *hw);
  137. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  138. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  139. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  140. #ifndef CONFIG_E1000_NO_NVM
  141. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  142. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  143. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  144. uint16_t words,
  145. uint16_t *data);
  146. /******************************************************************************
  147. * Raises the EEPROM's clock input.
  148. *
  149. * hw - Struct containing variables accessed by shared code
  150. * eecd - EECD's current value
  151. *****************************************************************************/
  152. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  153. {
  154. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  155. * wait 50 microseconds.
  156. */
  157. *eecd = *eecd | E1000_EECD_SK;
  158. E1000_WRITE_REG(hw, EECD, *eecd);
  159. E1000_WRITE_FLUSH(hw);
  160. udelay(50);
  161. }
  162. /******************************************************************************
  163. * Lowers the EEPROM's clock input.
  164. *
  165. * hw - Struct containing variables accessed by shared code
  166. * eecd - EECD's current value
  167. *****************************************************************************/
  168. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  169. {
  170. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  171. * wait 50 microseconds.
  172. */
  173. *eecd = *eecd & ~E1000_EECD_SK;
  174. E1000_WRITE_REG(hw, EECD, *eecd);
  175. E1000_WRITE_FLUSH(hw);
  176. udelay(50);
  177. }
  178. /******************************************************************************
  179. * Shift data bits out to the EEPROM.
  180. *
  181. * hw - Struct containing variables accessed by shared code
  182. * data - data to send to the EEPROM
  183. * count - number of bits to shift out
  184. *****************************************************************************/
  185. static void
  186. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  187. {
  188. uint32_t eecd;
  189. uint32_t mask;
  190. /* We need to shift "count" bits out to the EEPROM. So, value in the
  191. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  192. * In order to do this, "data" must be broken down into bits.
  193. */
  194. mask = 0x01 << (count - 1);
  195. eecd = E1000_READ_REG(hw, EECD);
  196. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  197. do {
  198. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  199. * and then raising and then lowering the clock (the SK bit controls
  200. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  201. * by setting "DI" to "0" and then raising and then lowering the clock.
  202. */
  203. eecd &= ~E1000_EECD_DI;
  204. if (data & mask)
  205. eecd |= E1000_EECD_DI;
  206. E1000_WRITE_REG(hw, EECD, eecd);
  207. E1000_WRITE_FLUSH(hw);
  208. udelay(50);
  209. e1000_raise_ee_clk(hw, &eecd);
  210. e1000_lower_ee_clk(hw, &eecd);
  211. mask = mask >> 1;
  212. } while (mask);
  213. /* We leave the "DI" bit set to "0" when we leave this routine. */
  214. eecd &= ~E1000_EECD_DI;
  215. E1000_WRITE_REG(hw, EECD, eecd);
  216. }
  217. /******************************************************************************
  218. * Shift data bits in from the EEPROM
  219. *
  220. * hw - Struct containing variables accessed by shared code
  221. *****************************************************************************/
  222. static uint16_t
  223. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  224. {
  225. uint32_t eecd;
  226. uint32_t i;
  227. uint16_t data;
  228. /* In order to read a register from the EEPROM, we need to shift 'count'
  229. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  230. * input to the EEPROM (setting the SK bit), and then reading the
  231. * value of the "DO" bit. During this "shifting in" process the
  232. * "DI" bit should always be clear.
  233. */
  234. eecd = E1000_READ_REG(hw, EECD);
  235. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  236. data = 0;
  237. for (i = 0; i < count; i++) {
  238. data = data << 1;
  239. e1000_raise_ee_clk(hw, &eecd);
  240. eecd = E1000_READ_REG(hw, EECD);
  241. eecd &= ~(E1000_EECD_DI);
  242. if (eecd & E1000_EECD_DO)
  243. data |= 1;
  244. e1000_lower_ee_clk(hw, &eecd);
  245. }
  246. return data;
  247. }
  248. /******************************************************************************
  249. * Returns EEPROM to a "standby" state
  250. *
  251. * hw - Struct containing variables accessed by shared code
  252. *****************************************************************************/
  253. void e1000_standby_eeprom(struct e1000_hw *hw)
  254. {
  255. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  256. uint32_t eecd;
  257. eecd = E1000_READ_REG(hw, EECD);
  258. if (eeprom->type == e1000_eeprom_microwire) {
  259. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  260. E1000_WRITE_REG(hw, EECD, eecd);
  261. E1000_WRITE_FLUSH(hw);
  262. udelay(eeprom->delay_usec);
  263. /* Clock high */
  264. eecd |= E1000_EECD_SK;
  265. E1000_WRITE_REG(hw, EECD, eecd);
  266. E1000_WRITE_FLUSH(hw);
  267. udelay(eeprom->delay_usec);
  268. /* Select EEPROM */
  269. eecd |= E1000_EECD_CS;
  270. E1000_WRITE_REG(hw, EECD, eecd);
  271. E1000_WRITE_FLUSH(hw);
  272. udelay(eeprom->delay_usec);
  273. /* Clock low */
  274. eecd &= ~E1000_EECD_SK;
  275. E1000_WRITE_REG(hw, EECD, eecd);
  276. E1000_WRITE_FLUSH(hw);
  277. udelay(eeprom->delay_usec);
  278. } else if (eeprom->type == e1000_eeprom_spi) {
  279. /* Toggle CS to flush commands */
  280. eecd |= E1000_EECD_CS;
  281. E1000_WRITE_REG(hw, EECD, eecd);
  282. E1000_WRITE_FLUSH(hw);
  283. udelay(eeprom->delay_usec);
  284. eecd &= ~E1000_EECD_CS;
  285. E1000_WRITE_REG(hw, EECD, eecd);
  286. E1000_WRITE_FLUSH(hw);
  287. udelay(eeprom->delay_usec);
  288. }
  289. }
  290. /***************************************************************************
  291. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  292. *
  293. * hw - Struct containing variables accessed by shared code
  294. ****************************************************************************/
  295. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  296. {
  297. uint32_t eecd = 0;
  298. DEBUGFUNC();
  299. if (hw->mac_type == e1000_ich8lan)
  300. return false;
  301. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  302. eecd = E1000_READ_REG(hw, EECD);
  303. /* Isolate bits 15 & 16 */
  304. eecd = ((eecd >> 15) & 0x03);
  305. /* If both bits are set, device is Flash type */
  306. if (eecd == 0x03)
  307. return false;
  308. }
  309. return true;
  310. }
  311. /******************************************************************************
  312. * Prepares EEPROM for access
  313. *
  314. * hw - Struct containing variables accessed by shared code
  315. *
  316. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  317. * function should be called before issuing a command to the EEPROM.
  318. *****************************************************************************/
  319. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  320. {
  321. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  322. uint32_t eecd, i = 0;
  323. DEBUGFUNC();
  324. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  325. return -E1000_ERR_SWFW_SYNC;
  326. eecd = E1000_READ_REG(hw, EECD);
  327. if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
  328. /* Request EEPROM Access */
  329. if (hw->mac_type > e1000_82544) {
  330. eecd |= E1000_EECD_REQ;
  331. E1000_WRITE_REG(hw, EECD, eecd);
  332. eecd = E1000_READ_REG(hw, EECD);
  333. while ((!(eecd & E1000_EECD_GNT)) &&
  334. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  335. i++;
  336. udelay(5);
  337. eecd = E1000_READ_REG(hw, EECD);
  338. }
  339. if (!(eecd & E1000_EECD_GNT)) {
  340. eecd &= ~E1000_EECD_REQ;
  341. E1000_WRITE_REG(hw, EECD, eecd);
  342. DEBUGOUT("Could not acquire EEPROM grant\n");
  343. return -E1000_ERR_EEPROM;
  344. }
  345. }
  346. }
  347. /* Setup EEPROM for Read/Write */
  348. if (eeprom->type == e1000_eeprom_microwire) {
  349. /* Clear SK and DI */
  350. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  351. E1000_WRITE_REG(hw, EECD, eecd);
  352. /* Set CS */
  353. eecd |= E1000_EECD_CS;
  354. E1000_WRITE_REG(hw, EECD, eecd);
  355. } else if (eeprom->type == e1000_eeprom_spi) {
  356. /* Clear SK and CS */
  357. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  358. E1000_WRITE_REG(hw, EECD, eecd);
  359. udelay(1);
  360. }
  361. return E1000_SUCCESS;
  362. }
  363. /******************************************************************************
  364. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  365. * is configured. Additionally, if this is ICH8, the flash controller GbE
  366. * registers must be mapped, or this will crash.
  367. *
  368. * hw - Struct containing variables accessed by shared code
  369. *****************************************************************************/
  370. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  371. {
  372. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  373. uint32_t eecd;
  374. int32_t ret_val = E1000_SUCCESS;
  375. uint16_t eeprom_size;
  376. if (hw->mac_type == e1000_igb)
  377. eecd = E1000_READ_REG(hw, I210_EECD);
  378. else
  379. eecd = E1000_READ_REG(hw, EECD);
  380. DEBUGFUNC();
  381. switch (hw->mac_type) {
  382. case e1000_82542_rev2_0:
  383. case e1000_82542_rev2_1:
  384. case e1000_82543:
  385. case e1000_82544:
  386. eeprom->type = e1000_eeprom_microwire;
  387. eeprom->word_size = 64;
  388. eeprom->opcode_bits = 3;
  389. eeprom->address_bits = 6;
  390. eeprom->delay_usec = 50;
  391. eeprom->use_eerd = false;
  392. eeprom->use_eewr = false;
  393. break;
  394. case e1000_82540:
  395. case e1000_82545:
  396. case e1000_82545_rev_3:
  397. case e1000_82546:
  398. case e1000_82546_rev_3:
  399. eeprom->type = e1000_eeprom_microwire;
  400. eeprom->opcode_bits = 3;
  401. eeprom->delay_usec = 50;
  402. if (eecd & E1000_EECD_SIZE) {
  403. eeprom->word_size = 256;
  404. eeprom->address_bits = 8;
  405. } else {
  406. eeprom->word_size = 64;
  407. eeprom->address_bits = 6;
  408. }
  409. eeprom->use_eerd = false;
  410. eeprom->use_eewr = false;
  411. break;
  412. case e1000_82541:
  413. case e1000_82541_rev_2:
  414. case e1000_82547:
  415. case e1000_82547_rev_2:
  416. if (eecd & E1000_EECD_TYPE) {
  417. eeprom->type = e1000_eeprom_spi;
  418. eeprom->opcode_bits = 8;
  419. eeprom->delay_usec = 1;
  420. if (eecd & E1000_EECD_ADDR_BITS) {
  421. eeprom->page_size = 32;
  422. eeprom->address_bits = 16;
  423. } else {
  424. eeprom->page_size = 8;
  425. eeprom->address_bits = 8;
  426. }
  427. } else {
  428. eeprom->type = e1000_eeprom_microwire;
  429. eeprom->opcode_bits = 3;
  430. eeprom->delay_usec = 50;
  431. if (eecd & E1000_EECD_ADDR_BITS) {
  432. eeprom->word_size = 256;
  433. eeprom->address_bits = 8;
  434. } else {
  435. eeprom->word_size = 64;
  436. eeprom->address_bits = 6;
  437. }
  438. }
  439. eeprom->use_eerd = false;
  440. eeprom->use_eewr = false;
  441. break;
  442. case e1000_82571:
  443. case e1000_82572:
  444. eeprom->type = e1000_eeprom_spi;
  445. eeprom->opcode_bits = 8;
  446. eeprom->delay_usec = 1;
  447. if (eecd & E1000_EECD_ADDR_BITS) {
  448. eeprom->page_size = 32;
  449. eeprom->address_bits = 16;
  450. } else {
  451. eeprom->page_size = 8;
  452. eeprom->address_bits = 8;
  453. }
  454. eeprom->use_eerd = false;
  455. eeprom->use_eewr = false;
  456. break;
  457. case e1000_82573:
  458. case e1000_82574:
  459. eeprom->type = e1000_eeprom_spi;
  460. eeprom->opcode_bits = 8;
  461. eeprom->delay_usec = 1;
  462. if (eecd & E1000_EECD_ADDR_BITS) {
  463. eeprom->page_size = 32;
  464. eeprom->address_bits = 16;
  465. } else {
  466. eeprom->page_size = 8;
  467. eeprom->address_bits = 8;
  468. }
  469. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  470. eeprom->use_eerd = true;
  471. eeprom->use_eewr = true;
  472. eeprom->type = e1000_eeprom_flash;
  473. eeprom->word_size = 2048;
  474. /* Ensure that the Autonomous FLASH update bit is cleared due to
  475. * Flash update issue on parts which use a FLASH for NVM. */
  476. eecd &= ~E1000_EECD_AUPDEN;
  477. E1000_WRITE_REG(hw, EECD, eecd);
  478. }
  479. break;
  480. case e1000_80003es2lan:
  481. eeprom->type = e1000_eeprom_spi;
  482. eeprom->opcode_bits = 8;
  483. eeprom->delay_usec = 1;
  484. if (eecd & E1000_EECD_ADDR_BITS) {
  485. eeprom->page_size = 32;
  486. eeprom->address_bits = 16;
  487. } else {
  488. eeprom->page_size = 8;
  489. eeprom->address_bits = 8;
  490. }
  491. eeprom->use_eerd = true;
  492. eeprom->use_eewr = false;
  493. break;
  494. case e1000_igb:
  495. /* i210 has 4k of iNVM mapped as EEPROM */
  496. eeprom->type = e1000_eeprom_invm;
  497. eeprom->opcode_bits = 8;
  498. eeprom->delay_usec = 1;
  499. eeprom->page_size = 32;
  500. eeprom->address_bits = 16;
  501. eeprom->use_eerd = true;
  502. eeprom->use_eewr = false;
  503. break;
  504. default:
  505. break;
  506. }
  507. if (eeprom->type == e1000_eeprom_spi ||
  508. eeprom->type == e1000_eeprom_invm) {
  509. /* eeprom_size will be an enum [0..8] that maps
  510. * to eeprom sizes 128B to
  511. * 32KB (incremented by powers of 2).
  512. */
  513. if (hw->mac_type <= e1000_82547_rev_2) {
  514. /* Set to default value for initial eeprom read. */
  515. eeprom->word_size = 64;
  516. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  517. &eeprom_size);
  518. if (ret_val)
  519. return ret_val;
  520. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  521. >> EEPROM_SIZE_SHIFT;
  522. /* 256B eeprom size was not supported in earlier
  523. * hardware, so we bump eeprom_size up one to
  524. * ensure that "1" (which maps to 256B) is never
  525. * the result used in the shifting logic below. */
  526. if (eeprom_size)
  527. eeprom_size++;
  528. } else {
  529. eeprom_size = (uint16_t)((eecd &
  530. E1000_EECD_SIZE_EX_MASK) >>
  531. E1000_EECD_SIZE_EX_SHIFT);
  532. }
  533. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  534. }
  535. return ret_val;
  536. }
  537. /******************************************************************************
  538. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  539. *
  540. * hw - Struct containing variables accessed by shared code
  541. *****************************************************************************/
  542. static int32_t
  543. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  544. {
  545. uint32_t attempts = 100000;
  546. uint32_t i, reg = 0;
  547. int32_t done = E1000_ERR_EEPROM;
  548. for (i = 0; i < attempts; i++) {
  549. if (eerd == E1000_EEPROM_POLL_READ) {
  550. if (hw->mac_type == e1000_igb)
  551. reg = E1000_READ_REG(hw, I210_EERD);
  552. else
  553. reg = E1000_READ_REG(hw, EERD);
  554. } else {
  555. if (hw->mac_type == e1000_igb)
  556. reg = E1000_READ_REG(hw, I210_EEWR);
  557. else
  558. reg = E1000_READ_REG(hw, EEWR);
  559. }
  560. if (reg & E1000_EEPROM_RW_REG_DONE) {
  561. done = E1000_SUCCESS;
  562. break;
  563. }
  564. udelay(5);
  565. }
  566. return done;
  567. }
  568. /******************************************************************************
  569. * Reads a 16 bit word from the EEPROM using the EERD register.
  570. *
  571. * hw - Struct containing variables accessed by shared code
  572. * offset - offset of word in the EEPROM to read
  573. * data - word read from the EEPROM
  574. * words - number of words to read
  575. *****************************************************************************/
  576. static int32_t
  577. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  578. uint16_t offset,
  579. uint16_t words,
  580. uint16_t *data)
  581. {
  582. uint32_t i, eerd = 0;
  583. int32_t error = 0;
  584. for (i = 0; i < words; i++) {
  585. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  586. E1000_EEPROM_RW_REG_START;
  587. if (hw->mac_type == e1000_igb)
  588. E1000_WRITE_REG(hw, I210_EERD, eerd);
  589. else
  590. E1000_WRITE_REG(hw, EERD, eerd);
  591. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  592. if (error)
  593. break;
  594. if (hw->mac_type == e1000_igb) {
  595. data[i] = (E1000_READ_REG(hw, I210_EERD) >>
  596. E1000_EEPROM_RW_REG_DATA);
  597. } else {
  598. data[i] = (E1000_READ_REG(hw, EERD) >>
  599. E1000_EEPROM_RW_REG_DATA);
  600. }
  601. }
  602. return error;
  603. }
  604. void e1000_release_eeprom(struct e1000_hw *hw)
  605. {
  606. uint32_t eecd;
  607. DEBUGFUNC();
  608. eecd = E1000_READ_REG(hw, EECD);
  609. if (hw->eeprom.type == e1000_eeprom_spi) {
  610. eecd |= E1000_EECD_CS; /* Pull CS high */
  611. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  612. E1000_WRITE_REG(hw, EECD, eecd);
  613. udelay(hw->eeprom.delay_usec);
  614. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  615. /* cleanup eeprom */
  616. /* CS on Microwire is active-high */
  617. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  618. E1000_WRITE_REG(hw, EECD, eecd);
  619. /* Rising edge of clock */
  620. eecd |= E1000_EECD_SK;
  621. E1000_WRITE_REG(hw, EECD, eecd);
  622. E1000_WRITE_FLUSH(hw);
  623. udelay(hw->eeprom.delay_usec);
  624. /* Falling edge of clock */
  625. eecd &= ~E1000_EECD_SK;
  626. E1000_WRITE_REG(hw, EECD, eecd);
  627. E1000_WRITE_FLUSH(hw);
  628. udelay(hw->eeprom.delay_usec);
  629. }
  630. /* Stop requesting EEPROM access */
  631. if (hw->mac_type > e1000_82544) {
  632. eecd &= ~E1000_EECD_REQ;
  633. E1000_WRITE_REG(hw, EECD, eecd);
  634. }
  635. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  636. }
  637. /******************************************************************************
  638. * Reads a 16 bit word from the EEPROM.
  639. *
  640. * hw - Struct containing variables accessed by shared code
  641. *****************************************************************************/
  642. static int32_t
  643. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  644. {
  645. uint16_t retry_count = 0;
  646. uint8_t spi_stat_reg;
  647. DEBUGFUNC();
  648. /* Read "Status Register" repeatedly until the LSB is cleared. The
  649. * EEPROM will signal that the command has been completed by clearing
  650. * bit 0 of the internal status register. If it's not cleared within
  651. * 5 milliseconds, then error out.
  652. */
  653. retry_count = 0;
  654. do {
  655. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  656. hw->eeprom.opcode_bits);
  657. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  658. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  659. break;
  660. udelay(5);
  661. retry_count += 5;
  662. e1000_standby_eeprom(hw);
  663. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  664. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  665. * only 0-5mSec on 5V devices)
  666. */
  667. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  668. DEBUGOUT("SPI EEPROM Status error\n");
  669. return -E1000_ERR_EEPROM;
  670. }
  671. return E1000_SUCCESS;
  672. }
  673. /******************************************************************************
  674. * Reads a 16 bit word from the EEPROM.
  675. *
  676. * hw - Struct containing variables accessed by shared code
  677. * offset - offset of word in the EEPROM to read
  678. * data - word read from the EEPROM
  679. *****************************************************************************/
  680. static int32_t
  681. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  682. uint16_t words, uint16_t *data)
  683. {
  684. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  685. uint32_t i = 0;
  686. DEBUGFUNC();
  687. /* If eeprom is not yet detected, do so now */
  688. if (eeprom->word_size == 0)
  689. e1000_init_eeprom_params(hw);
  690. /* A check for invalid values: offset too large, too many words,
  691. * and not enough words.
  692. */
  693. if ((offset >= eeprom->word_size) ||
  694. (words > eeprom->word_size - offset) ||
  695. (words == 0)) {
  696. DEBUGOUT("\"words\" parameter out of bounds."
  697. "Words = %d, size = %d\n", offset, eeprom->word_size);
  698. return -E1000_ERR_EEPROM;
  699. }
  700. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  701. * directly. In this case, we need to acquire the EEPROM so that
  702. * FW or other port software does not interrupt.
  703. */
  704. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  705. hw->eeprom.use_eerd == false) {
  706. /* Prepare the EEPROM for bit-bang reading */
  707. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  708. return -E1000_ERR_EEPROM;
  709. }
  710. /* Eerd register EEPROM access requires no eeprom aquire/release */
  711. if (eeprom->use_eerd == true)
  712. return e1000_read_eeprom_eerd(hw, offset, words, data);
  713. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  714. * acquired the EEPROM at this point, so any returns should relase it */
  715. if (eeprom->type == e1000_eeprom_spi) {
  716. uint16_t word_in;
  717. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  718. if (e1000_spi_eeprom_ready(hw)) {
  719. e1000_release_eeprom(hw);
  720. return -E1000_ERR_EEPROM;
  721. }
  722. e1000_standby_eeprom(hw);
  723. /* Some SPI eeproms use the 8th address bit embedded in
  724. * the opcode */
  725. if ((eeprom->address_bits == 8) && (offset >= 128))
  726. read_opcode |= EEPROM_A8_OPCODE_SPI;
  727. /* Send the READ command (opcode + addr) */
  728. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  729. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  730. eeprom->address_bits);
  731. /* Read the data. The address of the eeprom internally
  732. * increments with each byte (spi) being read, saving on the
  733. * overhead of eeprom setup and tear-down. The address
  734. * counter will roll over if reading beyond the size of
  735. * the eeprom, thus allowing the entire memory to be read
  736. * starting from any offset. */
  737. for (i = 0; i < words; i++) {
  738. word_in = e1000_shift_in_ee_bits(hw, 16);
  739. data[i] = (word_in >> 8) | (word_in << 8);
  740. }
  741. } else if (eeprom->type == e1000_eeprom_microwire) {
  742. for (i = 0; i < words; i++) {
  743. /* Send the READ command (opcode + addr) */
  744. e1000_shift_out_ee_bits(hw,
  745. EEPROM_READ_OPCODE_MICROWIRE,
  746. eeprom->opcode_bits);
  747. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  748. eeprom->address_bits);
  749. /* Read the data. For microwire, each word requires
  750. * the overhead of eeprom setup and tear-down. */
  751. data[i] = e1000_shift_in_ee_bits(hw, 16);
  752. e1000_standby_eeprom(hw);
  753. }
  754. }
  755. /* End this read operation */
  756. e1000_release_eeprom(hw);
  757. return E1000_SUCCESS;
  758. }
  759. /******************************************************************************
  760. * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
  761. * @hw: pointer to the HW structure
  762. * @offset: offset within the Shadow Ram to be written to
  763. * @words: number of words to write
  764. * @data: 16 bit word(s) to be written to the Shadow Ram
  765. *
  766. * Writes data to Shadow Ram at offset using EEWR register.
  767. *
  768. * If e1000_update_eeprom_checksum_i210 is not called after this function, the
  769. * Shadow Ram will most likely contain an invalid checksum.
  770. *****************************************************************************/
  771. static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
  772. uint16_t words, uint16_t *data)
  773. {
  774. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  775. uint32_t i, k, eewr = 0;
  776. uint32_t attempts = 100000;
  777. int32_t ret_val = 0;
  778. /* A check for invalid values: offset too large, too many words,
  779. * too many words for the offset, and not enough words.
  780. */
  781. if ((offset >= eeprom->word_size) ||
  782. (words > (eeprom->word_size - offset)) || (words == 0)) {
  783. DEBUGOUT("nvm parameter(s) out of bounds\n");
  784. ret_val = -E1000_ERR_EEPROM;
  785. goto out;
  786. }
  787. for (i = 0; i < words; i++) {
  788. eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
  789. | (data[i] << E1000_EEPROM_RW_REG_DATA) |
  790. E1000_EEPROM_RW_REG_START;
  791. E1000_WRITE_REG(hw, I210_EEWR, eewr);
  792. for (k = 0; k < attempts; k++) {
  793. if (E1000_EEPROM_RW_REG_DONE &
  794. E1000_READ_REG(hw, I210_EEWR)) {
  795. ret_val = 0;
  796. break;
  797. }
  798. udelay(5);
  799. }
  800. if (ret_val) {
  801. DEBUGOUT("Shadow RAM write EEWR timed out\n");
  802. break;
  803. }
  804. }
  805. out:
  806. return ret_val;
  807. }
  808. /******************************************************************************
  809. * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
  810. * @hw: pointer to the HW structure
  811. *
  812. *****************************************************************************/
  813. static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
  814. {
  815. int32_t ret_val = -E1000_ERR_EEPROM;
  816. uint32_t i, reg;
  817. for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
  818. reg = E1000_READ_REG(hw, EECD);
  819. if (reg & E1000_EECD_FLUDONE_I210) {
  820. ret_val = 0;
  821. break;
  822. }
  823. udelay(5);
  824. }
  825. return ret_val;
  826. }
  827. /******************************************************************************
  828. * e1000_update_flash_i210 - Commit EEPROM to the flash
  829. * @hw: pointer to the HW structure
  830. *
  831. *****************************************************************************/
  832. static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
  833. {
  834. int32_t ret_val = 0;
  835. uint32_t flup;
  836. ret_val = e1000_pool_flash_update_done_i210(hw);
  837. if (ret_val == -E1000_ERR_EEPROM) {
  838. DEBUGOUT("Flash update time out\n");
  839. goto out;
  840. }
  841. flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
  842. E1000_WRITE_REG(hw, EECD, flup);
  843. ret_val = e1000_pool_flash_update_done_i210(hw);
  844. if (ret_val)
  845. DEBUGOUT("Flash update time out\n");
  846. else
  847. DEBUGOUT("Flash update complete\n");
  848. out:
  849. return ret_val;
  850. }
  851. /******************************************************************************
  852. * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
  853. * @hw: pointer to the HW structure
  854. *
  855. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  856. * up to the checksum. Then calculates the EEPROM checksum and writes the
  857. * value to the EEPROM. Next commit EEPROM data onto the Flash.
  858. *****************************************************************************/
  859. static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
  860. {
  861. int32_t ret_val = 0;
  862. uint16_t checksum = 0;
  863. uint16_t i, nvm_data;
  864. /* Read the first word from the EEPROM. If this times out or fails, do
  865. * not continue or we could be in for a very long wait while every
  866. * EEPROM read fails
  867. */
  868. ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
  869. if (ret_val) {
  870. DEBUGOUT("EEPROM read failed\n");
  871. goto out;
  872. }
  873. if (!(e1000_get_hw_eeprom_semaphore(hw))) {
  874. /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
  875. * because we do not want to take the synchronization
  876. * semaphores twice here.
  877. */
  878. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  879. ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
  880. if (ret_val) {
  881. e1000_put_hw_eeprom_semaphore(hw);
  882. DEBUGOUT("EEPROM Read Error while updating checksum.\n");
  883. goto out;
  884. }
  885. checksum += nvm_data;
  886. }
  887. checksum = (uint16_t)EEPROM_SUM - checksum;
  888. ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
  889. &checksum);
  890. if (ret_val) {
  891. e1000_put_hw_eeprom_semaphore(hw);
  892. DEBUGOUT("EEPROM Write Error while updating checksum.\n");
  893. goto out;
  894. }
  895. e1000_put_hw_eeprom_semaphore(hw);
  896. ret_val = e1000_update_flash_i210(hw);
  897. } else {
  898. ret_val = -E1000_ERR_SWFW_SYNC;
  899. }
  900. out:
  901. return ret_val;
  902. }
  903. /******************************************************************************
  904. * Verifies that the EEPROM has a valid checksum
  905. *
  906. * hw - Struct containing variables accessed by shared code
  907. *
  908. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  909. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  910. * valid.
  911. *****************************************************************************/
  912. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  913. {
  914. uint16_t i, checksum, checksum_reg, *buf;
  915. DEBUGFUNC();
  916. /* Allocate a temporary buffer */
  917. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  918. if (!buf) {
  919. E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
  920. return -E1000_ERR_EEPROM;
  921. }
  922. /* Read the EEPROM */
  923. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  924. E1000_ERR(hw, "Unable to read EEPROM!\n");
  925. return -E1000_ERR_EEPROM;
  926. }
  927. /* Compute the checksum */
  928. checksum = 0;
  929. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  930. checksum += buf[i];
  931. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  932. checksum_reg = buf[i];
  933. /* Verify it! */
  934. if (checksum == checksum_reg)
  935. return 0;
  936. /* Hrm, verification failed, print an error */
  937. E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
  938. E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
  939. checksum_reg, checksum);
  940. return -E1000_ERR_EEPROM;
  941. }
  942. #endif /* CONFIG_E1000_NO_NVM */
  943. /*****************************************************************************
  944. * Set PHY to class A mode
  945. * Assumes the following operations will follow to enable the new class mode.
  946. * 1. Do a PHY soft reset
  947. * 2. Restart auto-negotiation or force link.
  948. *
  949. * hw - Struct containing variables accessed by shared code
  950. ****************************************************************************/
  951. static int32_t
  952. e1000_set_phy_mode(struct e1000_hw *hw)
  953. {
  954. #ifndef CONFIG_E1000_NO_NVM
  955. int32_t ret_val;
  956. uint16_t eeprom_data;
  957. DEBUGFUNC();
  958. if ((hw->mac_type == e1000_82545_rev_3) &&
  959. (hw->media_type == e1000_media_type_copper)) {
  960. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  961. 1, &eeprom_data);
  962. if (ret_val)
  963. return ret_val;
  964. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  965. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  966. ret_val = e1000_write_phy_reg(hw,
  967. M88E1000_PHY_PAGE_SELECT, 0x000B);
  968. if (ret_val)
  969. return ret_val;
  970. ret_val = e1000_write_phy_reg(hw,
  971. M88E1000_PHY_GEN_CONTROL, 0x8104);
  972. if (ret_val)
  973. return ret_val;
  974. hw->phy_reset_disable = false;
  975. }
  976. }
  977. #endif
  978. return E1000_SUCCESS;
  979. }
  980. #ifndef CONFIG_E1000_NO_NVM
  981. /***************************************************************************
  982. *
  983. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  984. *
  985. * hw: Struct containing variables accessed by shared code
  986. *
  987. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  988. * E1000_SUCCESS at any other case.
  989. *
  990. ***************************************************************************/
  991. static int32_t
  992. e1000_get_software_semaphore(struct e1000_hw *hw)
  993. {
  994. int32_t timeout = hw->eeprom.word_size + 1;
  995. uint32_t swsm;
  996. DEBUGFUNC();
  997. if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
  998. return E1000_SUCCESS;
  999. while (timeout) {
  1000. swsm = E1000_READ_REG(hw, SWSM);
  1001. /* If SMBI bit cleared, it is now set and we hold
  1002. * the semaphore */
  1003. if (!(swsm & E1000_SWSM_SMBI))
  1004. break;
  1005. mdelay(1);
  1006. timeout--;
  1007. }
  1008. if (!timeout) {
  1009. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  1010. return -E1000_ERR_RESET;
  1011. }
  1012. return E1000_SUCCESS;
  1013. }
  1014. #endif
  1015. /***************************************************************************
  1016. * This function clears HW semaphore bits.
  1017. *
  1018. * hw: Struct containing variables accessed by shared code
  1019. *
  1020. * returns: - None.
  1021. *
  1022. ***************************************************************************/
  1023. static void
  1024. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  1025. {
  1026. #ifndef CONFIG_E1000_NO_NVM
  1027. uint32_t swsm;
  1028. DEBUGFUNC();
  1029. if (!hw->eeprom_semaphore_present)
  1030. return;
  1031. swsm = E1000_READ_REG(hw, SWSM);
  1032. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1033. /* Release both semaphores. */
  1034. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  1035. } else
  1036. swsm &= ~(E1000_SWSM_SWESMBI);
  1037. E1000_WRITE_REG(hw, SWSM, swsm);
  1038. #endif
  1039. }
  1040. /***************************************************************************
  1041. *
  1042. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  1043. * adapter or Eeprom access.
  1044. *
  1045. * hw: Struct containing variables accessed by shared code
  1046. *
  1047. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  1048. * E1000_SUCCESS at any other case.
  1049. *
  1050. ***************************************************************************/
  1051. static int32_t
  1052. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  1053. {
  1054. #ifndef CONFIG_E1000_NO_NVM
  1055. int32_t timeout;
  1056. uint32_t swsm;
  1057. DEBUGFUNC();
  1058. if (!hw->eeprom_semaphore_present)
  1059. return E1000_SUCCESS;
  1060. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1061. /* Get the SW semaphore. */
  1062. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  1063. return -E1000_ERR_EEPROM;
  1064. }
  1065. /* Get the FW semaphore. */
  1066. timeout = hw->eeprom.word_size + 1;
  1067. while (timeout) {
  1068. swsm = E1000_READ_REG(hw, SWSM);
  1069. swsm |= E1000_SWSM_SWESMBI;
  1070. E1000_WRITE_REG(hw, SWSM, swsm);
  1071. /* if we managed to set the bit we got the semaphore. */
  1072. swsm = E1000_READ_REG(hw, SWSM);
  1073. if (swsm & E1000_SWSM_SWESMBI)
  1074. break;
  1075. udelay(50);
  1076. timeout--;
  1077. }
  1078. if (!timeout) {
  1079. /* Release semaphores */
  1080. e1000_put_hw_eeprom_semaphore(hw);
  1081. DEBUGOUT("Driver can't access the Eeprom - "
  1082. "SWESMBI bit is set.\n");
  1083. return -E1000_ERR_EEPROM;
  1084. }
  1085. #endif
  1086. return E1000_SUCCESS;
  1087. }
  1088. /* Take ownership of the PHY */
  1089. static int32_t
  1090. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  1091. {
  1092. uint32_t swfw_sync = 0;
  1093. uint32_t swmask = mask;
  1094. uint32_t fwmask = mask << 16;
  1095. int32_t timeout = 200;
  1096. DEBUGFUNC();
  1097. while (timeout) {
  1098. if (e1000_get_hw_eeprom_semaphore(hw))
  1099. return -E1000_ERR_SWFW_SYNC;
  1100. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1101. if (!(swfw_sync & (fwmask | swmask)))
  1102. break;
  1103. /* firmware currently using resource (fwmask) */
  1104. /* or other software thread currently using resource (swmask) */
  1105. e1000_put_hw_eeprom_semaphore(hw);
  1106. mdelay(5);
  1107. timeout--;
  1108. }
  1109. if (!timeout) {
  1110. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  1111. return -E1000_ERR_SWFW_SYNC;
  1112. }
  1113. swfw_sync |= swmask;
  1114. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1115. e1000_put_hw_eeprom_semaphore(hw);
  1116. return E1000_SUCCESS;
  1117. }
  1118. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  1119. {
  1120. uint32_t swfw_sync = 0;
  1121. DEBUGFUNC();
  1122. while (e1000_get_hw_eeprom_semaphore(hw))
  1123. ; /* Empty */
  1124. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1125. swfw_sync &= ~mask;
  1126. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1127. e1000_put_hw_eeprom_semaphore(hw);
  1128. }
  1129. static bool e1000_is_second_port(struct e1000_hw *hw)
  1130. {
  1131. switch (hw->mac_type) {
  1132. case e1000_80003es2lan:
  1133. case e1000_82546:
  1134. case e1000_82571:
  1135. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  1136. return true;
  1137. /* Fallthrough */
  1138. default:
  1139. return false;
  1140. }
  1141. }
  1142. #ifndef CONFIG_E1000_NO_NVM
  1143. /******************************************************************************
  1144. * Reads the adapter's MAC address from the EEPROM
  1145. *
  1146. * hw - Struct containing variables accessed by shared code
  1147. * enetaddr - buffering where the MAC address will be stored
  1148. *****************************************************************************/
  1149. static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
  1150. unsigned char enetaddr[6])
  1151. {
  1152. uint16_t offset;
  1153. uint16_t eeprom_data;
  1154. int i;
  1155. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1156. offset = i >> 1;
  1157. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  1158. DEBUGOUT("EEPROM Read Error\n");
  1159. return -E1000_ERR_EEPROM;
  1160. }
  1161. enetaddr[i] = eeprom_data & 0xff;
  1162. enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  1163. }
  1164. return 0;
  1165. }
  1166. /******************************************************************************
  1167. * Reads the adapter's MAC address from the RAL/RAH registers
  1168. *
  1169. * hw - Struct containing variables accessed by shared code
  1170. * enetaddr - buffering where the MAC address will be stored
  1171. *****************************************************************************/
  1172. static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
  1173. unsigned char enetaddr[6])
  1174. {
  1175. uint16_t offset, tmp;
  1176. uint32_t reg_data = 0;
  1177. int i;
  1178. if (hw->mac_type != e1000_igb)
  1179. return -E1000_ERR_MAC_TYPE;
  1180. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1181. offset = i >> 1;
  1182. if (offset == 0)
  1183. reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
  1184. else if (offset == 1)
  1185. reg_data >>= 16;
  1186. else if (offset == 2)
  1187. reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
  1188. tmp = reg_data & 0xffff;
  1189. enetaddr[i] = tmp & 0xff;
  1190. enetaddr[i + 1] = (tmp >> 8) & 0xff;
  1191. }
  1192. return 0;
  1193. }
  1194. /******************************************************************************
  1195. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  1196. * second function of dual function devices
  1197. *
  1198. * hw - Struct containing variables accessed by shared code
  1199. * enetaddr - buffering where the MAC address will be stored
  1200. *****************************************************************************/
  1201. static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
  1202. {
  1203. int ret_val;
  1204. if (hw->mac_type == e1000_igb) {
  1205. /* i210 preloads MAC address into RAL/RAH registers */
  1206. ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
  1207. } else {
  1208. ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
  1209. }
  1210. if (ret_val)
  1211. return ret_val;
  1212. /* Invert the last bit if this is the second device */
  1213. if (e1000_is_second_port(hw))
  1214. enetaddr[5] ^= 1;
  1215. return 0;
  1216. }
  1217. #endif
  1218. /******************************************************************************
  1219. * Initializes receive address filters.
  1220. *
  1221. * hw - Struct containing variables accessed by shared code
  1222. *
  1223. * Places the MAC address in receive address register 0 and clears the rest
  1224. * of the receive addresss registers. Clears the multicast table. Assumes
  1225. * the receiver is in reset when the routine is called.
  1226. *****************************************************************************/
  1227. static void
  1228. e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
  1229. {
  1230. uint32_t i;
  1231. uint32_t addr_low;
  1232. uint32_t addr_high;
  1233. DEBUGFUNC();
  1234. /* Setup the receive address. */
  1235. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1236. addr_low = (enetaddr[0] |
  1237. (enetaddr[1] << 8) |
  1238. (enetaddr[2] << 16) | (enetaddr[3] << 24));
  1239. addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
  1240. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1241. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1242. /* Zero out the other 15 receive addresses. */
  1243. DEBUGOUT("Clearing RAR[1-15]\n");
  1244. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1245. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1246. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1247. }
  1248. }
  1249. /******************************************************************************
  1250. * Clears the VLAN filer table
  1251. *
  1252. * hw - Struct containing variables accessed by shared code
  1253. *****************************************************************************/
  1254. static void
  1255. e1000_clear_vfta(struct e1000_hw *hw)
  1256. {
  1257. uint32_t offset;
  1258. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1259. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1260. }
  1261. /******************************************************************************
  1262. * Set the mac type member in the hw struct.
  1263. *
  1264. * hw - Struct containing variables accessed by shared code
  1265. *****************************************************************************/
  1266. int32_t
  1267. e1000_set_mac_type(struct e1000_hw *hw)
  1268. {
  1269. DEBUGFUNC();
  1270. switch (hw->device_id) {
  1271. case E1000_DEV_ID_82542:
  1272. switch (hw->revision_id) {
  1273. case E1000_82542_2_0_REV_ID:
  1274. hw->mac_type = e1000_82542_rev2_0;
  1275. break;
  1276. case E1000_82542_2_1_REV_ID:
  1277. hw->mac_type = e1000_82542_rev2_1;
  1278. break;
  1279. default:
  1280. /* Invalid 82542 revision ID */
  1281. return -E1000_ERR_MAC_TYPE;
  1282. }
  1283. break;
  1284. case E1000_DEV_ID_82543GC_FIBER:
  1285. case E1000_DEV_ID_82543GC_COPPER:
  1286. hw->mac_type = e1000_82543;
  1287. break;
  1288. case E1000_DEV_ID_82544EI_COPPER:
  1289. case E1000_DEV_ID_82544EI_FIBER:
  1290. case E1000_DEV_ID_82544GC_COPPER:
  1291. case E1000_DEV_ID_82544GC_LOM:
  1292. hw->mac_type = e1000_82544;
  1293. break;
  1294. case E1000_DEV_ID_82540EM:
  1295. case E1000_DEV_ID_82540EM_LOM:
  1296. case E1000_DEV_ID_82540EP:
  1297. case E1000_DEV_ID_82540EP_LOM:
  1298. case E1000_DEV_ID_82540EP_LP:
  1299. hw->mac_type = e1000_82540;
  1300. break;
  1301. case E1000_DEV_ID_82545EM_COPPER:
  1302. case E1000_DEV_ID_82545EM_FIBER:
  1303. hw->mac_type = e1000_82545;
  1304. break;
  1305. case E1000_DEV_ID_82545GM_COPPER:
  1306. case E1000_DEV_ID_82545GM_FIBER:
  1307. case E1000_DEV_ID_82545GM_SERDES:
  1308. hw->mac_type = e1000_82545_rev_3;
  1309. break;
  1310. case E1000_DEV_ID_82546EB_COPPER:
  1311. case E1000_DEV_ID_82546EB_FIBER:
  1312. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1313. hw->mac_type = e1000_82546;
  1314. break;
  1315. case E1000_DEV_ID_82546GB_COPPER:
  1316. case E1000_DEV_ID_82546GB_FIBER:
  1317. case E1000_DEV_ID_82546GB_SERDES:
  1318. case E1000_DEV_ID_82546GB_PCIE:
  1319. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1320. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1321. hw->mac_type = e1000_82546_rev_3;
  1322. break;
  1323. case E1000_DEV_ID_82541EI:
  1324. case E1000_DEV_ID_82541EI_MOBILE:
  1325. case E1000_DEV_ID_82541ER_LOM:
  1326. hw->mac_type = e1000_82541;
  1327. break;
  1328. case E1000_DEV_ID_82541ER:
  1329. case E1000_DEV_ID_82541GI:
  1330. case E1000_DEV_ID_82541GI_LF:
  1331. case E1000_DEV_ID_82541GI_MOBILE:
  1332. hw->mac_type = e1000_82541_rev_2;
  1333. break;
  1334. case E1000_DEV_ID_82547EI:
  1335. case E1000_DEV_ID_82547EI_MOBILE:
  1336. hw->mac_type = e1000_82547;
  1337. break;
  1338. case E1000_DEV_ID_82547GI:
  1339. hw->mac_type = e1000_82547_rev_2;
  1340. break;
  1341. case E1000_DEV_ID_82571EB_COPPER:
  1342. case E1000_DEV_ID_82571EB_FIBER:
  1343. case E1000_DEV_ID_82571EB_SERDES:
  1344. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1345. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1346. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1347. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1348. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1349. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1350. hw->mac_type = e1000_82571;
  1351. break;
  1352. case E1000_DEV_ID_82572EI_COPPER:
  1353. case E1000_DEV_ID_82572EI_FIBER:
  1354. case E1000_DEV_ID_82572EI_SERDES:
  1355. case E1000_DEV_ID_82572EI:
  1356. hw->mac_type = e1000_82572;
  1357. break;
  1358. case E1000_DEV_ID_82573E:
  1359. case E1000_DEV_ID_82573E_IAMT:
  1360. case E1000_DEV_ID_82573L:
  1361. hw->mac_type = e1000_82573;
  1362. break;
  1363. case E1000_DEV_ID_82574L:
  1364. hw->mac_type = e1000_82574;
  1365. break;
  1366. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1367. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1368. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1369. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1370. hw->mac_type = e1000_80003es2lan;
  1371. break;
  1372. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1373. case E1000_DEV_ID_ICH8_IGP_AMT:
  1374. case E1000_DEV_ID_ICH8_IGP_C:
  1375. case E1000_DEV_ID_ICH8_IFE:
  1376. case E1000_DEV_ID_ICH8_IFE_GT:
  1377. case E1000_DEV_ID_ICH8_IFE_G:
  1378. case E1000_DEV_ID_ICH8_IGP_M:
  1379. hw->mac_type = e1000_ich8lan;
  1380. break;
  1381. case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
  1382. case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
  1383. case PCI_DEVICE_ID_INTEL_I210_COPPER:
  1384. case PCI_DEVICE_ID_INTEL_I211_COPPER:
  1385. case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
  1386. case PCI_DEVICE_ID_INTEL_I210_SERDES:
  1387. case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
  1388. case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
  1389. hw->mac_type = e1000_igb;
  1390. break;
  1391. default:
  1392. /* Should never have loaded on this device */
  1393. return -E1000_ERR_MAC_TYPE;
  1394. }
  1395. return E1000_SUCCESS;
  1396. }
  1397. /******************************************************************************
  1398. * Reset the transmit and receive units; mask and clear all interrupts.
  1399. *
  1400. * hw - Struct containing variables accessed by shared code
  1401. *****************************************************************************/
  1402. void
  1403. e1000_reset_hw(struct e1000_hw *hw)
  1404. {
  1405. uint32_t ctrl;
  1406. uint32_t ctrl_ext;
  1407. uint32_t manc;
  1408. uint32_t pba = 0;
  1409. uint32_t reg;
  1410. DEBUGFUNC();
  1411. /* get the correct pba value for both PCI and PCIe*/
  1412. if (hw->mac_type < e1000_82571)
  1413. pba = E1000_DEFAULT_PCI_PBA;
  1414. else
  1415. pba = E1000_DEFAULT_PCIE_PBA;
  1416. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1417. if (hw->mac_type == e1000_82542_rev2_0) {
  1418. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1419. #ifdef CONFIG_DM_ETH
  1420. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1421. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1422. #else
  1423. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1424. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1425. #endif
  1426. }
  1427. /* Clear interrupt mask to stop board from generating interrupts */
  1428. DEBUGOUT("Masking off all interrupts\n");
  1429. if (hw->mac_type == e1000_igb)
  1430. E1000_WRITE_REG(hw, I210_IAM, 0);
  1431. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1432. /* Disable the Transmit and Receive units. Then delay to allow
  1433. * any pending transactions to complete before we hit the MAC with
  1434. * the global reset.
  1435. */
  1436. E1000_WRITE_REG(hw, RCTL, 0);
  1437. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1438. E1000_WRITE_FLUSH(hw);
  1439. if (hw->mac_type == e1000_igb) {
  1440. E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
  1441. E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
  1442. }
  1443. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1444. hw->tbi_compatibility_on = false;
  1445. /* Delay to allow any outstanding PCI transactions to complete before
  1446. * resetting the device
  1447. */
  1448. mdelay(10);
  1449. /* Issue a global reset to the MAC. This will reset the chip's
  1450. * transmit, receive, DMA, and link units. It will not effect
  1451. * the current PCI configuration. The global reset bit is self-
  1452. * clearing, and should clear within a microsecond.
  1453. */
  1454. DEBUGOUT("Issuing a global reset to MAC\n");
  1455. ctrl = E1000_READ_REG(hw, CTRL);
  1456. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1457. /* Force a reload from the EEPROM if necessary */
  1458. if (hw->mac_type == e1000_igb) {
  1459. mdelay(20);
  1460. reg = E1000_READ_REG(hw, STATUS);
  1461. if (reg & E1000_STATUS_PF_RST_DONE)
  1462. DEBUGOUT("PF OK\n");
  1463. reg = E1000_READ_REG(hw, I210_EECD);
  1464. if (reg & E1000_EECD_AUTO_RD)
  1465. DEBUGOUT("EEC OK\n");
  1466. } else if (hw->mac_type < e1000_82540) {
  1467. /* Wait for reset to complete */
  1468. udelay(10);
  1469. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1470. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1471. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1472. E1000_WRITE_FLUSH(hw);
  1473. /* Wait for EEPROM reload */
  1474. mdelay(2);
  1475. } else {
  1476. /* Wait for EEPROM reload (it happens automatically) */
  1477. mdelay(4);
  1478. /* Dissable HW ARPs on ASF enabled adapters */
  1479. manc = E1000_READ_REG(hw, MANC);
  1480. manc &= ~(E1000_MANC_ARP_EN);
  1481. E1000_WRITE_REG(hw, MANC, manc);
  1482. }
  1483. /* Clear interrupt mask to stop board from generating interrupts */
  1484. DEBUGOUT("Masking off all interrupts\n");
  1485. if (hw->mac_type == e1000_igb)
  1486. E1000_WRITE_REG(hw, I210_IAM, 0);
  1487. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1488. /* Clear any pending interrupt events. */
  1489. E1000_READ_REG(hw, ICR);
  1490. /* If MWI was previously enabled, reenable it. */
  1491. if (hw->mac_type == e1000_82542_rev2_0) {
  1492. #ifdef CONFIG_DM_ETH
  1493. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1494. #else
  1495. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1496. #endif
  1497. }
  1498. if (hw->mac_type != e1000_igb)
  1499. E1000_WRITE_REG(hw, PBA, pba);
  1500. }
  1501. /******************************************************************************
  1502. *
  1503. * Initialize a number of hardware-dependent bits
  1504. *
  1505. * hw: Struct containing variables accessed by shared code
  1506. *
  1507. * This function contains hardware limitation workarounds for PCI-E adapters
  1508. *
  1509. *****************************************************************************/
  1510. static void
  1511. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1512. {
  1513. if ((hw->mac_type >= e1000_82571) &&
  1514. (!hw->initialize_hw_bits_disable)) {
  1515. /* Settings common to all PCI-express silicon */
  1516. uint32_t reg_ctrl, reg_ctrl_ext;
  1517. uint32_t reg_tarc0, reg_tarc1;
  1518. uint32_t reg_tctl;
  1519. uint32_t reg_txdctl, reg_txdctl1;
  1520. /* link autonegotiation/sync workarounds */
  1521. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1522. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1523. /* Enable not-done TX descriptor counting */
  1524. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1525. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1526. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1527. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1528. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1529. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1530. switch (hw->mac_type) {
  1531. case e1000_igb: /* IGB is cool */
  1532. return;
  1533. case e1000_82571:
  1534. case e1000_82572:
  1535. /* Clear PHY TX compatible mode bits */
  1536. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1537. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1538. /* link autonegotiation/sync workarounds */
  1539. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1540. /* TX ring control fixes */
  1541. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1542. /* Multiple read bit is reversed polarity */
  1543. reg_tctl = E1000_READ_REG(hw, TCTL);
  1544. if (reg_tctl & E1000_TCTL_MULR)
  1545. reg_tarc1 &= ~(1 << 28);
  1546. else
  1547. reg_tarc1 |= (1 << 28);
  1548. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1549. break;
  1550. case e1000_82573:
  1551. case e1000_82574:
  1552. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1553. reg_ctrl_ext &= ~(1 << 23);
  1554. reg_ctrl_ext |= (1 << 22);
  1555. /* TX byte count fix */
  1556. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1557. reg_ctrl &= ~(1 << 29);
  1558. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1559. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1560. break;
  1561. case e1000_80003es2lan:
  1562. /* improve small packet performace for fiber/serdes */
  1563. if ((hw->media_type == e1000_media_type_fiber)
  1564. || (hw->media_type ==
  1565. e1000_media_type_internal_serdes)) {
  1566. reg_tarc0 &= ~(1 << 20);
  1567. }
  1568. /* Multiple read bit is reversed polarity */
  1569. reg_tctl = E1000_READ_REG(hw, TCTL);
  1570. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1571. if (reg_tctl & E1000_TCTL_MULR)
  1572. reg_tarc1 &= ~(1 << 28);
  1573. else
  1574. reg_tarc1 |= (1 << 28);
  1575. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1576. break;
  1577. case e1000_ich8lan:
  1578. /* Reduce concurrent DMA requests to 3 from 4 */
  1579. if ((hw->revision_id < 3) ||
  1580. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1581. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1582. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1583. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1584. reg_ctrl_ext |= (1 << 22);
  1585. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1586. /* workaround TX hang with TSO=on */
  1587. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1588. /* Multiple read bit is reversed polarity */
  1589. reg_tctl = E1000_READ_REG(hw, TCTL);
  1590. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1591. if (reg_tctl & E1000_TCTL_MULR)
  1592. reg_tarc1 &= ~(1 << 28);
  1593. else
  1594. reg_tarc1 |= (1 << 28);
  1595. /* workaround TX hang with TSO=on */
  1596. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1597. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1598. break;
  1599. default:
  1600. break;
  1601. }
  1602. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1603. }
  1604. }
  1605. /******************************************************************************
  1606. * Performs basic configuration of the adapter.
  1607. *
  1608. * hw - Struct containing variables accessed by shared code
  1609. *
  1610. * Assumes that the controller has previously been reset and is in a
  1611. * post-reset uninitialized state. Initializes the receive address registers,
  1612. * multicast table, and VLAN filter table. Calls routines to setup link
  1613. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1614. * the transmit and receive units disabled and uninitialized.
  1615. *****************************************************************************/
  1616. static int
  1617. e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
  1618. {
  1619. uint32_t ctrl;
  1620. uint32_t i;
  1621. int32_t ret_val;
  1622. uint16_t pcix_cmd_word;
  1623. uint16_t pcix_stat_hi_word;
  1624. uint16_t cmd_mmrbc;
  1625. uint16_t stat_mmrbc;
  1626. uint32_t mta_size;
  1627. uint32_t reg_data;
  1628. uint32_t ctrl_ext;
  1629. DEBUGFUNC();
  1630. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1631. if ((hw->mac_type == e1000_ich8lan) &&
  1632. ((hw->revision_id < 3) ||
  1633. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1634. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1635. reg_data = E1000_READ_REG(hw, STATUS);
  1636. reg_data &= ~0x80000000;
  1637. E1000_WRITE_REG(hw, STATUS, reg_data);
  1638. }
  1639. /* Do not need initialize Identification LED */
  1640. /* Set the media type and TBI compatibility */
  1641. e1000_set_media_type(hw);
  1642. /* Must be called after e1000_set_media_type
  1643. * because media_type is used */
  1644. e1000_initialize_hardware_bits(hw);
  1645. /* Disabling VLAN filtering. */
  1646. DEBUGOUT("Initializing the IEEE VLAN\n");
  1647. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1648. if (hw->mac_type != e1000_ich8lan) {
  1649. if (hw->mac_type < e1000_82545_rev_3)
  1650. E1000_WRITE_REG(hw, VET, 0);
  1651. e1000_clear_vfta(hw);
  1652. }
  1653. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1654. if (hw->mac_type == e1000_82542_rev2_0) {
  1655. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1656. #ifdef CONFIG_DM_ETH
  1657. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1658. hw->
  1659. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1660. #else
  1661. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1662. hw->
  1663. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1664. #endif
  1665. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1666. E1000_WRITE_FLUSH(hw);
  1667. mdelay(5);
  1668. }
  1669. /* Setup the receive address. This involves initializing all of the Receive
  1670. * Address Registers (RARs 0 - 15).
  1671. */
  1672. e1000_init_rx_addrs(hw, enetaddr);
  1673. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1674. if (hw->mac_type == e1000_82542_rev2_0) {
  1675. E1000_WRITE_REG(hw, RCTL, 0);
  1676. E1000_WRITE_FLUSH(hw);
  1677. mdelay(1);
  1678. #ifdef CONFIG_DM_ETH
  1679. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1680. #else
  1681. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1682. #endif
  1683. }
  1684. /* Zero out the Multicast HASH table */
  1685. DEBUGOUT("Zeroing the MTA\n");
  1686. mta_size = E1000_MC_TBL_SIZE;
  1687. if (hw->mac_type == e1000_ich8lan)
  1688. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1689. for (i = 0; i < mta_size; i++) {
  1690. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1691. /* use write flush to prevent Memory Write Block (MWB) from
  1692. * occuring when accessing our register space */
  1693. E1000_WRITE_FLUSH(hw);
  1694. }
  1695. switch (hw->mac_type) {
  1696. case e1000_82545_rev_3:
  1697. case e1000_82546_rev_3:
  1698. case e1000_igb:
  1699. break;
  1700. default:
  1701. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1702. if (hw->bus_type == e1000_bus_type_pcix) {
  1703. #ifdef CONFIG_DM_ETH
  1704. dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1705. &pcix_cmd_word);
  1706. dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1707. &pcix_stat_hi_word);
  1708. #else
  1709. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1710. &pcix_cmd_word);
  1711. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1712. &pcix_stat_hi_word);
  1713. #endif
  1714. cmd_mmrbc =
  1715. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1716. PCIX_COMMAND_MMRBC_SHIFT;
  1717. stat_mmrbc =
  1718. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1719. PCIX_STATUS_HI_MMRBC_SHIFT;
  1720. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1721. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1722. if (cmd_mmrbc > stat_mmrbc) {
  1723. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1724. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1725. #ifdef CONFIG_DM_ETH
  1726. dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1727. pcix_cmd_word);
  1728. #else
  1729. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1730. pcix_cmd_word);
  1731. #endif
  1732. }
  1733. }
  1734. break;
  1735. }
  1736. /* More time needed for PHY to initialize */
  1737. if (hw->mac_type == e1000_ich8lan)
  1738. mdelay(15);
  1739. if (hw->mac_type == e1000_igb)
  1740. mdelay(15);
  1741. /* Call a subroutine to configure the link and setup flow control. */
  1742. ret_val = e1000_setup_link(hw);
  1743. /* Set the transmit descriptor write-back policy */
  1744. if (hw->mac_type > e1000_82544) {
  1745. ctrl = E1000_READ_REG(hw, TXDCTL);
  1746. ctrl =
  1747. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1748. E1000_TXDCTL_FULL_TX_DESC_WB;
  1749. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1750. }
  1751. /* Set the receive descriptor write back policy */
  1752. if (hw->mac_type >= e1000_82571) {
  1753. ctrl = E1000_READ_REG(hw, RXDCTL);
  1754. ctrl =
  1755. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1756. E1000_RXDCTL_FULL_RX_DESC_WB;
  1757. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1758. }
  1759. switch (hw->mac_type) {
  1760. default:
  1761. break;
  1762. case e1000_80003es2lan:
  1763. /* Enable retransmit on late collisions */
  1764. reg_data = E1000_READ_REG(hw, TCTL);
  1765. reg_data |= E1000_TCTL_RTLC;
  1766. E1000_WRITE_REG(hw, TCTL, reg_data);
  1767. /* Configure Gigabit Carry Extend Padding */
  1768. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1769. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1770. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1771. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1772. /* Configure Transmit Inter-Packet Gap */
  1773. reg_data = E1000_READ_REG(hw, TIPG);
  1774. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1775. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1776. E1000_WRITE_REG(hw, TIPG, reg_data);
  1777. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1778. reg_data &= ~0x00100000;
  1779. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1780. /* Fall through */
  1781. case e1000_82571:
  1782. case e1000_82572:
  1783. case e1000_ich8lan:
  1784. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1785. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1786. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1787. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1788. break;
  1789. case e1000_82573:
  1790. case e1000_82574:
  1791. reg_data = E1000_READ_REG(hw, GCR);
  1792. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1793. E1000_WRITE_REG(hw, GCR, reg_data);
  1794. case e1000_igb:
  1795. break;
  1796. }
  1797. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1798. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1799. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1800. /* Relaxed ordering must be disabled to avoid a parity
  1801. * error crash in a PCI slot. */
  1802. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1803. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1804. }
  1805. return ret_val;
  1806. }
  1807. /******************************************************************************
  1808. * Configures flow control and link settings.
  1809. *
  1810. * hw - Struct containing variables accessed by shared code
  1811. *
  1812. * Determines which flow control settings to use. Calls the apropriate media-
  1813. * specific link configuration function. Configures the flow control settings.
  1814. * Assuming the adapter has a valid link partner, a valid link should be
  1815. * established. Assumes the hardware has previously been reset and the
  1816. * transmitter and receiver are not enabled.
  1817. *****************************************************************************/
  1818. static int
  1819. e1000_setup_link(struct e1000_hw *hw)
  1820. {
  1821. int32_t ret_val;
  1822. #ifndef CONFIG_E1000_NO_NVM
  1823. uint32_t ctrl_ext;
  1824. uint16_t eeprom_data;
  1825. #endif
  1826. DEBUGFUNC();
  1827. /* In the case of the phy reset being blocked, we already have a link.
  1828. * We do not have to set it up again. */
  1829. if (e1000_check_phy_reset_block(hw))
  1830. return E1000_SUCCESS;
  1831. #ifndef CONFIG_E1000_NO_NVM
  1832. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1833. * that determine the hardware's default PAUSE (flow control) mode,
  1834. * a bit that determines whether the HW defaults to enabling or
  1835. * disabling auto-negotiation, and the direction of the
  1836. * SW defined pins. If there is no SW over-ride of the flow
  1837. * control setting, then the variable hw->fc will
  1838. * be initialized based on a value in the EEPROM.
  1839. */
  1840. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1841. &eeprom_data) < 0) {
  1842. DEBUGOUT("EEPROM Read Error\n");
  1843. return -E1000_ERR_EEPROM;
  1844. }
  1845. #endif
  1846. if (hw->fc == e1000_fc_default) {
  1847. switch (hw->mac_type) {
  1848. case e1000_ich8lan:
  1849. case e1000_82573:
  1850. case e1000_82574:
  1851. case e1000_igb:
  1852. hw->fc = e1000_fc_full;
  1853. break;
  1854. default:
  1855. #ifndef CONFIG_E1000_NO_NVM
  1856. ret_val = e1000_read_eeprom(hw,
  1857. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1858. if (ret_val) {
  1859. DEBUGOUT("EEPROM Read Error\n");
  1860. return -E1000_ERR_EEPROM;
  1861. }
  1862. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1863. hw->fc = e1000_fc_none;
  1864. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1865. EEPROM_WORD0F_ASM_DIR)
  1866. hw->fc = e1000_fc_tx_pause;
  1867. else
  1868. #endif
  1869. hw->fc = e1000_fc_full;
  1870. break;
  1871. }
  1872. }
  1873. /* We want to save off the original Flow Control configuration just
  1874. * in case we get disconnected and then reconnected into a different
  1875. * hub or switch with different Flow Control capabilities.
  1876. */
  1877. if (hw->mac_type == e1000_82542_rev2_0)
  1878. hw->fc &= (~e1000_fc_tx_pause);
  1879. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1880. hw->fc &= (~e1000_fc_rx_pause);
  1881. hw->original_fc = hw->fc;
  1882. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1883. #ifndef CONFIG_E1000_NO_NVM
  1884. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1885. * polarity value for the SW controlled pins, and setup the
  1886. * Extended Device Control reg with that info.
  1887. * This is needed because one of the SW controlled pins is used for
  1888. * signal detection. So this should be done before e1000_setup_pcs_link()
  1889. * or e1000_phy_setup() is called.
  1890. */
  1891. if (hw->mac_type == e1000_82543) {
  1892. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1893. SWDPIO__EXT_SHIFT);
  1894. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1895. }
  1896. #endif
  1897. /* Call the necessary subroutine to configure the link. */
  1898. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1899. e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
  1900. if (ret_val < 0) {
  1901. return ret_val;
  1902. }
  1903. /* Initialize the flow control address, type, and PAUSE timer
  1904. * registers to their default values. This is done even if flow
  1905. * control is disabled, because it does not hurt anything to
  1906. * initialize these registers.
  1907. */
  1908. DEBUGOUT("Initializing the Flow Control address, type"
  1909. "and timer regs\n");
  1910. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1911. if (hw->mac_type != e1000_ich8lan) {
  1912. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1913. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1914. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1915. }
  1916. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1917. /* Set the flow control receive threshold registers. Normally,
  1918. * these registers will be set to a default threshold that may be
  1919. * adjusted later by the driver's runtime code. However, if the
  1920. * ability to transmit pause frames in not enabled, then these
  1921. * registers will be set to 0.
  1922. */
  1923. if (!(hw->fc & e1000_fc_tx_pause)) {
  1924. E1000_WRITE_REG(hw, FCRTL, 0);
  1925. E1000_WRITE_REG(hw, FCRTH, 0);
  1926. } else {
  1927. /* We need to set up the Receive Threshold high and low water marks
  1928. * as well as (optionally) enabling the transmission of XON frames.
  1929. */
  1930. if (hw->fc_send_xon) {
  1931. E1000_WRITE_REG(hw, FCRTL,
  1932. (hw->fc_low_water | E1000_FCRTL_XONE));
  1933. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1934. } else {
  1935. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1936. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1937. }
  1938. }
  1939. return ret_val;
  1940. }
  1941. /******************************************************************************
  1942. * Sets up link for a fiber based adapter
  1943. *
  1944. * hw - Struct containing variables accessed by shared code
  1945. *
  1946. * Manipulates Physical Coding Sublayer functions in order to configure
  1947. * link. Assumes the hardware has been previously reset and the transmitter
  1948. * and receiver are not enabled.
  1949. *****************************************************************************/
  1950. static int
  1951. e1000_setup_fiber_link(struct e1000_hw *hw)
  1952. {
  1953. uint32_t ctrl;
  1954. uint32_t status;
  1955. uint32_t txcw = 0;
  1956. uint32_t i;
  1957. uint32_t signal;
  1958. int32_t ret_val;
  1959. DEBUGFUNC();
  1960. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1961. * set when the optics detect a signal. On older adapters, it will be
  1962. * cleared when there is a signal
  1963. */
  1964. ctrl = E1000_READ_REG(hw, CTRL);
  1965. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1966. signal = E1000_CTRL_SWDPIN1;
  1967. else
  1968. signal = 0;
  1969. printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
  1970. ctrl);
  1971. /* Take the link out of reset */
  1972. ctrl &= ~(E1000_CTRL_LRST);
  1973. e1000_config_collision_dist(hw);
  1974. /* Check for a software override of the flow control settings, and setup
  1975. * the device accordingly. If auto-negotiation is enabled, then software
  1976. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1977. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1978. * auto-negotiation is disabled, then software will have to manually
  1979. * configure the two flow control enable bits in the CTRL register.
  1980. *
  1981. * The possible values of the "fc" parameter are:
  1982. * 0: Flow control is completely disabled
  1983. * 1: Rx flow control is enabled (we can receive pause frames, but
  1984. * not send pause frames).
  1985. * 2: Tx flow control is enabled (we can send pause frames but we do
  1986. * not support receiving pause frames).
  1987. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1988. */
  1989. switch (hw->fc) {
  1990. case e1000_fc_none:
  1991. /* Flow control is completely disabled by a software over-ride. */
  1992. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1993. break;
  1994. case e1000_fc_rx_pause:
  1995. /* RX Flow control is enabled and TX Flow control is disabled by a
  1996. * software over-ride. Since there really isn't a way to advertise
  1997. * that we are capable of RX Pause ONLY, we will advertise that we
  1998. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1999. * disable the adapter's ability to send PAUSE frames.
  2000. */
  2001. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2002. break;
  2003. case e1000_fc_tx_pause:
  2004. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  2005. * software over-ride.
  2006. */
  2007. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  2008. break;
  2009. case e1000_fc_full:
  2010. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  2011. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2012. break;
  2013. default:
  2014. DEBUGOUT("Flow control param set incorrectly\n");
  2015. return -E1000_ERR_CONFIG;
  2016. break;
  2017. }
  2018. /* Since auto-negotiation is enabled, take the link out of reset (the link
  2019. * will be in reset, because we previously reset the chip). This will
  2020. * restart auto-negotiation. If auto-neogtiation is successful then the
  2021. * link-up status bit will be set and the flow control enable bits (RFCE
  2022. * and TFCE) will be set according to their negotiated value.
  2023. */
  2024. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  2025. E1000_WRITE_REG(hw, TXCW, txcw);
  2026. E1000_WRITE_REG(hw, CTRL, ctrl);
  2027. E1000_WRITE_FLUSH(hw);
  2028. hw->txcw = txcw;
  2029. mdelay(1);
  2030. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  2031. * indication in the Device Status Register. Time-out if a link isn't
  2032. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  2033. * less than 500 milliseconds even if the other end is doing it in SW).
  2034. */
  2035. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  2036. DEBUGOUT("Looking for Link\n");
  2037. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  2038. mdelay(10);
  2039. status = E1000_READ_REG(hw, STATUS);
  2040. if (status & E1000_STATUS_LU)
  2041. break;
  2042. }
  2043. if (i == (LINK_UP_TIMEOUT / 10)) {
  2044. /* AutoNeg failed to achieve a link, so we'll call
  2045. * e1000_check_for_link. This routine will force the link up if we
  2046. * detect a signal. This will allow us to communicate with
  2047. * non-autonegotiating link partners.
  2048. */
  2049. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  2050. hw->autoneg_failed = 1;
  2051. ret_val = e1000_check_for_link(hw);
  2052. if (ret_val < 0) {
  2053. DEBUGOUT("Error while checking for link\n");
  2054. return ret_val;
  2055. }
  2056. hw->autoneg_failed = 0;
  2057. } else {
  2058. hw->autoneg_failed = 0;
  2059. DEBUGOUT("Valid Link Found\n");
  2060. }
  2061. } else {
  2062. DEBUGOUT("No Signal Detected\n");
  2063. return -E1000_ERR_NOLINK;
  2064. }
  2065. return 0;
  2066. }
  2067. /******************************************************************************
  2068. * Make sure we have a valid PHY and change PHY mode before link setup.
  2069. *
  2070. * hw - Struct containing variables accessed by shared code
  2071. ******************************************************************************/
  2072. static int32_t
  2073. e1000_copper_link_preconfig(struct e1000_hw *hw)
  2074. {
  2075. uint32_t ctrl;
  2076. int32_t ret_val;
  2077. uint16_t phy_data;
  2078. DEBUGFUNC();
  2079. ctrl = E1000_READ_REG(hw, CTRL);
  2080. /* With 82543, we need to force speed and duplex on the MAC equal to what
  2081. * the PHY speed and duplex configuration is. In addition, we need to
  2082. * perform a hardware reset on the PHY to take it out of reset.
  2083. */
  2084. if (hw->mac_type > e1000_82543) {
  2085. ctrl |= E1000_CTRL_SLU;
  2086. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2087. E1000_WRITE_REG(hw, CTRL, ctrl);
  2088. } else {
  2089. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  2090. | E1000_CTRL_SLU);
  2091. E1000_WRITE_REG(hw, CTRL, ctrl);
  2092. ret_val = e1000_phy_hw_reset(hw);
  2093. if (ret_val)
  2094. return ret_val;
  2095. }
  2096. /* Make sure we have a valid PHY */
  2097. ret_val = e1000_detect_gig_phy(hw);
  2098. if (ret_val) {
  2099. DEBUGOUT("Error, did not detect valid phy.\n");
  2100. return ret_val;
  2101. }
  2102. DEBUGOUT("Phy ID = %x\n", hw->phy_id);
  2103. /* Set PHY to class A mode (if necessary) */
  2104. ret_val = e1000_set_phy_mode(hw);
  2105. if (ret_val)
  2106. return ret_val;
  2107. if ((hw->mac_type == e1000_82545_rev_3) ||
  2108. (hw->mac_type == e1000_82546_rev_3)) {
  2109. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2110. &phy_data);
  2111. phy_data |= 0x00000008;
  2112. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2113. phy_data);
  2114. }
  2115. if (hw->mac_type <= e1000_82543 ||
  2116. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  2117. hw->mac_type == e1000_82541_rev_2
  2118. || hw->mac_type == e1000_82547_rev_2)
  2119. hw->phy_reset_disable = false;
  2120. return E1000_SUCCESS;
  2121. }
  2122. /*****************************************************************************
  2123. *
  2124. * This function sets the lplu state according to the active flag. When
  2125. * activating lplu this function also disables smart speed and vise versa.
  2126. * lplu will not be activated unless the device autonegotiation advertisment
  2127. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2128. * hw: Struct containing variables accessed by shared code
  2129. * active - true to enable lplu false to disable lplu.
  2130. *
  2131. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2132. * E1000_SUCCESS at any other case.
  2133. *
  2134. ****************************************************************************/
  2135. static int32_t
  2136. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  2137. {
  2138. uint32_t phy_ctrl = 0;
  2139. int32_t ret_val;
  2140. uint16_t phy_data;
  2141. DEBUGFUNC();
  2142. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  2143. && hw->phy_type != e1000_phy_igp_3)
  2144. return E1000_SUCCESS;
  2145. /* During driver activity LPLU should not be used or it will attain link
  2146. * from the lowest speeds starting from 10Mbps. The capability is used
  2147. * for Dx transitions and states */
  2148. if (hw->mac_type == e1000_82541_rev_2
  2149. || hw->mac_type == e1000_82547_rev_2) {
  2150. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2151. &phy_data);
  2152. if (ret_val)
  2153. return ret_val;
  2154. } else if (hw->mac_type == e1000_ich8lan) {
  2155. /* MAC writes into PHY register based on the state transition
  2156. * and start auto-negotiation. SW driver can overwrite the
  2157. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  2158. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2159. } else {
  2160. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2161. &phy_data);
  2162. if (ret_val)
  2163. return ret_val;
  2164. }
  2165. if (!active) {
  2166. if (hw->mac_type == e1000_82541_rev_2 ||
  2167. hw->mac_type == e1000_82547_rev_2) {
  2168. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  2169. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2170. phy_data);
  2171. if (ret_val)
  2172. return ret_val;
  2173. } else {
  2174. if (hw->mac_type == e1000_ich8lan) {
  2175. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  2176. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2177. } else {
  2178. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  2179. ret_val = e1000_write_phy_reg(hw,
  2180. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2181. if (ret_val)
  2182. return ret_val;
  2183. }
  2184. }
  2185. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2186. * Dx states where the power conservation is most important. During
  2187. * driver activity we should enable SmartSpeed, so performance is
  2188. * maintained. */
  2189. if (hw->smart_speed == e1000_smart_speed_on) {
  2190. ret_val = e1000_read_phy_reg(hw,
  2191. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2192. if (ret_val)
  2193. return ret_val;
  2194. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2195. ret_val = e1000_write_phy_reg(hw,
  2196. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2197. if (ret_val)
  2198. return ret_val;
  2199. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2200. ret_val = e1000_read_phy_reg(hw,
  2201. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2202. if (ret_val)
  2203. return ret_val;
  2204. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2205. ret_val = e1000_write_phy_reg(hw,
  2206. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2207. if (ret_val)
  2208. return ret_val;
  2209. }
  2210. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  2211. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  2212. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  2213. if (hw->mac_type == e1000_82541_rev_2 ||
  2214. hw->mac_type == e1000_82547_rev_2) {
  2215. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  2216. ret_val = e1000_write_phy_reg(hw,
  2217. IGP01E1000_GMII_FIFO, phy_data);
  2218. if (ret_val)
  2219. return ret_val;
  2220. } else {
  2221. if (hw->mac_type == e1000_ich8lan) {
  2222. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  2223. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2224. } else {
  2225. phy_data |= IGP02E1000_PM_D3_LPLU;
  2226. ret_val = e1000_write_phy_reg(hw,
  2227. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2228. if (ret_val)
  2229. return ret_val;
  2230. }
  2231. }
  2232. /* When LPLU is enabled we should disable SmartSpeed */
  2233. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2234. &phy_data);
  2235. if (ret_val)
  2236. return ret_val;
  2237. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2238. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2239. phy_data);
  2240. if (ret_val)
  2241. return ret_val;
  2242. }
  2243. return E1000_SUCCESS;
  2244. }
  2245. /*****************************************************************************
  2246. *
  2247. * This function sets the lplu d0 state according to the active flag. When
  2248. * activating lplu this function also disables smart speed and vise versa.
  2249. * lplu will not be activated unless the device autonegotiation advertisment
  2250. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2251. * hw: Struct containing variables accessed by shared code
  2252. * active - true to enable lplu false to disable lplu.
  2253. *
  2254. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2255. * E1000_SUCCESS at any other case.
  2256. *
  2257. ****************************************************************************/
  2258. static int32_t
  2259. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  2260. {
  2261. uint32_t phy_ctrl = 0;
  2262. int32_t ret_val;
  2263. uint16_t phy_data;
  2264. DEBUGFUNC();
  2265. if (hw->mac_type <= e1000_82547_rev_2)
  2266. return E1000_SUCCESS;
  2267. if (hw->mac_type == e1000_ich8lan) {
  2268. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2269. } else if (hw->mac_type == e1000_igb) {
  2270. phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
  2271. } else {
  2272. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2273. &phy_data);
  2274. if (ret_val)
  2275. return ret_val;
  2276. }
  2277. if (!active) {
  2278. if (hw->mac_type == e1000_ich8lan) {
  2279. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2280. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2281. } else if (hw->mac_type == e1000_igb) {
  2282. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2283. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2284. } else {
  2285. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2286. ret_val = e1000_write_phy_reg(hw,
  2287. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2288. if (ret_val)
  2289. return ret_val;
  2290. }
  2291. if (hw->mac_type == e1000_igb)
  2292. return E1000_SUCCESS;
  2293. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2294. * Dx states where the power conservation is most important. During
  2295. * driver activity we should enable SmartSpeed, so performance is
  2296. * maintained. */
  2297. if (hw->smart_speed == e1000_smart_speed_on) {
  2298. ret_val = e1000_read_phy_reg(hw,
  2299. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2300. if (ret_val)
  2301. return ret_val;
  2302. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2303. ret_val = e1000_write_phy_reg(hw,
  2304. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2305. if (ret_val)
  2306. return ret_val;
  2307. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2308. ret_val = e1000_read_phy_reg(hw,
  2309. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2310. if (ret_val)
  2311. return ret_val;
  2312. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2313. ret_val = e1000_write_phy_reg(hw,
  2314. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2315. if (ret_val)
  2316. return ret_val;
  2317. }
  2318. } else {
  2319. if (hw->mac_type == e1000_ich8lan) {
  2320. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2321. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2322. } else if (hw->mac_type == e1000_igb) {
  2323. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2324. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2325. } else {
  2326. phy_data |= IGP02E1000_PM_D0_LPLU;
  2327. ret_val = e1000_write_phy_reg(hw,
  2328. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2329. if (ret_val)
  2330. return ret_val;
  2331. }
  2332. if (hw->mac_type == e1000_igb)
  2333. return E1000_SUCCESS;
  2334. /* When LPLU is enabled we should disable SmartSpeed */
  2335. ret_val = e1000_read_phy_reg(hw,
  2336. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2337. if (ret_val)
  2338. return ret_val;
  2339. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2340. ret_val = e1000_write_phy_reg(hw,
  2341. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2342. if (ret_val)
  2343. return ret_val;
  2344. }
  2345. return E1000_SUCCESS;
  2346. }
  2347. /********************************************************************
  2348. * Copper link setup for e1000_phy_igp series.
  2349. *
  2350. * hw - Struct containing variables accessed by shared code
  2351. *********************************************************************/
  2352. static int32_t
  2353. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2354. {
  2355. uint32_t led_ctrl;
  2356. int32_t ret_val;
  2357. uint16_t phy_data;
  2358. DEBUGFUNC();
  2359. if (hw->phy_reset_disable)
  2360. return E1000_SUCCESS;
  2361. ret_val = e1000_phy_reset(hw);
  2362. if (ret_val) {
  2363. DEBUGOUT("Error Resetting the PHY\n");
  2364. return ret_val;
  2365. }
  2366. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2367. mdelay(15);
  2368. if (hw->mac_type != e1000_ich8lan) {
  2369. /* Configure activity LED after PHY reset */
  2370. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2371. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2372. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2373. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2374. }
  2375. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2376. if (hw->phy_type == e1000_phy_igp) {
  2377. /* disable lplu d3 during driver init */
  2378. ret_val = e1000_set_d3_lplu_state(hw, false);
  2379. if (ret_val) {
  2380. DEBUGOUT("Error Disabling LPLU D3\n");
  2381. return ret_val;
  2382. }
  2383. }
  2384. /* disable lplu d0 during driver init */
  2385. ret_val = e1000_set_d0_lplu_state(hw, false);
  2386. if (ret_val) {
  2387. DEBUGOUT("Error Disabling LPLU D0\n");
  2388. return ret_val;
  2389. }
  2390. /* Configure mdi-mdix settings */
  2391. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2392. if (ret_val)
  2393. return ret_val;
  2394. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2395. hw->dsp_config_state = e1000_dsp_config_disabled;
  2396. /* Force MDI for earlier revs of the IGP PHY */
  2397. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2398. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2399. hw->mdix = 1;
  2400. } else {
  2401. hw->dsp_config_state = e1000_dsp_config_enabled;
  2402. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2403. switch (hw->mdix) {
  2404. case 1:
  2405. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2406. break;
  2407. case 2:
  2408. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2409. break;
  2410. case 0:
  2411. default:
  2412. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2413. break;
  2414. }
  2415. }
  2416. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2417. if (ret_val)
  2418. return ret_val;
  2419. /* set auto-master slave resolution settings */
  2420. if (hw->autoneg) {
  2421. e1000_ms_type phy_ms_setting = hw->master_slave;
  2422. if (hw->ffe_config_state == e1000_ffe_config_active)
  2423. hw->ffe_config_state = e1000_ffe_config_enabled;
  2424. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2425. hw->dsp_config_state = e1000_dsp_config_enabled;
  2426. /* when autonegotiation advertisment is only 1000Mbps then we
  2427. * should disable SmartSpeed and enable Auto MasterSlave
  2428. * resolution as hardware default. */
  2429. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2430. /* Disable SmartSpeed */
  2431. ret_val = e1000_read_phy_reg(hw,
  2432. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2433. if (ret_val)
  2434. return ret_val;
  2435. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2436. ret_val = e1000_write_phy_reg(hw,
  2437. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2438. if (ret_val)
  2439. return ret_val;
  2440. /* Set auto Master/Slave resolution process */
  2441. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2442. &phy_data);
  2443. if (ret_val)
  2444. return ret_val;
  2445. phy_data &= ~CR_1000T_MS_ENABLE;
  2446. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2447. phy_data);
  2448. if (ret_val)
  2449. return ret_val;
  2450. }
  2451. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2452. if (ret_val)
  2453. return ret_val;
  2454. /* load defaults for future use */
  2455. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2456. ((phy_data & CR_1000T_MS_VALUE) ?
  2457. e1000_ms_force_master :
  2458. e1000_ms_force_slave) :
  2459. e1000_ms_auto;
  2460. switch (phy_ms_setting) {
  2461. case e1000_ms_force_master:
  2462. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2463. break;
  2464. case e1000_ms_force_slave:
  2465. phy_data |= CR_1000T_MS_ENABLE;
  2466. phy_data &= ~(CR_1000T_MS_VALUE);
  2467. break;
  2468. case e1000_ms_auto:
  2469. phy_data &= ~CR_1000T_MS_ENABLE;
  2470. default:
  2471. break;
  2472. }
  2473. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2474. if (ret_val)
  2475. return ret_val;
  2476. }
  2477. return E1000_SUCCESS;
  2478. }
  2479. /*****************************************************************************
  2480. * This function checks the mode of the firmware.
  2481. *
  2482. * returns - true when the mode is IAMT or false.
  2483. ****************************************************************************/
  2484. bool
  2485. e1000_check_mng_mode(struct e1000_hw *hw)
  2486. {
  2487. uint32_t fwsm;
  2488. DEBUGFUNC();
  2489. fwsm = E1000_READ_REG(hw, FWSM);
  2490. if (hw->mac_type == e1000_ich8lan) {
  2491. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2492. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2493. return true;
  2494. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2495. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2496. return true;
  2497. return false;
  2498. }
  2499. static int32_t
  2500. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2501. {
  2502. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2503. uint32_t reg_val;
  2504. DEBUGFUNC();
  2505. if (e1000_is_second_port(hw))
  2506. swfw = E1000_SWFW_PHY1_SM;
  2507. if (e1000_swfw_sync_acquire(hw, swfw))
  2508. return -E1000_ERR_SWFW_SYNC;
  2509. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2510. & E1000_KUMCTRLSTA_OFFSET) | data;
  2511. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2512. udelay(2);
  2513. return E1000_SUCCESS;
  2514. }
  2515. static int32_t
  2516. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2517. {
  2518. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2519. uint32_t reg_val;
  2520. DEBUGFUNC();
  2521. if (e1000_is_second_port(hw))
  2522. swfw = E1000_SWFW_PHY1_SM;
  2523. if (e1000_swfw_sync_acquire(hw, swfw)) {
  2524. debug("%s[%i]\n", __func__, __LINE__);
  2525. return -E1000_ERR_SWFW_SYNC;
  2526. }
  2527. /* Write register address */
  2528. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2529. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2530. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2531. udelay(2);
  2532. /* Read the data returned */
  2533. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2534. *data = (uint16_t)reg_val;
  2535. return E1000_SUCCESS;
  2536. }
  2537. /********************************************************************
  2538. * Copper link setup for e1000_phy_gg82563 series.
  2539. *
  2540. * hw - Struct containing variables accessed by shared code
  2541. *********************************************************************/
  2542. static int32_t
  2543. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2544. {
  2545. int32_t ret_val;
  2546. uint16_t phy_data;
  2547. uint32_t reg_data;
  2548. DEBUGFUNC();
  2549. if (!hw->phy_reset_disable) {
  2550. /* Enable CRS on TX for half-duplex operation. */
  2551. ret_val = e1000_read_phy_reg(hw,
  2552. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2553. if (ret_val)
  2554. return ret_val;
  2555. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2556. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2557. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2558. ret_val = e1000_write_phy_reg(hw,
  2559. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2560. if (ret_val)
  2561. return ret_val;
  2562. /* Options:
  2563. * MDI/MDI-X = 0 (default)
  2564. * 0 - Auto for all speeds
  2565. * 1 - MDI mode
  2566. * 2 - MDI-X mode
  2567. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2568. */
  2569. ret_val = e1000_read_phy_reg(hw,
  2570. GG82563_PHY_SPEC_CTRL, &phy_data);
  2571. if (ret_val)
  2572. return ret_val;
  2573. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2574. switch (hw->mdix) {
  2575. case 1:
  2576. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2577. break;
  2578. case 2:
  2579. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2580. break;
  2581. case 0:
  2582. default:
  2583. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2584. break;
  2585. }
  2586. /* Options:
  2587. * disable_polarity_correction = 0 (default)
  2588. * Automatic Correction for Reversed Cable Polarity
  2589. * 0 - Disabled
  2590. * 1 - Enabled
  2591. */
  2592. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2593. ret_val = e1000_write_phy_reg(hw,
  2594. GG82563_PHY_SPEC_CTRL, phy_data);
  2595. if (ret_val)
  2596. return ret_val;
  2597. /* SW Reset the PHY so all changes take effect */
  2598. ret_val = e1000_phy_reset(hw);
  2599. if (ret_val) {
  2600. DEBUGOUT("Error Resetting the PHY\n");
  2601. return ret_val;
  2602. }
  2603. } /* phy_reset_disable */
  2604. if (hw->mac_type == e1000_80003es2lan) {
  2605. /* Bypass RX and TX FIFO's */
  2606. ret_val = e1000_write_kmrn_reg(hw,
  2607. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2608. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2609. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2610. if (ret_val)
  2611. return ret_val;
  2612. ret_val = e1000_read_phy_reg(hw,
  2613. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2614. if (ret_val)
  2615. return ret_val;
  2616. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2617. ret_val = e1000_write_phy_reg(hw,
  2618. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2619. if (ret_val)
  2620. return ret_val;
  2621. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2622. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2623. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2624. ret_val = e1000_read_phy_reg(hw,
  2625. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2626. if (ret_val)
  2627. return ret_val;
  2628. /* Do not init these registers when the HW is in IAMT mode, since the
  2629. * firmware will have already initialized them. We only initialize
  2630. * them if the HW is not in IAMT mode.
  2631. */
  2632. if (e1000_check_mng_mode(hw) == false) {
  2633. /* Enable Electrical Idle on the PHY */
  2634. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2635. ret_val = e1000_write_phy_reg(hw,
  2636. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2637. if (ret_val)
  2638. return ret_val;
  2639. ret_val = e1000_read_phy_reg(hw,
  2640. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2641. if (ret_val)
  2642. return ret_val;
  2643. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2644. ret_val = e1000_write_phy_reg(hw,
  2645. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2646. if (ret_val)
  2647. return ret_val;
  2648. }
  2649. /* Workaround: Disable padding in Kumeran interface in the MAC
  2650. * and in the PHY to avoid CRC errors.
  2651. */
  2652. ret_val = e1000_read_phy_reg(hw,
  2653. GG82563_PHY_INBAND_CTRL, &phy_data);
  2654. if (ret_val)
  2655. return ret_val;
  2656. phy_data |= GG82563_ICR_DIS_PADDING;
  2657. ret_val = e1000_write_phy_reg(hw,
  2658. GG82563_PHY_INBAND_CTRL, phy_data);
  2659. if (ret_val)
  2660. return ret_val;
  2661. }
  2662. return E1000_SUCCESS;
  2663. }
  2664. /********************************************************************
  2665. * Copper link setup for e1000_phy_m88 series.
  2666. *
  2667. * hw - Struct containing variables accessed by shared code
  2668. *********************************************************************/
  2669. static int32_t
  2670. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2671. {
  2672. int32_t ret_val;
  2673. uint16_t phy_data;
  2674. DEBUGFUNC();
  2675. if (hw->phy_reset_disable)
  2676. return E1000_SUCCESS;
  2677. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2678. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2679. if (ret_val)
  2680. return ret_val;
  2681. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2682. /* Options:
  2683. * MDI/MDI-X = 0 (default)
  2684. * 0 - Auto for all speeds
  2685. * 1 - MDI mode
  2686. * 2 - MDI-X mode
  2687. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2688. */
  2689. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2690. switch (hw->mdix) {
  2691. case 1:
  2692. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2693. break;
  2694. case 2:
  2695. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2696. break;
  2697. case 3:
  2698. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2699. break;
  2700. case 0:
  2701. default:
  2702. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2703. break;
  2704. }
  2705. /* Options:
  2706. * disable_polarity_correction = 0 (default)
  2707. * Automatic Correction for Reversed Cable Polarity
  2708. * 0 - Disabled
  2709. * 1 - Enabled
  2710. */
  2711. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2712. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2713. if (ret_val)
  2714. return ret_val;
  2715. if (hw->phy_revision < M88E1011_I_REV_4) {
  2716. /* Force TX_CLK in the Extended PHY Specific Control Register
  2717. * to 25MHz clock.
  2718. */
  2719. ret_val = e1000_read_phy_reg(hw,
  2720. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2721. if (ret_val)
  2722. return ret_val;
  2723. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2724. if ((hw->phy_revision == E1000_REVISION_2) &&
  2725. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2726. /* Vidalia Phy, set the downshift counter to 5x */
  2727. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2728. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2729. ret_val = e1000_write_phy_reg(hw,
  2730. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2731. if (ret_val)
  2732. return ret_val;
  2733. } else {
  2734. /* Configure Master and Slave downshift values */
  2735. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2736. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2737. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2738. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2739. ret_val = e1000_write_phy_reg(hw,
  2740. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2741. if (ret_val)
  2742. return ret_val;
  2743. }
  2744. }
  2745. /* SW Reset the PHY so all changes take effect */
  2746. ret_val = e1000_phy_reset(hw);
  2747. if (ret_val) {
  2748. DEBUGOUT("Error Resetting the PHY\n");
  2749. return ret_val;
  2750. }
  2751. return E1000_SUCCESS;
  2752. }
  2753. /********************************************************************
  2754. * Setup auto-negotiation and flow control advertisements,
  2755. * and then perform auto-negotiation.
  2756. *
  2757. * hw - Struct containing variables accessed by shared code
  2758. *********************************************************************/
  2759. static int32_t
  2760. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2761. {
  2762. int32_t ret_val;
  2763. uint16_t phy_data;
  2764. DEBUGFUNC();
  2765. /* Perform some bounds checking on the hw->autoneg_advertised
  2766. * parameter. If this variable is zero, then set it to the default.
  2767. */
  2768. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2769. /* If autoneg_advertised is zero, we assume it was not defaulted
  2770. * by the calling code so we set to advertise full capability.
  2771. */
  2772. if (hw->autoneg_advertised == 0)
  2773. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2774. /* IFE phy only supports 10/100 */
  2775. if (hw->phy_type == e1000_phy_ife)
  2776. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2777. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2778. ret_val = e1000_phy_setup_autoneg(hw);
  2779. if (ret_val) {
  2780. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2781. return ret_val;
  2782. }
  2783. DEBUGOUT("Restarting Auto-Neg\n");
  2784. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2785. * the Auto Neg Restart bit in the PHY control register.
  2786. */
  2787. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2788. if (ret_val)
  2789. return ret_val;
  2790. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2791. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2792. if (ret_val)
  2793. return ret_val;
  2794. /* Does the user want to wait for Auto-Neg to complete here, or
  2795. * check at a later time (for example, callback routine).
  2796. */
  2797. /* If we do not wait for autonegtation to complete I
  2798. * do not see a valid link status.
  2799. * wait_autoneg_complete = 1 .
  2800. */
  2801. if (hw->wait_autoneg_complete) {
  2802. ret_val = e1000_wait_autoneg(hw);
  2803. if (ret_val) {
  2804. DEBUGOUT("Error while waiting for autoneg"
  2805. "to complete\n");
  2806. return ret_val;
  2807. }
  2808. }
  2809. hw->get_link_status = true;
  2810. return E1000_SUCCESS;
  2811. }
  2812. /******************************************************************************
  2813. * Config the MAC and the PHY after link is up.
  2814. * 1) Set up the MAC to the current PHY speed/duplex
  2815. * if we are on 82543. If we
  2816. * are on newer silicon, we only need to configure
  2817. * collision distance in the Transmit Control Register.
  2818. * 2) Set up flow control on the MAC to that established with
  2819. * the link partner.
  2820. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2821. *
  2822. * hw - Struct containing variables accessed by shared code
  2823. ******************************************************************************/
  2824. static int32_t
  2825. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2826. {
  2827. int32_t ret_val;
  2828. DEBUGFUNC();
  2829. if (hw->mac_type >= e1000_82544) {
  2830. e1000_config_collision_dist(hw);
  2831. } else {
  2832. ret_val = e1000_config_mac_to_phy(hw);
  2833. if (ret_val) {
  2834. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2835. return ret_val;
  2836. }
  2837. }
  2838. ret_val = e1000_config_fc_after_link_up(hw);
  2839. if (ret_val) {
  2840. DEBUGOUT("Error Configuring Flow Control\n");
  2841. return ret_val;
  2842. }
  2843. return E1000_SUCCESS;
  2844. }
  2845. /******************************************************************************
  2846. * Detects which PHY is present and setup the speed and duplex
  2847. *
  2848. * hw - Struct containing variables accessed by shared code
  2849. ******************************************************************************/
  2850. static int
  2851. e1000_setup_copper_link(struct e1000_hw *hw)
  2852. {
  2853. int32_t ret_val;
  2854. uint16_t i;
  2855. uint16_t phy_data;
  2856. uint16_t reg_data;
  2857. DEBUGFUNC();
  2858. switch (hw->mac_type) {
  2859. case e1000_80003es2lan:
  2860. case e1000_ich8lan:
  2861. /* Set the mac to wait the maximum time between each
  2862. * iteration and increase the max iterations when
  2863. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2864. ret_val = e1000_write_kmrn_reg(hw,
  2865. GG82563_REG(0x34, 4), 0xFFFF);
  2866. if (ret_val)
  2867. return ret_val;
  2868. ret_val = e1000_read_kmrn_reg(hw,
  2869. GG82563_REG(0x34, 9), &reg_data);
  2870. if (ret_val)
  2871. return ret_val;
  2872. reg_data |= 0x3F;
  2873. ret_val = e1000_write_kmrn_reg(hw,
  2874. GG82563_REG(0x34, 9), reg_data);
  2875. if (ret_val)
  2876. return ret_val;
  2877. default:
  2878. break;
  2879. }
  2880. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2881. ret_val = e1000_copper_link_preconfig(hw);
  2882. if (ret_val)
  2883. return ret_val;
  2884. switch (hw->mac_type) {
  2885. case e1000_80003es2lan:
  2886. /* Kumeran registers are written-only */
  2887. reg_data =
  2888. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2889. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2890. ret_val = e1000_write_kmrn_reg(hw,
  2891. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2892. if (ret_val)
  2893. return ret_val;
  2894. break;
  2895. default:
  2896. break;
  2897. }
  2898. if (hw->phy_type == e1000_phy_igp ||
  2899. hw->phy_type == e1000_phy_igp_3 ||
  2900. hw->phy_type == e1000_phy_igp_2) {
  2901. ret_val = e1000_copper_link_igp_setup(hw);
  2902. if (ret_val)
  2903. return ret_val;
  2904. } else if (hw->phy_type == e1000_phy_m88 ||
  2905. hw->phy_type == e1000_phy_igb) {
  2906. ret_val = e1000_copper_link_mgp_setup(hw);
  2907. if (ret_val)
  2908. return ret_val;
  2909. } else if (hw->phy_type == e1000_phy_gg82563) {
  2910. ret_val = e1000_copper_link_ggp_setup(hw);
  2911. if (ret_val)
  2912. return ret_val;
  2913. }
  2914. /* always auto */
  2915. /* Setup autoneg and flow control advertisement
  2916. * and perform autonegotiation */
  2917. ret_val = e1000_copper_link_autoneg(hw);
  2918. if (ret_val)
  2919. return ret_val;
  2920. /* Check link status. Wait up to 100 microseconds for link to become
  2921. * valid.
  2922. */
  2923. for (i = 0; i < 10; i++) {
  2924. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2925. if (ret_val)
  2926. return ret_val;
  2927. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2928. if (ret_val)
  2929. return ret_val;
  2930. if (phy_data & MII_SR_LINK_STATUS) {
  2931. /* Config the MAC and PHY after link is up */
  2932. ret_val = e1000_copper_link_postconfig(hw);
  2933. if (ret_val)
  2934. return ret_val;
  2935. DEBUGOUT("Valid link established!!!\n");
  2936. return E1000_SUCCESS;
  2937. }
  2938. udelay(10);
  2939. }
  2940. DEBUGOUT("Unable to establish link!!!\n");
  2941. return E1000_SUCCESS;
  2942. }
  2943. /******************************************************************************
  2944. * Configures PHY autoneg and flow control advertisement settings
  2945. *
  2946. * hw - Struct containing variables accessed by shared code
  2947. ******************************************************************************/
  2948. int32_t
  2949. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2950. {
  2951. int32_t ret_val;
  2952. uint16_t mii_autoneg_adv_reg;
  2953. uint16_t mii_1000t_ctrl_reg;
  2954. DEBUGFUNC();
  2955. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2956. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2957. if (ret_val)
  2958. return ret_val;
  2959. if (hw->phy_type != e1000_phy_ife) {
  2960. /* Read the MII 1000Base-T Control Register (Address 9). */
  2961. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2962. &mii_1000t_ctrl_reg);
  2963. if (ret_val)
  2964. return ret_val;
  2965. } else
  2966. mii_1000t_ctrl_reg = 0;
  2967. /* Need to parse both autoneg_advertised and fc and set up
  2968. * the appropriate PHY registers. First we will parse for
  2969. * autoneg_advertised software override. Since we can advertise
  2970. * a plethora of combinations, we need to check each bit
  2971. * individually.
  2972. */
  2973. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2974. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2975. * the 1000Base-T Control Register (Address 9).
  2976. */
  2977. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2978. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2979. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2980. /* Do we want to advertise 10 Mb Half Duplex? */
  2981. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2982. DEBUGOUT("Advertise 10mb Half duplex\n");
  2983. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2984. }
  2985. /* Do we want to advertise 10 Mb Full Duplex? */
  2986. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2987. DEBUGOUT("Advertise 10mb Full duplex\n");
  2988. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2989. }
  2990. /* Do we want to advertise 100 Mb Half Duplex? */
  2991. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2992. DEBUGOUT("Advertise 100mb Half duplex\n");
  2993. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2994. }
  2995. /* Do we want to advertise 100 Mb Full Duplex? */
  2996. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2997. DEBUGOUT("Advertise 100mb Full duplex\n");
  2998. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  2999. }
  3000. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  3001. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  3002. DEBUGOUT
  3003. ("Advertise 1000mb Half duplex requested, request denied!\n");
  3004. }
  3005. /* Do we want to advertise 1000 Mb Full Duplex? */
  3006. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  3007. DEBUGOUT("Advertise 1000mb Full duplex\n");
  3008. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  3009. }
  3010. /* Check for a software override of the flow control settings, and
  3011. * setup the PHY advertisement registers accordingly. If
  3012. * auto-negotiation is enabled, then software will have to set the
  3013. * "PAUSE" bits to the correct value in the Auto-Negotiation
  3014. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  3015. *
  3016. * The possible values of the "fc" parameter are:
  3017. * 0: Flow control is completely disabled
  3018. * 1: Rx flow control is enabled (we can receive pause frames
  3019. * but not send pause frames).
  3020. * 2: Tx flow control is enabled (we can send pause frames
  3021. * but we do not support receiving pause frames).
  3022. * 3: Both Rx and TX flow control (symmetric) are enabled.
  3023. * other: No software override. The flow control configuration
  3024. * in the EEPROM is used.
  3025. */
  3026. switch (hw->fc) {
  3027. case e1000_fc_none: /* 0 */
  3028. /* Flow control (RX & TX) is completely disabled by a
  3029. * software over-ride.
  3030. */
  3031. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3032. break;
  3033. case e1000_fc_rx_pause: /* 1 */
  3034. /* RX Flow control is enabled, and TX Flow control is
  3035. * disabled, by a software over-ride.
  3036. */
  3037. /* Since there really isn't a way to advertise that we are
  3038. * capable of RX Pause ONLY, we will advertise that we
  3039. * support both symmetric and asymmetric RX PAUSE. Later
  3040. * (in e1000_config_fc_after_link_up) we will disable the
  3041. *hw's ability to send PAUSE frames.
  3042. */
  3043. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3044. break;
  3045. case e1000_fc_tx_pause: /* 2 */
  3046. /* TX Flow control is enabled, and RX Flow control is
  3047. * disabled, by a software over-ride.
  3048. */
  3049. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  3050. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  3051. break;
  3052. case e1000_fc_full: /* 3 */
  3053. /* Flow control (both RX and TX) is enabled by a software
  3054. * over-ride.
  3055. */
  3056. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3057. break;
  3058. default:
  3059. DEBUGOUT("Flow control param set incorrectly\n");
  3060. return -E1000_ERR_CONFIG;
  3061. }
  3062. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  3063. if (ret_val)
  3064. return ret_val;
  3065. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  3066. if (hw->phy_type != e1000_phy_ife) {
  3067. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  3068. mii_1000t_ctrl_reg);
  3069. if (ret_val)
  3070. return ret_val;
  3071. }
  3072. return E1000_SUCCESS;
  3073. }
  3074. /******************************************************************************
  3075. * Sets the collision distance in the Transmit Control register
  3076. *
  3077. * hw - Struct containing variables accessed by shared code
  3078. *
  3079. * Link should have been established previously. Reads the speed and duplex
  3080. * information from the Device Status register.
  3081. ******************************************************************************/
  3082. static void
  3083. e1000_config_collision_dist(struct e1000_hw *hw)
  3084. {
  3085. uint32_t tctl, coll_dist;
  3086. DEBUGFUNC();
  3087. if (hw->mac_type < e1000_82543)
  3088. coll_dist = E1000_COLLISION_DISTANCE_82542;
  3089. else
  3090. coll_dist = E1000_COLLISION_DISTANCE;
  3091. tctl = E1000_READ_REG(hw, TCTL);
  3092. tctl &= ~E1000_TCTL_COLD;
  3093. tctl |= coll_dist << E1000_COLD_SHIFT;
  3094. E1000_WRITE_REG(hw, TCTL, tctl);
  3095. E1000_WRITE_FLUSH(hw);
  3096. }
  3097. /******************************************************************************
  3098. * Sets MAC speed and duplex settings to reflect the those in the PHY
  3099. *
  3100. * hw - Struct containing variables accessed by shared code
  3101. * mii_reg - data to write to the MII control register
  3102. *
  3103. * The contents of the PHY register containing the needed information need to
  3104. * be passed in.
  3105. ******************************************************************************/
  3106. static int
  3107. e1000_config_mac_to_phy(struct e1000_hw *hw)
  3108. {
  3109. uint32_t ctrl;
  3110. uint16_t phy_data;
  3111. DEBUGFUNC();
  3112. /* Read the Device Control Register and set the bits to Force Speed
  3113. * and Duplex.
  3114. */
  3115. ctrl = E1000_READ_REG(hw, CTRL);
  3116. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  3117. ctrl &= ~(E1000_CTRL_ILOS);
  3118. ctrl |= (E1000_CTRL_SPD_SEL);
  3119. /* Set up duplex in the Device Control and Transmit Control
  3120. * registers depending on negotiated values.
  3121. */
  3122. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  3123. DEBUGOUT("PHY Read Error\n");
  3124. return -E1000_ERR_PHY;
  3125. }
  3126. if (phy_data & M88E1000_PSSR_DPLX)
  3127. ctrl |= E1000_CTRL_FD;
  3128. else
  3129. ctrl &= ~E1000_CTRL_FD;
  3130. e1000_config_collision_dist(hw);
  3131. /* Set up speed in the Device Control register depending on
  3132. * negotiated values.
  3133. */
  3134. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  3135. ctrl |= E1000_CTRL_SPD_1000;
  3136. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  3137. ctrl |= E1000_CTRL_SPD_100;
  3138. /* Write the configured values back to the Device Control Reg. */
  3139. E1000_WRITE_REG(hw, CTRL, ctrl);
  3140. return 0;
  3141. }
  3142. /******************************************************************************
  3143. * Forces the MAC's flow control settings.
  3144. *
  3145. * hw - Struct containing variables accessed by shared code
  3146. *
  3147. * Sets the TFCE and RFCE bits in the device control register to reflect
  3148. * the adapter settings. TFCE and RFCE need to be explicitly set by
  3149. * software when a Copper PHY is used because autonegotiation is managed
  3150. * by the PHY rather than the MAC. Software must also configure these
  3151. * bits when link is forced on a fiber connection.
  3152. *****************************************************************************/
  3153. static int
  3154. e1000_force_mac_fc(struct e1000_hw *hw)
  3155. {
  3156. uint32_t ctrl;
  3157. DEBUGFUNC();
  3158. /* Get the current configuration of the Device Control Register */
  3159. ctrl = E1000_READ_REG(hw, CTRL);
  3160. /* Because we didn't get link via the internal auto-negotiation
  3161. * mechanism (we either forced link or we got link via PHY
  3162. * auto-neg), we have to manually enable/disable transmit an
  3163. * receive flow control.
  3164. *
  3165. * The "Case" statement below enables/disable flow control
  3166. * according to the "hw->fc" parameter.
  3167. *
  3168. * The possible values of the "fc" parameter are:
  3169. * 0: Flow control is completely disabled
  3170. * 1: Rx flow control is enabled (we can receive pause
  3171. * frames but not send pause frames).
  3172. * 2: Tx flow control is enabled (we can send pause frames
  3173. * frames but we do not receive pause frames).
  3174. * 3: Both Rx and TX flow control (symmetric) is enabled.
  3175. * other: No other values should be possible at this point.
  3176. */
  3177. switch (hw->fc) {
  3178. case e1000_fc_none:
  3179. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  3180. break;
  3181. case e1000_fc_rx_pause:
  3182. ctrl &= (~E1000_CTRL_TFCE);
  3183. ctrl |= E1000_CTRL_RFCE;
  3184. break;
  3185. case e1000_fc_tx_pause:
  3186. ctrl &= (~E1000_CTRL_RFCE);
  3187. ctrl |= E1000_CTRL_TFCE;
  3188. break;
  3189. case e1000_fc_full:
  3190. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  3191. break;
  3192. default:
  3193. DEBUGOUT("Flow control param set incorrectly\n");
  3194. return -E1000_ERR_CONFIG;
  3195. }
  3196. /* Disable TX Flow Control for 82542 (rev 2.0) */
  3197. if (hw->mac_type == e1000_82542_rev2_0)
  3198. ctrl &= (~E1000_CTRL_TFCE);
  3199. E1000_WRITE_REG(hw, CTRL, ctrl);
  3200. return 0;
  3201. }
  3202. /******************************************************************************
  3203. * Configures flow control settings after link is established
  3204. *
  3205. * hw - Struct containing variables accessed by shared code
  3206. *
  3207. * Should be called immediately after a valid link has been established.
  3208. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  3209. * and autonegotiation is enabled, the MAC flow control settings will be set
  3210. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  3211. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  3212. *****************************************************************************/
  3213. static int32_t
  3214. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  3215. {
  3216. int32_t ret_val;
  3217. uint16_t mii_status_reg;
  3218. uint16_t mii_nway_adv_reg;
  3219. uint16_t mii_nway_lp_ability_reg;
  3220. uint16_t speed;
  3221. uint16_t duplex;
  3222. DEBUGFUNC();
  3223. /* Check for the case where we have fiber media and auto-neg failed
  3224. * so we had to force link. In this case, we need to force the
  3225. * configuration of the MAC to match the "fc" parameter.
  3226. */
  3227. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  3228. || ((hw->media_type == e1000_media_type_internal_serdes)
  3229. && (hw->autoneg_failed))
  3230. || ((hw->media_type == e1000_media_type_copper)
  3231. && (!hw->autoneg))) {
  3232. ret_val = e1000_force_mac_fc(hw);
  3233. if (ret_val < 0) {
  3234. DEBUGOUT("Error forcing flow control settings\n");
  3235. return ret_val;
  3236. }
  3237. }
  3238. /* Check for the case where we have copper media and auto-neg is
  3239. * enabled. In this case, we need to check and see if Auto-Neg
  3240. * has completed, and if so, how the PHY and link partner has
  3241. * flow control configured.
  3242. */
  3243. if (hw->media_type == e1000_media_type_copper) {
  3244. /* Read the MII Status Register and check to see if AutoNeg
  3245. * has completed. We read this twice because this reg has
  3246. * some "sticky" (latched) bits.
  3247. */
  3248. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3249. DEBUGOUT("PHY Read Error\n");
  3250. return -E1000_ERR_PHY;
  3251. }
  3252. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3253. DEBUGOUT("PHY Read Error\n");
  3254. return -E1000_ERR_PHY;
  3255. }
  3256. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  3257. /* The AutoNeg process has completed, so we now need to
  3258. * read both the Auto Negotiation Advertisement Register
  3259. * (Address 4) and the Auto_Negotiation Base Page Ability
  3260. * Register (Address 5) to determine how flow control was
  3261. * negotiated.
  3262. */
  3263. if (e1000_read_phy_reg
  3264. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  3265. DEBUGOUT("PHY Read Error\n");
  3266. return -E1000_ERR_PHY;
  3267. }
  3268. if (e1000_read_phy_reg
  3269. (hw, PHY_LP_ABILITY,
  3270. &mii_nway_lp_ability_reg) < 0) {
  3271. DEBUGOUT("PHY Read Error\n");
  3272. return -E1000_ERR_PHY;
  3273. }
  3274. /* Two bits in the Auto Negotiation Advertisement Register
  3275. * (Address 4) and two bits in the Auto Negotiation Base
  3276. * Page Ability Register (Address 5) determine flow control
  3277. * for both the PHY and the link partner. The following
  3278. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  3279. * 1999, describes these PAUSE resolution bits and how flow
  3280. * control is determined based upon these settings.
  3281. * NOTE: DC = Don't Care
  3282. *
  3283. * LOCAL DEVICE | LINK PARTNER
  3284. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  3285. *-------|---------|-------|---------|--------------------
  3286. * 0 | 0 | DC | DC | e1000_fc_none
  3287. * 0 | 1 | 0 | DC | e1000_fc_none
  3288. * 0 | 1 | 1 | 0 | e1000_fc_none
  3289. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3290. * 1 | 0 | 0 | DC | e1000_fc_none
  3291. * 1 | DC | 1 | DC | e1000_fc_full
  3292. * 1 | 1 | 0 | 0 | e1000_fc_none
  3293. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3294. *
  3295. */
  3296. /* Are both PAUSE bits set to 1? If so, this implies
  3297. * Symmetric Flow Control is enabled at both ends. The
  3298. * ASM_DIR bits are irrelevant per the spec.
  3299. *
  3300. * For Symmetric Flow Control:
  3301. *
  3302. * LOCAL DEVICE | LINK PARTNER
  3303. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3304. *-------|---------|-------|---------|--------------------
  3305. * 1 | DC | 1 | DC | e1000_fc_full
  3306. *
  3307. */
  3308. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3309. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3310. /* Now we need to check if the user selected RX ONLY
  3311. * of pause frames. In this case, we had to advertise
  3312. * FULL flow control because we could not advertise RX
  3313. * ONLY. Hence, we must now check to see if we need to
  3314. * turn OFF the TRANSMISSION of PAUSE frames.
  3315. */
  3316. if (hw->original_fc == e1000_fc_full) {
  3317. hw->fc = e1000_fc_full;
  3318. DEBUGOUT("Flow Control = FULL.\r\n");
  3319. } else {
  3320. hw->fc = e1000_fc_rx_pause;
  3321. DEBUGOUT
  3322. ("Flow Control = RX PAUSE frames only.\r\n");
  3323. }
  3324. }
  3325. /* For receiving PAUSE frames ONLY.
  3326. *
  3327. * LOCAL DEVICE | LINK PARTNER
  3328. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3329. *-------|---------|-------|---------|--------------------
  3330. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3331. *
  3332. */
  3333. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3334. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3335. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3336. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3337. {
  3338. hw->fc = e1000_fc_tx_pause;
  3339. DEBUGOUT
  3340. ("Flow Control = TX PAUSE frames only.\r\n");
  3341. }
  3342. /* For transmitting PAUSE frames ONLY.
  3343. *
  3344. * LOCAL DEVICE | LINK PARTNER
  3345. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3346. *-------|---------|-------|---------|--------------------
  3347. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3348. *
  3349. */
  3350. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3351. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3352. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3353. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3354. {
  3355. hw->fc = e1000_fc_rx_pause;
  3356. DEBUGOUT
  3357. ("Flow Control = RX PAUSE frames only.\r\n");
  3358. }
  3359. /* Per the IEEE spec, at this point flow control should be
  3360. * disabled. However, we want to consider that we could
  3361. * be connected to a legacy switch that doesn't advertise
  3362. * desired flow control, but can be forced on the link
  3363. * partner. So if we advertised no flow control, that is
  3364. * what we will resolve to. If we advertised some kind of
  3365. * receive capability (Rx Pause Only or Full Flow Control)
  3366. * and the link partner advertised none, we will configure
  3367. * ourselves to enable Rx Flow Control only. We can do
  3368. * this safely for two reasons: If the link partner really
  3369. * didn't want flow control enabled, and we enable Rx, no
  3370. * harm done since we won't be receiving any PAUSE frames
  3371. * anyway. If the intent on the link partner was to have
  3372. * flow control enabled, then by us enabling RX only, we
  3373. * can at least receive pause frames and process them.
  3374. * This is a good idea because in most cases, since we are
  3375. * predominantly a server NIC, more times than not we will
  3376. * be asked to delay transmission of packets than asking
  3377. * our link partner to pause transmission of frames.
  3378. */
  3379. else if (hw->original_fc == e1000_fc_none ||
  3380. hw->original_fc == e1000_fc_tx_pause) {
  3381. hw->fc = e1000_fc_none;
  3382. DEBUGOUT("Flow Control = NONE.\r\n");
  3383. } else {
  3384. hw->fc = e1000_fc_rx_pause;
  3385. DEBUGOUT
  3386. ("Flow Control = RX PAUSE frames only.\r\n");
  3387. }
  3388. /* Now we need to do one last check... If we auto-
  3389. * negotiated to HALF DUPLEX, flow control should not be
  3390. * enabled per IEEE 802.3 spec.
  3391. */
  3392. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3393. if (duplex == HALF_DUPLEX)
  3394. hw->fc = e1000_fc_none;
  3395. /* Now we call a subroutine to actually force the MAC
  3396. * controller to use the correct flow control settings.
  3397. */
  3398. ret_val = e1000_force_mac_fc(hw);
  3399. if (ret_val < 0) {
  3400. DEBUGOUT
  3401. ("Error forcing flow control settings\n");
  3402. return ret_val;
  3403. }
  3404. } else {
  3405. DEBUGOUT
  3406. ("Copper PHY and Auto Neg has not completed.\r\n");
  3407. }
  3408. }
  3409. return E1000_SUCCESS;
  3410. }
  3411. /******************************************************************************
  3412. * Checks to see if the link status of the hardware has changed.
  3413. *
  3414. * hw - Struct containing variables accessed by shared code
  3415. *
  3416. * Called by any function that needs to check the link status of the adapter.
  3417. *****************************************************************************/
  3418. static int
  3419. e1000_check_for_link(struct e1000_hw *hw)
  3420. {
  3421. uint32_t rxcw;
  3422. uint32_t ctrl;
  3423. uint32_t status;
  3424. uint32_t rctl;
  3425. uint32_t signal;
  3426. int32_t ret_val;
  3427. uint16_t phy_data;
  3428. uint16_t lp_capability;
  3429. DEBUGFUNC();
  3430. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3431. * set when the optics detect a signal. On older adapters, it will be
  3432. * cleared when there is a signal
  3433. */
  3434. ctrl = E1000_READ_REG(hw, CTRL);
  3435. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3436. signal = E1000_CTRL_SWDPIN1;
  3437. else
  3438. signal = 0;
  3439. status = E1000_READ_REG(hw, STATUS);
  3440. rxcw = E1000_READ_REG(hw, RXCW);
  3441. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3442. /* If we have a copper PHY then we only want to go out to the PHY
  3443. * registers to see if Auto-Neg has completed and/or if our link
  3444. * status has changed. The get_link_status flag will be set if we
  3445. * receive a Link Status Change interrupt or we have Rx Sequence
  3446. * Errors.
  3447. */
  3448. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3449. /* First we want to see if the MII Status Register reports
  3450. * link. If so, then we want to get the current speed/duplex
  3451. * of the PHY.
  3452. * Read the register twice since the link bit is sticky.
  3453. */
  3454. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3455. DEBUGOUT("PHY Read Error\n");
  3456. return -E1000_ERR_PHY;
  3457. }
  3458. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3459. DEBUGOUT("PHY Read Error\n");
  3460. return -E1000_ERR_PHY;
  3461. }
  3462. if (phy_data & MII_SR_LINK_STATUS) {
  3463. hw->get_link_status = false;
  3464. } else {
  3465. /* No link detected */
  3466. return -E1000_ERR_NOLINK;
  3467. }
  3468. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3469. * have Si on board that is 82544 or newer, Auto
  3470. * Speed Detection takes care of MAC speed/duplex
  3471. * configuration. So we only need to configure Collision
  3472. * Distance in the MAC. Otherwise, we need to force
  3473. * speed/duplex on the MAC to the current PHY speed/duplex
  3474. * settings.
  3475. */
  3476. if (hw->mac_type >= e1000_82544)
  3477. e1000_config_collision_dist(hw);
  3478. else {
  3479. ret_val = e1000_config_mac_to_phy(hw);
  3480. if (ret_val < 0) {
  3481. DEBUGOUT
  3482. ("Error configuring MAC to PHY settings\n");
  3483. return ret_val;
  3484. }
  3485. }
  3486. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3487. * need to restore the desired flow control settings because we may
  3488. * have had to re-autoneg with a different link partner.
  3489. */
  3490. ret_val = e1000_config_fc_after_link_up(hw);
  3491. if (ret_val < 0) {
  3492. DEBUGOUT("Error configuring flow control\n");
  3493. return ret_val;
  3494. }
  3495. /* At this point we know that we are on copper and we have
  3496. * auto-negotiated link. These are conditions for checking the link
  3497. * parter capability register. We use the link partner capability to
  3498. * determine if TBI Compatibility needs to be turned on or off. If
  3499. * the link partner advertises any speed in addition to Gigabit, then
  3500. * we assume that they are GMII-based, and TBI compatibility is not
  3501. * needed. If no other speeds are advertised, we assume the link
  3502. * partner is TBI-based, and we turn on TBI Compatibility.
  3503. */
  3504. if (hw->tbi_compatibility_en) {
  3505. if (e1000_read_phy_reg
  3506. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3507. DEBUGOUT("PHY Read Error\n");
  3508. return -E1000_ERR_PHY;
  3509. }
  3510. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3511. NWAY_LPAR_10T_FD_CAPS |
  3512. NWAY_LPAR_100TX_HD_CAPS |
  3513. NWAY_LPAR_100TX_FD_CAPS |
  3514. NWAY_LPAR_100T4_CAPS)) {
  3515. /* If our link partner advertises anything in addition to
  3516. * gigabit, we do not need to enable TBI compatibility.
  3517. */
  3518. if (hw->tbi_compatibility_on) {
  3519. /* If we previously were in the mode, turn it off. */
  3520. rctl = E1000_READ_REG(hw, RCTL);
  3521. rctl &= ~E1000_RCTL_SBP;
  3522. E1000_WRITE_REG(hw, RCTL, rctl);
  3523. hw->tbi_compatibility_on = false;
  3524. }
  3525. } else {
  3526. /* If TBI compatibility is was previously off, turn it on. For
  3527. * compatibility with a TBI link partner, we will store bad
  3528. * packets. Some frames have an additional byte on the end and
  3529. * will look like CRC errors to to the hardware.
  3530. */
  3531. if (!hw->tbi_compatibility_on) {
  3532. hw->tbi_compatibility_on = true;
  3533. rctl = E1000_READ_REG(hw, RCTL);
  3534. rctl |= E1000_RCTL_SBP;
  3535. E1000_WRITE_REG(hw, RCTL, rctl);
  3536. }
  3537. }
  3538. }
  3539. }
  3540. /* If we don't have link (auto-negotiation failed or link partner cannot
  3541. * auto-negotiate), the cable is plugged in (we have signal), and our
  3542. * link partner is not trying to auto-negotiate with us (we are receiving
  3543. * idles or data), we need to force link up. We also need to give
  3544. * auto-negotiation time to complete, in case the cable was just plugged
  3545. * in. The autoneg_failed flag does this.
  3546. */
  3547. else if ((hw->media_type == e1000_media_type_fiber) &&
  3548. (!(status & E1000_STATUS_LU)) &&
  3549. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3550. (!(rxcw & E1000_RXCW_C))) {
  3551. if (hw->autoneg_failed == 0) {
  3552. hw->autoneg_failed = 1;
  3553. return 0;
  3554. }
  3555. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3556. /* Disable auto-negotiation in the TXCW register */
  3557. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3558. /* Force link-up and also force full-duplex. */
  3559. ctrl = E1000_READ_REG(hw, CTRL);
  3560. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3561. E1000_WRITE_REG(hw, CTRL, ctrl);
  3562. /* Configure Flow Control after forcing link up. */
  3563. ret_val = e1000_config_fc_after_link_up(hw);
  3564. if (ret_val < 0) {
  3565. DEBUGOUT("Error configuring flow control\n");
  3566. return ret_val;
  3567. }
  3568. }
  3569. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3570. * auto-negotiation in the TXCW register and disable forced link in the
  3571. * Device Control register in an attempt to auto-negotiate with our link
  3572. * partner.
  3573. */
  3574. else if ((hw->media_type == e1000_media_type_fiber) &&
  3575. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3576. DEBUGOUT
  3577. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3578. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3579. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3580. }
  3581. return 0;
  3582. }
  3583. /******************************************************************************
  3584. * Configure the MAC-to-PHY interface for 10/100Mbps
  3585. *
  3586. * hw - Struct containing variables accessed by shared code
  3587. ******************************************************************************/
  3588. static int32_t
  3589. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3590. {
  3591. int32_t ret_val = E1000_SUCCESS;
  3592. uint32_t tipg;
  3593. uint16_t reg_data;
  3594. DEBUGFUNC();
  3595. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3596. ret_val = e1000_write_kmrn_reg(hw,
  3597. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3598. if (ret_val)
  3599. return ret_val;
  3600. /* Configure Transmit Inter-Packet Gap */
  3601. tipg = E1000_READ_REG(hw, TIPG);
  3602. tipg &= ~E1000_TIPG_IPGT_MASK;
  3603. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3604. E1000_WRITE_REG(hw, TIPG, tipg);
  3605. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3606. if (ret_val)
  3607. return ret_val;
  3608. if (duplex == HALF_DUPLEX)
  3609. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3610. else
  3611. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3612. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3613. return ret_val;
  3614. }
  3615. static int32_t
  3616. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3617. {
  3618. int32_t ret_val = E1000_SUCCESS;
  3619. uint16_t reg_data;
  3620. uint32_t tipg;
  3621. DEBUGFUNC();
  3622. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3623. ret_val = e1000_write_kmrn_reg(hw,
  3624. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3625. if (ret_val)
  3626. return ret_val;
  3627. /* Configure Transmit Inter-Packet Gap */
  3628. tipg = E1000_READ_REG(hw, TIPG);
  3629. tipg &= ~E1000_TIPG_IPGT_MASK;
  3630. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3631. E1000_WRITE_REG(hw, TIPG, tipg);
  3632. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3633. if (ret_val)
  3634. return ret_val;
  3635. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3636. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3637. return ret_val;
  3638. }
  3639. /******************************************************************************
  3640. * Detects the current speed and duplex settings of the hardware.
  3641. *
  3642. * hw - Struct containing variables accessed by shared code
  3643. * speed - Speed of the connection
  3644. * duplex - Duplex setting of the connection
  3645. *****************************************************************************/
  3646. static int
  3647. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3648. uint16_t *duplex)
  3649. {
  3650. uint32_t status;
  3651. int32_t ret_val;
  3652. uint16_t phy_data;
  3653. DEBUGFUNC();
  3654. if (hw->mac_type >= e1000_82543) {
  3655. status = E1000_READ_REG(hw, STATUS);
  3656. if (status & E1000_STATUS_SPEED_1000) {
  3657. *speed = SPEED_1000;
  3658. DEBUGOUT("1000 Mbs, ");
  3659. } else if (status & E1000_STATUS_SPEED_100) {
  3660. *speed = SPEED_100;
  3661. DEBUGOUT("100 Mbs, ");
  3662. } else {
  3663. *speed = SPEED_10;
  3664. DEBUGOUT("10 Mbs, ");
  3665. }
  3666. if (status & E1000_STATUS_FD) {
  3667. *duplex = FULL_DUPLEX;
  3668. DEBUGOUT("Full Duplex\r\n");
  3669. } else {
  3670. *duplex = HALF_DUPLEX;
  3671. DEBUGOUT(" Half Duplex\r\n");
  3672. }
  3673. } else {
  3674. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3675. *speed = SPEED_1000;
  3676. *duplex = FULL_DUPLEX;
  3677. }
  3678. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3679. * even if it is operating at half duplex. Here we set the duplex
  3680. * settings to match the duplex in the link partner's capabilities.
  3681. */
  3682. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3683. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3684. if (ret_val)
  3685. return ret_val;
  3686. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3687. *duplex = HALF_DUPLEX;
  3688. else {
  3689. ret_val = e1000_read_phy_reg(hw,
  3690. PHY_LP_ABILITY, &phy_data);
  3691. if (ret_val)
  3692. return ret_val;
  3693. if ((*speed == SPEED_100 &&
  3694. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3695. || (*speed == SPEED_10
  3696. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3697. *duplex = HALF_DUPLEX;
  3698. }
  3699. }
  3700. if ((hw->mac_type == e1000_80003es2lan) &&
  3701. (hw->media_type == e1000_media_type_copper)) {
  3702. if (*speed == SPEED_1000)
  3703. ret_val = e1000_configure_kmrn_for_1000(hw);
  3704. else
  3705. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3706. if (ret_val)
  3707. return ret_val;
  3708. }
  3709. return E1000_SUCCESS;
  3710. }
  3711. /******************************************************************************
  3712. * Blocks until autoneg completes or times out (~4.5 seconds)
  3713. *
  3714. * hw - Struct containing variables accessed by shared code
  3715. ******************************************************************************/
  3716. static int
  3717. e1000_wait_autoneg(struct e1000_hw *hw)
  3718. {
  3719. uint16_t i;
  3720. uint16_t phy_data;
  3721. DEBUGFUNC();
  3722. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3723. /* We will wait for autoneg to complete or timeout to expire. */
  3724. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3725. /* Read the MII Status Register and wait for Auto-Neg
  3726. * Complete bit to be set.
  3727. */
  3728. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3729. DEBUGOUT("PHY Read Error\n");
  3730. return -E1000_ERR_PHY;
  3731. }
  3732. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3733. DEBUGOUT("PHY Read Error\n");
  3734. return -E1000_ERR_PHY;
  3735. }
  3736. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3737. DEBUGOUT("Auto-Neg complete.\n");
  3738. return 0;
  3739. }
  3740. mdelay(100);
  3741. }
  3742. DEBUGOUT("Auto-Neg timedout.\n");
  3743. return -E1000_ERR_TIMEOUT;
  3744. }
  3745. /******************************************************************************
  3746. * Raises the Management Data Clock
  3747. *
  3748. * hw - Struct containing variables accessed by shared code
  3749. * ctrl - Device control register's current value
  3750. ******************************************************************************/
  3751. static void
  3752. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3753. {
  3754. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3755. * bit), and then delay 2 microseconds.
  3756. */
  3757. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3758. E1000_WRITE_FLUSH(hw);
  3759. udelay(2);
  3760. }
  3761. /******************************************************************************
  3762. * Lowers the Management Data Clock
  3763. *
  3764. * hw - Struct containing variables accessed by shared code
  3765. * ctrl - Device control register's current value
  3766. ******************************************************************************/
  3767. static void
  3768. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3769. {
  3770. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3771. * bit), and then delay 2 microseconds.
  3772. */
  3773. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3774. E1000_WRITE_FLUSH(hw);
  3775. udelay(2);
  3776. }
  3777. /******************************************************************************
  3778. * Shifts data bits out to the PHY
  3779. *
  3780. * hw - Struct containing variables accessed by shared code
  3781. * data - Data to send out to the PHY
  3782. * count - Number of bits to shift out
  3783. *
  3784. * Bits are shifted out in MSB to LSB order.
  3785. ******************************************************************************/
  3786. static void
  3787. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3788. {
  3789. uint32_t ctrl;
  3790. uint32_t mask;
  3791. /* We need to shift "count" number of bits out to the PHY. So, the value
  3792. * in the "data" parameter will be shifted out to the PHY one bit at a
  3793. * time. In order to do this, "data" must be broken down into bits.
  3794. */
  3795. mask = 0x01;
  3796. mask <<= (count - 1);
  3797. ctrl = E1000_READ_REG(hw, CTRL);
  3798. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3799. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3800. while (mask) {
  3801. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3802. * then raising and lowering the Management Data Clock. A "0" is
  3803. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3804. * raising and lowering the clock.
  3805. */
  3806. if (data & mask)
  3807. ctrl |= E1000_CTRL_MDIO;
  3808. else
  3809. ctrl &= ~E1000_CTRL_MDIO;
  3810. E1000_WRITE_REG(hw, CTRL, ctrl);
  3811. E1000_WRITE_FLUSH(hw);
  3812. udelay(2);
  3813. e1000_raise_mdi_clk(hw, &ctrl);
  3814. e1000_lower_mdi_clk(hw, &ctrl);
  3815. mask = mask >> 1;
  3816. }
  3817. }
  3818. /******************************************************************************
  3819. * Shifts data bits in from the PHY
  3820. *
  3821. * hw - Struct containing variables accessed by shared code
  3822. *
  3823. * Bits are shifted in in MSB to LSB order.
  3824. ******************************************************************************/
  3825. static uint16_t
  3826. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3827. {
  3828. uint32_t ctrl;
  3829. uint16_t data = 0;
  3830. uint8_t i;
  3831. /* In order to read a register from the PHY, we need to shift in a total
  3832. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3833. * to avoid contention on the MDIO pin when a read operation is performed.
  3834. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3835. * by raising the input to the Management Data Clock (setting the MDC bit),
  3836. * and then reading the value of the MDIO bit.
  3837. */
  3838. ctrl = E1000_READ_REG(hw, CTRL);
  3839. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3840. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3841. ctrl &= ~E1000_CTRL_MDIO;
  3842. E1000_WRITE_REG(hw, CTRL, ctrl);
  3843. E1000_WRITE_FLUSH(hw);
  3844. /* Raise and Lower the clock before reading in the data. This accounts for
  3845. * the turnaround bits. The first clock occurred when we clocked out the
  3846. * last bit of the Register Address.
  3847. */
  3848. e1000_raise_mdi_clk(hw, &ctrl);
  3849. e1000_lower_mdi_clk(hw, &ctrl);
  3850. for (data = 0, i = 0; i < 16; i++) {
  3851. data = data << 1;
  3852. e1000_raise_mdi_clk(hw, &ctrl);
  3853. ctrl = E1000_READ_REG(hw, CTRL);
  3854. /* Check to see if we shifted in a "1". */
  3855. if (ctrl & E1000_CTRL_MDIO)
  3856. data |= 1;
  3857. e1000_lower_mdi_clk(hw, &ctrl);
  3858. }
  3859. e1000_raise_mdi_clk(hw, &ctrl);
  3860. e1000_lower_mdi_clk(hw, &ctrl);
  3861. return data;
  3862. }
  3863. /*****************************************************************************
  3864. * Reads the value from a PHY register
  3865. *
  3866. * hw - Struct containing variables accessed by shared code
  3867. * reg_addr - address of the PHY register to read
  3868. ******************************************************************************/
  3869. static int
  3870. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3871. {
  3872. uint32_t i;
  3873. uint32_t mdic = 0;
  3874. const uint32_t phy_addr = 1;
  3875. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3876. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3877. return -E1000_ERR_PARAM;
  3878. }
  3879. if (hw->mac_type > e1000_82543) {
  3880. /* Set up Op-code, Phy Address, and register address in the MDI
  3881. * Control register. The MAC will take care of interfacing with the
  3882. * PHY to retrieve the desired data.
  3883. */
  3884. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3885. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3886. (E1000_MDIC_OP_READ));
  3887. E1000_WRITE_REG(hw, MDIC, mdic);
  3888. /* Poll the ready bit to see if the MDI read completed */
  3889. for (i = 0; i < 64; i++) {
  3890. udelay(10);
  3891. mdic = E1000_READ_REG(hw, MDIC);
  3892. if (mdic & E1000_MDIC_READY)
  3893. break;
  3894. }
  3895. if (!(mdic & E1000_MDIC_READY)) {
  3896. DEBUGOUT("MDI Read did not complete\n");
  3897. return -E1000_ERR_PHY;
  3898. }
  3899. if (mdic & E1000_MDIC_ERROR) {
  3900. DEBUGOUT("MDI Error\n");
  3901. return -E1000_ERR_PHY;
  3902. }
  3903. *phy_data = (uint16_t) mdic;
  3904. } else {
  3905. /* We must first send a preamble through the MDIO pin to signal the
  3906. * beginning of an MII instruction. This is done by sending 32
  3907. * consecutive "1" bits.
  3908. */
  3909. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3910. /* Now combine the next few fields that are required for a read
  3911. * operation. We use this method instead of calling the
  3912. * e1000_shift_out_mdi_bits routine five different times. The format of
  3913. * a MII read instruction consists of a shift out of 14 bits and is
  3914. * defined as follows:
  3915. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3916. * followed by a shift in of 18 bits. This first two bits shifted in
  3917. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3918. * READ operation is performed. These two bits are thrown away
  3919. * followed by a shift in of 16 bits which contains the desired data.
  3920. */
  3921. mdic = ((reg_addr) | (phy_addr << 5) |
  3922. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3923. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3924. /* Now that we've shifted out the read command to the MII, we need to
  3925. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3926. * register address.
  3927. */
  3928. *phy_data = e1000_shift_in_mdi_bits(hw);
  3929. }
  3930. return 0;
  3931. }
  3932. /******************************************************************************
  3933. * Writes a value to a PHY register
  3934. *
  3935. * hw - Struct containing variables accessed by shared code
  3936. * reg_addr - address of the PHY register to write
  3937. * data - data to write to the PHY
  3938. ******************************************************************************/
  3939. static int
  3940. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3941. {
  3942. uint32_t i;
  3943. uint32_t mdic = 0;
  3944. const uint32_t phy_addr = 1;
  3945. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3946. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3947. return -E1000_ERR_PARAM;
  3948. }
  3949. if (hw->mac_type > e1000_82543) {
  3950. /* Set up Op-code, Phy Address, register address, and data intended
  3951. * for the PHY register in the MDI Control register. The MAC will take
  3952. * care of interfacing with the PHY to send the desired data.
  3953. */
  3954. mdic = (((uint32_t) phy_data) |
  3955. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3956. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3957. (E1000_MDIC_OP_WRITE));
  3958. E1000_WRITE_REG(hw, MDIC, mdic);
  3959. /* Poll the ready bit to see if the MDI read completed */
  3960. for (i = 0; i < 64; i++) {
  3961. udelay(10);
  3962. mdic = E1000_READ_REG(hw, MDIC);
  3963. if (mdic & E1000_MDIC_READY)
  3964. break;
  3965. }
  3966. if (!(mdic & E1000_MDIC_READY)) {
  3967. DEBUGOUT("MDI Write did not complete\n");
  3968. return -E1000_ERR_PHY;
  3969. }
  3970. } else {
  3971. /* We'll need to use the SW defined pins to shift the write command
  3972. * out to the PHY. We first send a preamble to the PHY to signal the
  3973. * beginning of the MII instruction. This is done by sending 32
  3974. * consecutive "1" bits.
  3975. */
  3976. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3977. /* Now combine the remaining required fields that will indicate a
  3978. * write operation. We use this method instead of calling the
  3979. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3980. * format of a MII write instruction is as follows:
  3981. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3982. */
  3983. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3984. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3985. mdic <<= 16;
  3986. mdic |= (uint32_t) phy_data;
  3987. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3988. }
  3989. return 0;
  3990. }
  3991. /******************************************************************************
  3992. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3993. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3994. * the caller to figure out how to deal with it.
  3995. *
  3996. * hw - Struct containing variables accessed by shared code
  3997. *
  3998. * returns: - E1000_BLK_PHY_RESET
  3999. * E1000_SUCCESS
  4000. *
  4001. *****************************************************************************/
  4002. int32_t
  4003. e1000_check_phy_reset_block(struct e1000_hw *hw)
  4004. {
  4005. uint32_t manc = 0;
  4006. uint32_t fwsm = 0;
  4007. if (hw->mac_type == e1000_ich8lan) {
  4008. fwsm = E1000_READ_REG(hw, FWSM);
  4009. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  4010. : E1000_BLK_PHY_RESET;
  4011. }
  4012. if (hw->mac_type > e1000_82547_rev_2)
  4013. manc = E1000_READ_REG(hw, MANC);
  4014. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  4015. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  4016. }
  4017. /***************************************************************************
  4018. * Checks if the PHY configuration is done
  4019. *
  4020. * hw: Struct containing variables accessed by shared code
  4021. *
  4022. * returns: - E1000_ERR_RESET if fail to reset MAC
  4023. * E1000_SUCCESS at any other case.
  4024. *
  4025. ***************************************************************************/
  4026. static int32_t
  4027. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  4028. {
  4029. int32_t timeout = PHY_CFG_TIMEOUT;
  4030. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  4031. DEBUGFUNC();
  4032. switch (hw->mac_type) {
  4033. default:
  4034. mdelay(10);
  4035. break;
  4036. case e1000_80003es2lan:
  4037. /* Separate *_CFG_DONE_* bit for each port */
  4038. if (e1000_is_second_port(hw))
  4039. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  4040. /* Fall Through */
  4041. case e1000_82571:
  4042. case e1000_82572:
  4043. case e1000_igb:
  4044. while (timeout) {
  4045. if (hw->mac_type == e1000_igb) {
  4046. if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
  4047. break;
  4048. } else {
  4049. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  4050. break;
  4051. }
  4052. mdelay(1);
  4053. timeout--;
  4054. }
  4055. if (!timeout) {
  4056. DEBUGOUT("MNG configuration cycle has not "
  4057. "completed.\n");
  4058. return -E1000_ERR_RESET;
  4059. }
  4060. break;
  4061. }
  4062. return E1000_SUCCESS;
  4063. }
  4064. /******************************************************************************
  4065. * Returns the PHY to the power-on reset state
  4066. *
  4067. * hw - Struct containing variables accessed by shared code
  4068. ******************************************************************************/
  4069. int32_t
  4070. e1000_phy_hw_reset(struct e1000_hw *hw)
  4071. {
  4072. uint16_t swfw = E1000_SWFW_PHY0_SM;
  4073. uint32_t ctrl, ctrl_ext;
  4074. uint32_t led_ctrl;
  4075. int32_t ret_val;
  4076. DEBUGFUNC();
  4077. /* In the case of the phy reset being blocked, it's not an error, we
  4078. * simply return success without performing the reset. */
  4079. ret_val = e1000_check_phy_reset_block(hw);
  4080. if (ret_val)
  4081. return E1000_SUCCESS;
  4082. DEBUGOUT("Resetting Phy...\n");
  4083. if (hw->mac_type > e1000_82543) {
  4084. if (e1000_is_second_port(hw))
  4085. swfw = E1000_SWFW_PHY1_SM;
  4086. if (e1000_swfw_sync_acquire(hw, swfw)) {
  4087. DEBUGOUT("Unable to acquire swfw sync\n");
  4088. return -E1000_ERR_SWFW_SYNC;
  4089. }
  4090. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  4091. * bit. Then, take it out of reset.
  4092. */
  4093. ctrl = E1000_READ_REG(hw, CTRL);
  4094. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  4095. E1000_WRITE_FLUSH(hw);
  4096. if (hw->mac_type < e1000_82571)
  4097. udelay(10);
  4098. else
  4099. udelay(100);
  4100. E1000_WRITE_REG(hw, CTRL, ctrl);
  4101. E1000_WRITE_FLUSH(hw);
  4102. if (hw->mac_type >= e1000_82571)
  4103. mdelay(10);
  4104. } else {
  4105. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  4106. * bit to put the PHY into reset. Then, take it out of reset.
  4107. */
  4108. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4109. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  4110. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  4111. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4112. E1000_WRITE_FLUSH(hw);
  4113. mdelay(10);
  4114. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  4115. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4116. E1000_WRITE_FLUSH(hw);
  4117. }
  4118. udelay(150);
  4119. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4120. /* Configure activity LED after PHY reset */
  4121. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4122. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4123. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4124. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4125. }
  4126. e1000_swfw_sync_release(hw, swfw);
  4127. /* Wait for FW to finish PHY configuration. */
  4128. ret_val = e1000_get_phy_cfg_done(hw);
  4129. if (ret_val != E1000_SUCCESS)
  4130. return ret_val;
  4131. return ret_val;
  4132. }
  4133. /******************************************************************************
  4134. * IGP phy init script - initializes the GbE PHY
  4135. *
  4136. * hw - Struct containing variables accessed by shared code
  4137. *****************************************************************************/
  4138. static void
  4139. e1000_phy_init_script(struct e1000_hw *hw)
  4140. {
  4141. uint32_t ret_val;
  4142. uint16_t phy_saved_data;
  4143. DEBUGFUNC();
  4144. if (hw->phy_init_script) {
  4145. mdelay(20);
  4146. /* Save off the current value of register 0x2F5B to be
  4147. * restored at the end of this routine. */
  4148. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  4149. /* Disabled the PHY transmitter */
  4150. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  4151. mdelay(20);
  4152. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  4153. mdelay(5);
  4154. switch (hw->mac_type) {
  4155. case e1000_82541:
  4156. case e1000_82547:
  4157. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  4158. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  4159. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  4160. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  4161. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  4162. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  4163. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  4164. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  4165. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  4166. break;
  4167. case e1000_82541_rev_2:
  4168. case e1000_82547_rev_2:
  4169. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  4170. break;
  4171. default:
  4172. break;
  4173. }
  4174. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  4175. mdelay(20);
  4176. /* Now enable the transmitter */
  4177. if (!ret_val)
  4178. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  4179. if (hw->mac_type == e1000_82547) {
  4180. uint16_t fused, fine, coarse;
  4181. /* Move to analog registers page */
  4182. e1000_read_phy_reg(hw,
  4183. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  4184. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  4185. e1000_read_phy_reg(hw,
  4186. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  4187. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  4188. coarse = fused
  4189. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  4190. if (coarse >
  4191. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  4192. coarse -=
  4193. IGP01E1000_ANALOG_FUSE_COARSE_10;
  4194. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  4195. } else if (coarse
  4196. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  4197. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  4198. fused = (fused
  4199. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  4200. (fine
  4201. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  4202. (coarse
  4203. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  4204. e1000_write_phy_reg(hw,
  4205. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  4206. e1000_write_phy_reg(hw,
  4207. IGP01E1000_ANALOG_FUSE_BYPASS,
  4208. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  4209. }
  4210. }
  4211. }
  4212. }
  4213. /******************************************************************************
  4214. * Resets the PHY
  4215. *
  4216. * hw - Struct containing variables accessed by shared code
  4217. *
  4218. * Sets bit 15 of the MII Control register
  4219. ******************************************************************************/
  4220. int32_t
  4221. e1000_phy_reset(struct e1000_hw *hw)
  4222. {
  4223. int32_t ret_val;
  4224. uint16_t phy_data;
  4225. DEBUGFUNC();
  4226. /* In the case of the phy reset being blocked, it's not an error, we
  4227. * simply return success without performing the reset. */
  4228. ret_val = e1000_check_phy_reset_block(hw);
  4229. if (ret_val)
  4230. return E1000_SUCCESS;
  4231. switch (hw->phy_type) {
  4232. case e1000_phy_igp:
  4233. case e1000_phy_igp_2:
  4234. case e1000_phy_igp_3:
  4235. case e1000_phy_ife:
  4236. case e1000_phy_igb:
  4237. ret_val = e1000_phy_hw_reset(hw);
  4238. if (ret_val)
  4239. return ret_val;
  4240. break;
  4241. default:
  4242. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  4243. if (ret_val)
  4244. return ret_val;
  4245. phy_data |= MII_CR_RESET;
  4246. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  4247. if (ret_val)
  4248. return ret_val;
  4249. udelay(1);
  4250. break;
  4251. }
  4252. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  4253. e1000_phy_init_script(hw);
  4254. return E1000_SUCCESS;
  4255. }
  4256. static int e1000_set_phy_type (struct e1000_hw *hw)
  4257. {
  4258. DEBUGFUNC ();
  4259. if (hw->mac_type == e1000_undefined)
  4260. return -E1000_ERR_PHY_TYPE;
  4261. switch (hw->phy_id) {
  4262. case M88E1000_E_PHY_ID:
  4263. case M88E1000_I_PHY_ID:
  4264. case M88E1011_I_PHY_ID:
  4265. case M88E1111_I_PHY_ID:
  4266. hw->phy_type = e1000_phy_m88;
  4267. break;
  4268. case IGP01E1000_I_PHY_ID:
  4269. if (hw->mac_type == e1000_82541 ||
  4270. hw->mac_type == e1000_82541_rev_2 ||
  4271. hw->mac_type == e1000_82547 ||
  4272. hw->mac_type == e1000_82547_rev_2) {
  4273. hw->phy_type = e1000_phy_igp;
  4274. break;
  4275. }
  4276. case IGP03E1000_E_PHY_ID:
  4277. hw->phy_type = e1000_phy_igp_3;
  4278. break;
  4279. case IFE_E_PHY_ID:
  4280. case IFE_PLUS_E_PHY_ID:
  4281. case IFE_C_E_PHY_ID:
  4282. hw->phy_type = e1000_phy_ife;
  4283. break;
  4284. case GG82563_E_PHY_ID:
  4285. if (hw->mac_type == e1000_80003es2lan) {
  4286. hw->phy_type = e1000_phy_gg82563;
  4287. break;
  4288. }
  4289. case BME1000_E_PHY_ID:
  4290. hw->phy_type = e1000_phy_bm;
  4291. break;
  4292. case I210_I_PHY_ID:
  4293. hw->phy_type = e1000_phy_igb;
  4294. break;
  4295. /* Fall Through */
  4296. default:
  4297. /* Should never have loaded on this device */
  4298. hw->phy_type = e1000_phy_undefined;
  4299. return -E1000_ERR_PHY_TYPE;
  4300. }
  4301. return E1000_SUCCESS;
  4302. }
  4303. /******************************************************************************
  4304. * Probes the expected PHY address for known PHY IDs
  4305. *
  4306. * hw - Struct containing variables accessed by shared code
  4307. ******************************************************************************/
  4308. static int32_t
  4309. e1000_detect_gig_phy(struct e1000_hw *hw)
  4310. {
  4311. int32_t phy_init_status, ret_val;
  4312. uint16_t phy_id_high, phy_id_low;
  4313. bool match = false;
  4314. DEBUGFUNC();
  4315. /* The 82571 firmware may still be configuring the PHY. In this
  4316. * case, we cannot access the PHY until the configuration is done. So
  4317. * we explicitly set the PHY values. */
  4318. if (hw->mac_type == e1000_82571 ||
  4319. hw->mac_type == e1000_82572) {
  4320. hw->phy_id = IGP01E1000_I_PHY_ID;
  4321. hw->phy_type = e1000_phy_igp_2;
  4322. return E1000_SUCCESS;
  4323. }
  4324. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4325. * work- around that forces PHY page 0 to be set or the reads fail.
  4326. * The rest of the code in this routine uses e1000_read_phy_reg to
  4327. * read the PHY ID. So for ESB-2 we need to have this set so our
  4328. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4329. * the routines below will figure this out as well. */
  4330. if (hw->mac_type == e1000_80003es2lan)
  4331. hw->phy_type = e1000_phy_gg82563;
  4332. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4333. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4334. if (ret_val)
  4335. return ret_val;
  4336. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4337. udelay(20);
  4338. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4339. if (ret_val)
  4340. return ret_val;
  4341. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4342. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4343. switch (hw->mac_type) {
  4344. case e1000_82543:
  4345. if (hw->phy_id == M88E1000_E_PHY_ID)
  4346. match = true;
  4347. break;
  4348. case e1000_82544:
  4349. if (hw->phy_id == M88E1000_I_PHY_ID)
  4350. match = true;
  4351. break;
  4352. case e1000_82540:
  4353. case e1000_82545:
  4354. case e1000_82545_rev_3:
  4355. case e1000_82546:
  4356. case e1000_82546_rev_3:
  4357. if (hw->phy_id == M88E1011_I_PHY_ID)
  4358. match = true;
  4359. break;
  4360. case e1000_82541:
  4361. case e1000_82541_rev_2:
  4362. case e1000_82547:
  4363. case e1000_82547_rev_2:
  4364. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4365. match = true;
  4366. break;
  4367. case e1000_82573:
  4368. if (hw->phy_id == M88E1111_I_PHY_ID)
  4369. match = true;
  4370. break;
  4371. case e1000_82574:
  4372. if (hw->phy_id == BME1000_E_PHY_ID)
  4373. match = true;
  4374. break;
  4375. case e1000_80003es2lan:
  4376. if (hw->phy_id == GG82563_E_PHY_ID)
  4377. match = true;
  4378. break;
  4379. case e1000_ich8lan:
  4380. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4381. match = true;
  4382. if (hw->phy_id == IFE_E_PHY_ID)
  4383. match = true;
  4384. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4385. match = true;
  4386. if (hw->phy_id == IFE_C_E_PHY_ID)
  4387. match = true;
  4388. break;
  4389. case e1000_igb:
  4390. if (hw->phy_id == I210_I_PHY_ID)
  4391. match = true;
  4392. break;
  4393. default:
  4394. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4395. return -E1000_ERR_CONFIG;
  4396. }
  4397. phy_init_status = e1000_set_phy_type(hw);
  4398. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4399. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4400. return 0;
  4401. }
  4402. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4403. return -E1000_ERR_PHY;
  4404. }
  4405. /*****************************************************************************
  4406. * Set media type and TBI compatibility.
  4407. *
  4408. * hw - Struct containing variables accessed by shared code
  4409. * **************************************************************************/
  4410. void
  4411. e1000_set_media_type(struct e1000_hw *hw)
  4412. {
  4413. uint32_t status;
  4414. DEBUGFUNC();
  4415. if (hw->mac_type != e1000_82543) {
  4416. /* tbi_compatibility is only valid on 82543 */
  4417. hw->tbi_compatibility_en = false;
  4418. }
  4419. switch (hw->device_id) {
  4420. case E1000_DEV_ID_82545GM_SERDES:
  4421. case E1000_DEV_ID_82546GB_SERDES:
  4422. case E1000_DEV_ID_82571EB_SERDES:
  4423. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4424. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4425. case E1000_DEV_ID_82572EI_SERDES:
  4426. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4427. hw->media_type = e1000_media_type_internal_serdes;
  4428. break;
  4429. default:
  4430. switch (hw->mac_type) {
  4431. case e1000_82542_rev2_0:
  4432. case e1000_82542_rev2_1:
  4433. hw->media_type = e1000_media_type_fiber;
  4434. break;
  4435. case e1000_ich8lan:
  4436. case e1000_82573:
  4437. case e1000_82574:
  4438. case e1000_igb:
  4439. /* The STATUS_TBIMODE bit is reserved or reused
  4440. * for the this device.
  4441. */
  4442. hw->media_type = e1000_media_type_copper;
  4443. break;
  4444. default:
  4445. status = E1000_READ_REG(hw, STATUS);
  4446. if (status & E1000_STATUS_TBIMODE) {
  4447. hw->media_type = e1000_media_type_fiber;
  4448. /* tbi_compatibility not valid on fiber */
  4449. hw->tbi_compatibility_en = false;
  4450. } else {
  4451. hw->media_type = e1000_media_type_copper;
  4452. }
  4453. break;
  4454. }
  4455. }
  4456. }
  4457. /**
  4458. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4459. *
  4460. * e1000_sw_init initializes the Adapter private data structure.
  4461. * Fields are initialized based on PCI device information and
  4462. * OS network device settings (MTU size).
  4463. **/
  4464. static int
  4465. e1000_sw_init(struct e1000_hw *hw)
  4466. {
  4467. int result;
  4468. /* PCI config space info */
  4469. #ifdef CONFIG_DM_ETH
  4470. dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4471. dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4472. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4473. &hw->subsystem_vendor_id);
  4474. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4475. dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4476. dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4477. #else
  4478. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4479. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4480. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4481. &hw->subsystem_vendor_id);
  4482. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4483. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4484. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4485. #endif
  4486. /* identify the MAC */
  4487. result = e1000_set_mac_type(hw);
  4488. if (result) {
  4489. E1000_ERR(hw, "Unknown MAC Type\n");
  4490. return result;
  4491. }
  4492. switch (hw->mac_type) {
  4493. default:
  4494. break;
  4495. case e1000_82541:
  4496. case e1000_82547:
  4497. case e1000_82541_rev_2:
  4498. case e1000_82547_rev_2:
  4499. hw->phy_init_script = 1;
  4500. break;
  4501. }
  4502. /* flow control settings */
  4503. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4504. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4505. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4506. hw->fc_send_xon = 1;
  4507. /* Media type - copper or fiber */
  4508. hw->tbi_compatibility_en = true;
  4509. e1000_set_media_type(hw);
  4510. if (hw->mac_type >= e1000_82543) {
  4511. uint32_t status = E1000_READ_REG(hw, STATUS);
  4512. if (status & E1000_STATUS_TBIMODE) {
  4513. DEBUGOUT("fiber interface\n");
  4514. hw->media_type = e1000_media_type_fiber;
  4515. } else {
  4516. DEBUGOUT("copper interface\n");
  4517. hw->media_type = e1000_media_type_copper;
  4518. }
  4519. } else {
  4520. hw->media_type = e1000_media_type_fiber;
  4521. }
  4522. hw->wait_autoneg_complete = true;
  4523. if (hw->mac_type < e1000_82543)
  4524. hw->report_tx_early = 0;
  4525. else
  4526. hw->report_tx_early = 1;
  4527. return E1000_SUCCESS;
  4528. }
  4529. void
  4530. fill_rx(struct e1000_hw *hw)
  4531. {
  4532. struct e1000_rx_desc *rd;
  4533. unsigned long flush_start, flush_end;
  4534. rx_last = rx_tail;
  4535. rd = rx_base + rx_tail;
  4536. rx_tail = (rx_tail + 1) % 8;
  4537. memset(rd, 0, 16);
  4538. rd->buffer_addr = cpu_to_le64((unsigned long)packet);
  4539. /*
  4540. * Make sure there are no stale data in WB over this area, which
  4541. * might get written into the memory while the e1000 also writes
  4542. * into the same memory area.
  4543. */
  4544. invalidate_dcache_range((unsigned long)packet,
  4545. (unsigned long)packet + 4096);
  4546. /* Dump the DMA descriptor into RAM. */
  4547. flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4548. flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4549. flush_dcache_range(flush_start, flush_end);
  4550. E1000_WRITE_REG(hw, RDT, rx_tail);
  4551. }
  4552. /**
  4553. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4554. * @adapter: board private structure
  4555. *
  4556. * Configure the Tx unit of the MAC after a reset.
  4557. **/
  4558. static void
  4559. e1000_configure_tx(struct e1000_hw *hw)
  4560. {
  4561. unsigned long tctl;
  4562. unsigned long tipg, tarc;
  4563. uint32_t ipgr1, ipgr2;
  4564. E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
  4565. E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
  4566. E1000_WRITE_REG(hw, TDLEN, 128);
  4567. /* Setup the HW Tx Head and Tail descriptor pointers */
  4568. E1000_WRITE_REG(hw, TDH, 0);
  4569. E1000_WRITE_REG(hw, TDT, 0);
  4570. tx_tail = 0;
  4571. /* Set the default values for the Tx Inter Packet Gap timer */
  4572. if (hw->mac_type <= e1000_82547_rev_2 &&
  4573. (hw->media_type == e1000_media_type_fiber ||
  4574. hw->media_type == e1000_media_type_internal_serdes))
  4575. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4576. else
  4577. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4578. /* Set the default values for the Tx Inter Packet Gap timer */
  4579. switch (hw->mac_type) {
  4580. case e1000_82542_rev2_0:
  4581. case e1000_82542_rev2_1:
  4582. tipg = DEFAULT_82542_TIPG_IPGT;
  4583. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4584. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4585. break;
  4586. case e1000_80003es2lan:
  4587. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4588. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4589. break;
  4590. default:
  4591. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4592. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4593. break;
  4594. }
  4595. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4596. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4597. E1000_WRITE_REG(hw, TIPG, tipg);
  4598. /* Program the Transmit Control Register */
  4599. tctl = E1000_READ_REG(hw, TCTL);
  4600. tctl &= ~E1000_TCTL_CT;
  4601. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4602. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4603. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4604. tarc = E1000_READ_REG(hw, TARC0);
  4605. /* set the speed mode bit, we'll clear it if we're not at
  4606. * gigabit link later */
  4607. /* git bit can be set to 1*/
  4608. } else if (hw->mac_type == e1000_80003es2lan) {
  4609. tarc = E1000_READ_REG(hw, TARC0);
  4610. tarc |= 1;
  4611. E1000_WRITE_REG(hw, TARC0, tarc);
  4612. tarc = E1000_READ_REG(hw, TARC1);
  4613. tarc |= 1;
  4614. E1000_WRITE_REG(hw, TARC1, tarc);
  4615. }
  4616. e1000_config_collision_dist(hw);
  4617. /* Setup Transmit Descriptor Settings for eop descriptor */
  4618. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4619. /* Need to set up RS bit */
  4620. if (hw->mac_type < e1000_82543)
  4621. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4622. else
  4623. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4624. if (hw->mac_type == e1000_igb) {
  4625. E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
  4626. uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  4627. reg_txdctl |= 1 << 25;
  4628. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  4629. mdelay(20);
  4630. }
  4631. E1000_WRITE_REG(hw, TCTL, tctl);
  4632. }
  4633. /**
  4634. * e1000_setup_rctl - configure the receive control register
  4635. * @adapter: Board private structure
  4636. **/
  4637. static void
  4638. e1000_setup_rctl(struct e1000_hw *hw)
  4639. {
  4640. uint32_t rctl;
  4641. rctl = E1000_READ_REG(hw, RCTL);
  4642. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4643. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4644. | E1000_RCTL_RDMTS_HALF; /* |
  4645. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4646. if (hw->tbi_compatibility_on == 1)
  4647. rctl |= E1000_RCTL_SBP;
  4648. else
  4649. rctl &= ~E1000_RCTL_SBP;
  4650. rctl &= ~(E1000_RCTL_SZ_4096);
  4651. rctl |= E1000_RCTL_SZ_2048;
  4652. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4653. E1000_WRITE_REG(hw, RCTL, rctl);
  4654. }
  4655. /**
  4656. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4657. * @adapter: board private structure
  4658. *
  4659. * Configure the Rx unit of the MAC after a reset.
  4660. **/
  4661. static void
  4662. e1000_configure_rx(struct e1000_hw *hw)
  4663. {
  4664. unsigned long rctl, ctrl_ext;
  4665. rx_tail = 0;
  4666. /* make sure receives are disabled while setting up the descriptors */
  4667. rctl = E1000_READ_REG(hw, RCTL);
  4668. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4669. if (hw->mac_type >= e1000_82540) {
  4670. /* Set the interrupt throttling rate. Value is calculated
  4671. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4672. #define MAX_INTS_PER_SEC 8000
  4673. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4674. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4675. }
  4676. if (hw->mac_type >= e1000_82571) {
  4677. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4678. /* Reset delay timers after every interrupt */
  4679. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4680. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4681. E1000_WRITE_FLUSH(hw);
  4682. }
  4683. /* Setup the Base and Length of the Rx Descriptor Ring */
  4684. E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
  4685. E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
  4686. E1000_WRITE_REG(hw, RDLEN, 128);
  4687. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4688. E1000_WRITE_REG(hw, RDH, 0);
  4689. E1000_WRITE_REG(hw, RDT, 0);
  4690. /* Enable Receives */
  4691. if (hw->mac_type == e1000_igb) {
  4692. uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
  4693. reg_rxdctl |= 1 << 25;
  4694. E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
  4695. mdelay(20);
  4696. }
  4697. E1000_WRITE_REG(hw, RCTL, rctl);
  4698. fill_rx(hw);
  4699. }
  4700. /**************************************************************************
  4701. POLL - Wait for a frame
  4702. ***************************************************************************/
  4703. static int
  4704. _e1000_poll(struct e1000_hw *hw)
  4705. {
  4706. struct e1000_rx_desc *rd;
  4707. unsigned long inval_start, inval_end;
  4708. uint32_t len;
  4709. /* return true if there's an ethernet packet ready to read */
  4710. rd = rx_base + rx_last;
  4711. /* Re-load the descriptor from RAM. */
  4712. inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4713. inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4714. invalidate_dcache_range(inval_start, inval_end);
  4715. if (!(rd->status & E1000_RXD_STAT_DD))
  4716. return 0;
  4717. /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
  4718. /* Packet received, make sure the data are re-loaded from RAM. */
  4719. len = le16_to_cpu(rd->length);
  4720. invalidate_dcache_range((unsigned long)packet,
  4721. (unsigned long)packet +
  4722. roundup(len, ARCH_DMA_MINALIGN));
  4723. return len;
  4724. }
  4725. static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
  4726. {
  4727. void *nv_packet = (void *)txpacket;
  4728. struct e1000_tx_desc *txp;
  4729. int i = 0;
  4730. unsigned long flush_start, flush_end;
  4731. txp = tx_base + tx_tail;
  4732. tx_tail = (tx_tail + 1) % 8;
  4733. txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
  4734. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4735. txp->upper.data = 0;
  4736. /* Dump the packet into RAM so e1000 can pick them. */
  4737. flush_dcache_range((unsigned long)nv_packet,
  4738. (unsigned long)nv_packet +
  4739. roundup(length, ARCH_DMA_MINALIGN));
  4740. /* Dump the descriptor into RAM as well. */
  4741. flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
  4742. flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
  4743. flush_dcache_range(flush_start, flush_end);
  4744. E1000_WRITE_REG(hw, TDT, tx_tail);
  4745. E1000_WRITE_FLUSH(hw);
  4746. while (1) {
  4747. invalidate_dcache_range(flush_start, flush_end);
  4748. if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
  4749. break;
  4750. if (i++ > TOUT_LOOP) {
  4751. DEBUGOUT("e1000: tx timeout\n");
  4752. return 0;
  4753. }
  4754. udelay(10); /* give the nic a chance to write to the register */
  4755. }
  4756. return 1;
  4757. }
  4758. static void
  4759. _e1000_disable(struct e1000_hw *hw)
  4760. {
  4761. /* Turn off the ethernet interface */
  4762. E1000_WRITE_REG(hw, RCTL, 0);
  4763. E1000_WRITE_REG(hw, TCTL, 0);
  4764. /* Clear the transmit ring */
  4765. E1000_WRITE_REG(hw, TDH, 0);
  4766. E1000_WRITE_REG(hw, TDT, 0);
  4767. /* Clear the receive ring */
  4768. E1000_WRITE_REG(hw, RDH, 0);
  4769. E1000_WRITE_REG(hw, RDT, 0);
  4770. mdelay(10);
  4771. }
  4772. /*reset function*/
  4773. static inline int
  4774. e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
  4775. {
  4776. e1000_reset_hw(hw);
  4777. if (hw->mac_type >= e1000_82544)
  4778. E1000_WRITE_REG(hw, WUC, 0);
  4779. return e1000_init_hw(hw, enetaddr);
  4780. }
  4781. static int
  4782. _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
  4783. {
  4784. int ret_val = 0;
  4785. ret_val = e1000_reset(hw, enetaddr);
  4786. if (ret_val < 0) {
  4787. if ((ret_val == -E1000_ERR_NOLINK) ||
  4788. (ret_val == -E1000_ERR_TIMEOUT)) {
  4789. E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
  4790. } else {
  4791. E1000_ERR(hw, "Hardware Initialization Failed\n");
  4792. }
  4793. return ret_val;
  4794. }
  4795. e1000_configure_tx(hw);
  4796. e1000_setup_rctl(hw);
  4797. e1000_configure_rx(hw);
  4798. return 0;
  4799. }
  4800. /******************************************************************************
  4801. * Gets the current PCI bus type of hardware
  4802. *
  4803. * hw - Struct containing variables accessed by shared code
  4804. *****************************************************************************/
  4805. void e1000_get_bus_type(struct e1000_hw *hw)
  4806. {
  4807. uint32_t status;
  4808. switch (hw->mac_type) {
  4809. case e1000_82542_rev2_0:
  4810. case e1000_82542_rev2_1:
  4811. hw->bus_type = e1000_bus_type_pci;
  4812. break;
  4813. case e1000_82571:
  4814. case e1000_82572:
  4815. case e1000_82573:
  4816. case e1000_82574:
  4817. case e1000_80003es2lan:
  4818. case e1000_ich8lan:
  4819. case e1000_igb:
  4820. hw->bus_type = e1000_bus_type_pci_express;
  4821. break;
  4822. default:
  4823. status = E1000_READ_REG(hw, STATUS);
  4824. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4825. e1000_bus_type_pcix : e1000_bus_type_pci;
  4826. break;
  4827. }
  4828. }
  4829. #ifndef CONFIG_DM_ETH
  4830. /* A list of all registered e1000 devices */
  4831. static LIST_HEAD(e1000_hw_list);
  4832. #endif
  4833. #ifdef CONFIG_DM_ETH
  4834. static int e1000_init_one(struct e1000_hw *hw, int cardnum,
  4835. struct udevice *devno, unsigned char enetaddr[6])
  4836. #else
  4837. static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
  4838. unsigned char enetaddr[6])
  4839. #endif
  4840. {
  4841. u32 val;
  4842. /* Assign the passed-in values */
  4843. #ifdef CONFIG_DM_ETH
  4844. hw->pdev = devno;
  4845. #else
  4846. hw->pdev = devno;
  4847. #endif
  4848. hw->cardnum = cardnum;
  4849. /* Print a debug message with the IO base address */
  4850. #ifdef CONFIG_DM_ETH
  4851. dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
  4852. #else
  4853. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4854. #endif
  4855. E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
  4856. /* Try to enable I/O accesses and bus-mastering */
  4857. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4858. #ifdef CONFIG_DM_ETH
  4859. dm_pci_write_config32(devno, PCI_COMMAND, val);
  4860. #else
  4861. pci_write_config_dword(devno, PCI_COMMAND, val);
  4862. #endif
  4863. /* Make sure it worked */
  4864. #ifdef CONFIG_DM_ETH
  4865. dm_pci_read_config32(devno, PCI_COMMAND, &val);
  4866. #else
  4867. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4868. #endif
  4869. if (!(val & PCI_COMMAND_MEMORY)) {
  4870. E1000_ERR(hw, "Can't enable I/O memory\n");
  4871. return -ENOSPC;
  4872. }
  4873. if (!(val & PCI_COMMAND_MASTER)) {
  4874. E1000_ERR(hw, "Can't enable bus-mastering\n");
  4875. return -EPERM;
  4876. }
  4877. /* Are these variables needed? */
  4878. hw->fc = e1000_fc_default;
  4879. hw->original_fc = e1000_fc_default;
  4880. hw->autoneg_failed = 0;
  4881. hw->autoneg = 1;
  4882. hw->get_link_status = true;
  4883. #ifndef CONFIG_E1000_NO_NVM
  4884. hw->eeprom_semaphore_present = true;
  4885. #endif
  4886. #ifdef CONFIG_DM_ETH
  4887. hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4888. PCI_REGION_MEM);
  4889. #else
  4890. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4891. PCI_REGION_MEM);
  4892. #endif
  4893. hw->mac_type = e1000_undefined;
  4894. /* MAC and Phy settings */
  4895. if (e1000_sw_init(hw) < 0) {
  4896. E1000_ERR(hw, "Software init failed\n");
  4897. return -EIO;
  4898. }
  4899. if (e1000_check_phy_reset_block(hw))
  4900. E1000_ERR(hw, "PHY Reset is blocked!\n");
  4901. /* Basic init was OK, reset the hardware and allow SPI access */
  4902. e1000_reset_hw(hw);
  4903. #ifndef CONFIG_E1000_NO_NVM
  4904. /* Validate the EEPROM and get chipset information */
  4905. if (e1000_init_eeprom_params(hw)) {
  4906. E1000_ERR(hw, "EEPROM is invalid!\n");
  4907. return -EINVAL;
  4908. }
  4909. if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
  4910. e1000_validate_eeprom_checksum(hw))
  4911. return -ENXIO;
  4912. e1000_read_mac_addr(hw, enetaddr);
  4913. #endif
  4914. e1000_get_bus_type(hw);
  4915. #ifndef CONFIG_E1000_NO_NVM
  4916. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4917. enetaddr[0], enetaddr[1], enetaddr[2],
  4918. enetaddr[3], enetaddr[4], enetaddr[5]);
  4919. #else
  4920. memset(enetaddr, 0, 6);
  4921. printf("e1000: no NVM\n");
  4922. #endif
  4923. return 0;
  4924. }
  4925. /* Put the name of a device in a string */
  4926. static void e1000_name(char *str, int cardnum)
  4927. {
  4928. sprintf(str, "e1000#%u", cardnum);
  4929. }
  4930. #ifndef CONFIG_DM_ETH
  4931. /**************************************************************************
  4932. TRANSMIT - Transmit a frame
  4933. ***************************************************************************/
  4934. static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
  4935. {
  4936. struct e1000_hw *hw = nic->priv;
  4937. return _e1000_transmit(hw, txpacket, length);
  4938. }
  4939. /**************************************************************************
  4940. DISABLE - Turn off ethernet interface
  4941. ***************************************************************************/
  4942. static void
  4943. e1000_disable(struct eth_device *nic)
  4944. {
  4945. struct e1000_hw *hw = nic->priv;
  4946. _e1000_disable(hw);
  4947. }
  4948. /**************************************************************************
  4949. INIT - set up ethernet interface(s)
  4950. ***************************************************************************/
  4951. static int
  4952. e1000_init(struct eth_device *nic, struct bd_info *bis)
  4953. {
  4954. struct e1000_hw *hw = nic->priv;
  4955. return _e1000_init(hw, nic->enetaddr);
  4956. }
  4957. static int
  4958. e1000_poll(struct eth_device *nic)
  4959. {
  4960. struct e1000_hw *hw = nic->priv;
  4961. int len;
  4962. len = _e1000_poll(hw);
  4963. if (len) {
  4964. net_process_received_packet((uchar *)packet, len);
  4965. fill_rx(hw);
  4966. }
  4967. return len ? 1 : 0;
  4968. }
  4969. #endif /* !CONFIG_DM_ETH */
  4970. #ifdef CONFIG_DM_ETH
  4971. static int e1000_write_hwaddr(struct udevice *dev)
  4972. #else
  4973. static int e1000_write_hwaddr(struct eth_device *dev)
  4974. #endif
  4975. {
  4976. #ifndef CONFIG_E1000_NO_NVM
  4977. unsigned char current_mac[6];
  4978. #ifdef CONFIG_DM_ETH
  4979. struct eth_pdata *plat = dev_get_plat(dev);
  4980. struct e1000_hw *hw = dev_get_priv(dev);
  4981. u8 *mac = plat->enetaddr;
  4982. #else
  4983. struct e1000_hw *hw = dev->priv;
  4984. u8 *mac = dev->enetaddr;
  4985. #endif
  4986. uint16_t data[3];
  4987. int ret_val, i;
  4988. DEBUGOUT("%s: mac=%pM\n", __func__, mac);
  4989. memset(current_mac, 0, 6);
  4990. /* Read from EEPROM, not from registers, to make sure
  4991. * the address is persistently configured
  4992. */
  4993. ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
  4994. DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
  4995. /* Only write to EEPROM if the given address is different or
  4996. * reading the current address failed
  4997. */
  4998. if (!ret_val && memcmp(current_mac, mac, 6) == 0)
  4999. return 0;
  5000. for (i = 0; i < 3; ++i)
  5001. data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
  5002. ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
  5003. if (!ret_val)
  5004. ret_val = e1000_update_eeprom_checksum_i210(hw);
  5005. return ret_val;
  5006. #else
  5007. return 0;
  5008. #endif
  5009. }
  5010. #ifndef CONFIG_DM_ETH
  5011. /**************************************************************************
  5012. PROBE - Look for an adapter, this routine's visible to the outside
  5013. You should omit the last argument struct pci_device * for a non-PCI NIC
  5014. ***************************************************************************/
  5015. int
  5016. e1000_initialize(struct bd_info * bis)
  5017. {
  5018. unsigned int i;
  5019. pci_dev_t devno;
  5020. int ret;
  5021. DEBUGFUNC();
  5022. /* Find and probe all the matching PCI devices */
  5023. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  5024. /*
  5025. * These will never get freed due to errors, this allows us to
  5026. * perform SPI EEPROM programming from U-Boot, for example.
  5027. */
  5028. struct eth_device *nic = malloc(sizeof(*nic));
  5029. struct e1000_hw *hw = malloc(sizeof(*hw));
  5030. if (!nic || !hw) {
  5031. printf("e1000#%u: Out of Memory!\n", i);
  5032. free(nic);
  5033. free(hw);
  5034. continue;
  5035. }
  5036. /* Make sure all of the fields are initially zeroed */
  5037. memset(nic, 0, sizeof(*nic));
  5038. memset(hw, 0, sizeof(*hw));
  5039. nic->priv = hw;
  5040. /* Generate a card name */
  5041. e1000_name(nic->name, i);
  5042. hw->name = nic->name;
  5043. ret = e1000_init_one(hw, i, devno, nic->enetaddr);
  5044. if (ret)
  5045. continue;
  5046. list_add_tail(&hw->list_node, &e1000_hw_list);
  5047. hw->nic = nic;
  5048. /* Set up the function pointers and register the device */
  5049. nic->init = e1000_init;
  5050. nic->recv = e1000_poll;
  5051. nic->send = e1000_transmit;
  5052. nic->halt = e1000_disable;
  5053. nic->write_hwaddr = e1000_write_hwaddr;
  5054. eth_register(nic);
  5055. }
  5056. return i;
  5057. }
  5058. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  5059. {
  5060. struct e1000_hw *hw;
  5061. list_for_each_entry(hw, &e1000_hw_list, list_node)
  5062. if (hw->cardnum == cardnum)
  5063. return hw;
  5064. return NULL;
  5065. }
  5066. #endif /* !CONFIG_DM_ETH */
  5067. #ifdef CONFIG_CMD_E1000
  5068. static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
  5069. char *const argv[])
  5070. {
  5071. unsigned char *mac = NULL;
  5072. #ifdef CONFIG_DM_ETH
  5073. struct eth_pdata *plat;
  5074. struct udevice *dev;
  5075. char name[30];
  5076. int ret;
  5077. #endif
  5078. #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
  5079. struct e1000_hw *hw;
  5080. #endif
  5081. int cardnum;
  5082. if (argc < 3) {
  5083. cmd_usage(cmdtp);
  5084. return 1;
  5085. }
  5086. /* Make sure we can find the requested e1000 card */
  5087. cardnum = simple_strtoul(argv[1], NULL, 10);
  5088. #ifdef CONFIG_DM_ETH
  5089. e1000_name(name, cardnum);
  5090. ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
  5091. if (!ret) {
  5092. plat = dev_get_plat(dev);
  5093. mac = plat->enetaddr;
  5094. }
  5095. #else
  5096. hw = e1000_find_card(cardnum);
  5097. if (hw)
  5098. mac = hw->nic->enetaddr;
  5099. #endif
  5100. if (!mac) {
  5101. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  5102. return 1;
  5103. }
  5104. if (!strcmp(argv[2], "print-mac-address")) {
  5105. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  5106. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  5107. return 0;
  5108. }
  5109. #ifdef CONFIG_E1000_SPI
  5110. #ifdef CONFIG_DM_ETH
  5111. hw = dev_get_priv(dev);
  5112. #endif
  5113. /* Handle the "SPI" subcommand */
  5114. if (!strcmp(argv[2], "spi"))
  5115. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  5116. #endif
  5117. cmd_usage(cmdtp);
  5118. return 1;
  5119. }
  5120. U_BOOT_CMD(
  5121. e1000, 7, 0, do_e1000,
  5122. "Intel e1000 controller management",
  5123. /* */"<card#> print-mac-address\n"
  5124. #ifdef CONFIG_E1000_SPI
  5125. "e1000 <card#> spi show [<offset> [<length>]]\n"
  5126. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  5127. "e1000 <card#> spi program <addr> <offset> <length>\n"
  5128. "e1000 <card#> spi checksum [update]\n"
  5129. #endif
  5130. " - Manage the Intel E1000 PCI device"
  5131. );
  5132. #endif /* not CONFIG_CMD_E1000 */
  5133. #ifdef CONFIG_DM_ETH
  5134. static int e1000_eth_start(struct udevice *dev)
  5135. {
  5136. struct eth_pdata *plat = dev_get_plat(dev);
  5137. struct e1000_hw *hw = dev_get_priv(dev);
  5138. return _e1000_init(hw, plat->enetaddr);
  5139. }
  5140. static void e1000_eth_stop(struct udevice *dev)
  5141. {
  5142. struct e1000_hw *hw = dev_get_priv(dev);
  5143. _e1000_disable(hw);
  5144. }
  5145. static int e1000_eth_send(struct udevice *dev, void *packet, int length)
  5146. {
  5147. struct e1000_hw *hw = dev_get_priv(dev);
  5148. int ret;
  5149. ret = _e1000_transmit(hw, packet, length);
  5150. return ret ? 0 : -ETIMEDOUT;
  5151. }
  5152. static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  5153. {
  5154. struct e1000_hw *hw = dev_get_priv(dev);
  5155. int len;
  5156. len = _e1000_poll(hw);
  5157. if (len)
  5158. *packetp = packet;
  5159. return len ? len : -EAGAIN;
  5160. }
  5161. static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
  5162. {
  5163. struct e1000_hw *hw = dev_get_priv(dev);
  5164. fill_rx(hw);
  5165. return 0;
  5166. }
  5167. static int e1000_eth_probe(struct udevice *dev)
  5168. {
  5169. struct eth_pdata *plat = dev_get_plat(dev);
  5170. struct e1000_hw *hw = dev_get_priv(dev);
  5171. int ret;
  5172. hw->name = dev->name;
  5173. ret = e1000_init_one(hw, trailing_strtol(dev->name),
  5174. dev, plat->enetaddr);
  5175. if (ret < 0) {
  5176. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  5177. return ret;
  5178. }
  5179. return 0;
  5180. }
  5181. static int e1000_eth_bind(struct udevice *dev)
  5182. {
  5183. char name[20];
  5184. /*
  5185. * A simple way to number the devices. When device tree is used this
  5186. * is unnecessary, but when the device is just discovered on the PCI
  5187. * bus we need a name. We could instead have the uclass figure out
  5188. * which devices are different and number them.
  5189. */
  5190. e1000_name(name, num_cards++);
  5191. return device_set_name(dev, name);
  5192. }
  5193. static const struct eth_ops e1000_eth_ops = {
  5194. .start = e1000_eth_start,
  5195. .send = e1000_eth_send,
  5196. .recv = e1000_eth_recv,
  5197. .stop = e1000_eth_stop,
  5198. .free_pkt = e1000_free_pkt,
  5199. .write_hwaddr = e1000_write_hwaddr,
  5200. };
  5201. static const struct udevice_id e1000_eth_ids[] = {
  5202. { .compatible = "intel,e1000" },
  5203. { }
  5204. };
  5205. U_BOOT_DRIVER(eth_e1000) = {
  5206. .name = "eth_e1000",
  5207. .id = UCLASS_ETH,
  5208. .of_match = e1000_eth_ids,
  5209. .bind = e1000_eth_bind,
  5210. .probe = e1000_eth_probe,
  5211. .ops = &e1000_eth_ops,
  5212. .priv_auto = sizeof(struct e1000_hw),
  5213. .plat_auto = sizeof(struct eth_pdata),
  5214. };
  5215. U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
  5216. #endif