imx8ulp-evk.dts 4.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright 2021 NXP
  4. */
  5. /dts-v1/;
  6. #include "imx8ulp.dtsi"
  7. / {
  8. model = "FSL i.MX8ULP EVK";
  9. compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
  10. chosen {
  11. stdout-path = &lpuart5;
  12. bootargs = "console=ttyLP1,115200 earlycon";
  13. };
  14. usdhc2_pwrseq: usdhc2_pwrseq {
  15. compatible = "mmc-pwrseq-simple";
  16. reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
  17. };
  18. };
  19. &lpuart5 {
  20. /* console */
  21. pinctrl-names = "default", "sleep";
  22. pinctrl-0 = <&pinctrl_lpuart5>;
  23. pinctrl-1 = <&pinctrl_lpuart5>;
  24. status = "okay";
  25. };
  26. &iomuxc1 {
  27. pinctrl_lpuart5: lpuart5grp {
  28. fsl,pins = <
  29. MX8ULP_PAD_PTF14__LPUART5_TX 0x03
  30. MX8ULP_PAD_PTF15__LPUART5_RX 0x03
  31. >;
  32. };
  33. pinctrl_lpi2c7: lpi2c7grp {
  34. fsl,pins = <
  35. MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27
  36. MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27
  37. >;
  38. };
  39. pinctrl_usdhc0: usdhc0grp {
  40. fsl,pins = <
  41. MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
  42. MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
  43. MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
  44. MX8ULP_PAD_PTD10__SDHC0_D0 0x43
  45. MX8ULP_PAD_PTD9__SDHC0_D1 0x43
  46. MX8ULP_PAD_PTD8__SDHC0_D2 0x43
  47. MX8ULP_PAD_PTD7__SDHC0_D3 0x43
  48. MX8ULP_PAD_PTD6__SDHC0_D4 0x43
  49. MX8ULP_PAD_PTD5__SDHC0_D5 0x43
  50. MX8ULP_PAD_PTD4__SDHC0_D6 0x43
  51. MX8ULP_PAD_PTD3__SDHC0_D7 0x43
  52. MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
  53. >;
  54. };
  55. pinctrl_usdhc2_pte: usdhc2ptegrp {
  56. fsl,pins = <
  57. MX8ULP_PAD_PTE1__SDHC2_D0 0x43
  58. MX8ULP_PAD_PTE0__SDHC2_D1 0x43
  59. MX8ULP_PAD_PTE5__SDHC2_D2 0x43
  60. MX8ULP_PAD_PTE4__SDHC2_D3 0x43
  61. MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
  62. MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
  63. MX8ULP_PAD_PTE7__PTE7 0x10003
  64. >;
  65. };
  66. pinctrl_fec: fecgrp {
  67. fsl,pins = <
  68. MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
  69. MX8ULP_PAD_PTE15__ENET0_MDC 0x43
  70. MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
  71. MX8ULP_PAD_PTE17__ENET0_RXER 0x43
  72. MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
  73. MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
  74. MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
  75. MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
  76. MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
  77. MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
  78. MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
  79. >;
  80. };
  81. pinctrl_usbotg0_id: otg0idgrp {
  82. fsl,pins = <
  83. MX8ULP_PAD_PTF2__USB0_ID 0x10003
  84. >;
  85. };
  86. pinctrl_usbotg1_id: otg1idgrp {
  87. fsl,pins = <
  88. MX8ULP_PAD_PTD23__USB1_ID 0x10003
  89. >;
  90. };
  91. };
  92. &usdhc0 {
  93. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  94. pinctrl-0 = <&pinctrl_usdhc0>;
  95. pinctrl-1 = <&pinctrl_usdhc0>;
  96. pinctrl-2 = <&pinctrl_usdhc0>;
  97. bus-width = <8>;
  98. non-removable;
  99. status = "okay";
  100. };
  101. &usdhc2 {
  102. pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
  103. pinctrl-0 = <&pinctrl_usdhc2_pte>;
  104. pinctrl-1 = <&pinctrl_usdhc2_pte>;
  105. pinctrl-2 = <&pinctrl_usdhc2_pte>;
  106. pinctrl-3 = <&pinctrl_usdhc2_pte>;
  107. mmc-pwrseq = <&usdhc2_pwrseq>;
  108. max-frequency = <100000000>;
  109. bus-width = <4>;
  110. keep-power-in-suspend;
  111. non-removable;
  112. wakeup-source;
  113. status = "okay";
  114. wifi_wake_host {
  115. compatible = "nxp,wifi-wake-host";
  116. interrupt-parent = <&gpioe>;
  117. interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  118. interrupt-names = "host-wake";
  119. };
  120. };
  121. &lpi2c7 {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. clock-frequency = <100000>;
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&pinctrl_lpi2c7>;
  127. status = "okay";
  128. pcal6408: gpio@21 {
  129. compatible = "ti,tca6408";
  130. reg = <0x21>;
  131. gpio-controller;
  132. #gpio-cells = <2>;
  133. };
  134. };
  135. &flexspi0 {
  136. status = "okay";
  137. flash0: atxp032@0 {
  138. reg = <0>;
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. compatible = "jedec,spi-nor";
  142. spi-max-frequency = <66000000>;
  143. };
  144. };
  145. &flexspi2 {
  146. status = "okay";
  147. flash1: mt35xu512aba@0 {
  148. reg = <0>;
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. compatible = "jedec,spi-nor";
  152. spi-max-frequency = <29000000>;
  153. spi-nor,ddr-quad-read-dummy = <8>;
  154. };
  155. };
  156. &fec {
  157. pinctrl-names = "default";
  158. pinctrl-0 = <&pinctrl_fec>;
  159. phy-mode = "rmii";
  160. phy-handle = <&ethphy>;
  161. status = "okay";
  162. phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
  163. mdio {
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. ethphy: ethernet-phy@1 {
  167. reg = <1>;
  168. micrel,led-mode = <1>;
  169. };
  170. };
  171. };
  172. &usbotg0 {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&pinctrl_usbotg0_id>;
  175. srp-disable;
  176. hnp-disable;
  177. adp-disable;
  178. status = "okay";
  179. };
  180. &usbphy0 {
  181. fsl,tx-d-cal = <88>;
  182. };
  183. &usbotg1 {
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&pinctrl_usbotg1_id>;
  186. srp-disable;
  187. hnp-disable;
  188. adp-disable;
  189. status = "okay";
  190. };
  191. &usbphy1 {
  192. fsl,tx-d-cal = <88>;
  193. };