xpedite550x.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010 Extreme Engineering Solutions, Inc.
  4. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite550x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5500"
  15. #define CONFIG_SYS_FORM_PMC_XMC 1
  16. #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
  17. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  18. #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
  19. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  20. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  21. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  22. /*
  23. * Multicore config
  24. */
  25. #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
  26. #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
  27. /*
  28. * DDR config
  29. */
  30. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  31. #define CONFIG_DDR_SPD
  32. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  33. #define SPD_EEPROM_ADDRESS 0x54
  34. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  35. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  36. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  37. #define CONFIG_DDR_ECC
  38. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  39. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  40. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  41. #define CONFIG_VERY_BIG_RAM
  42. #ifndef __ASSEMBLY__
  43. #include <linux/stringify.h>
  44. extern unsigned long get_board_sys_clk(unsigned long dummy);
  45. extern unsigned long get_board_ddr_clk(unsigned long dummy);
  46. #endif
  47. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  48. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  49. /*
  50. * These can be toggled for performance analysis, otherwise use default.
  51. */
  52. #define CONFIG_L2_CACHE /* toggle L2 cache */
  53. #define CONFIG_BTB /* toggle branch predition */
  54. #define CONFIG_ENABLE_36BIT_PHYS 1
  55. #define CONFIG_SYS_CCSRBAR 0xef000000
  56. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  57. /*
  58. * Diagnostics
  59. */
  60. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  61. CONFIG_SYS_POST_I2C)
  62. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
  63. CONFIG_SYS_I2C_LM75_ADDR, \
  64. CONFIG_SYS_I2C_LM90_ADDR, \
  65. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  66. CONFIG_SYS_I2C_PCA953X_ADDR2, \
  67. CONFIG_SYS_I2C_PCA953X_ADDR3, \
  68. CONFIG_SYS_I2C_RTC_ADDR}
  69. /*
  70. * Memory map
  71. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  72. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  73. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  74. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  75. * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
  76. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  77. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  78. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  79. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  80. */
  81. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  82. /*
  83. * NAND flash configuration
  84. */
  85. #define CONFIG_SYS_NAND_BASE 0xef800000
  86. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  87. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
  88. CONFIG_SYS_NAND_BASE2}
  89. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  90. #define CONFIG_NAND_FSL_ELBC
  91. /*
  92. * NOR flash configuration
  93. */
  94. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  95. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  96. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  97. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  98. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  99. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  100. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  101. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  102. {0xf7f40000, 0xc0000} }
  103. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  104. /*
  105. * Chip select configuration
  106. */
  107. /* NOR Flash 0 on CS0 */
  108. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  109. BR_PS_16 | \
  110. BR_V)
  111. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
  112. OR_GPCM_CSNT | \
  113. OR_GPCM_XACS | \
  114. OR_GPCM_ACS_DIV2 | \
  115. OR_GPCM_SCY_8 | \
  116. OR_GPCM_TRLX | \
  117. OR_GPCM_EHTR | \
  118. OR_GPCM_EAD)
  119. /* NOR Flash 1 on CS1 */
  120. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  121. BR_PS_16 | \
  122. BR_V)
  123. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  124. /* NAND flash on CS2 */
  125. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  126. (2<<BR_DECC_SHIFT) | \
  127. BR_PS_8 | \
  128. BR_MS_FCM | \
  129. BR_V)
  130. /* NAND flash on CS2 */
  131. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  132. OR_FCM_PGS | \
  133. OR_FCM_CSCT | \
  134. OR_FCM_CST | \
  135. OR_FCM_CHT | \
  136. OR_FCM_SCY_1 | \
  137. OR_FCM_TRLX | \
  138. OR_FCM_EHTR)
  139. /* NAND flash on CS3 */
  140. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  141. (2<<BR_DECC_SHIFT) | \
  142. BR_PS_8 | \
  143. BR_MS_FCM | \
  144. BR_V)
  145. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  146. /*
  147. * Use L1 as initial stack
  148. */
  149. #define CONFIG_SYS_INIT_RAM_LOCK 1
  150. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  151. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  152. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  153. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  154. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  155. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  156. /*
  157. * Serial Port
  158. */
  159. #define CONFIG_SYS_NS16550_SERIAL
  160. #define CONFIG_SYS_NS16550_REG_SIZE 1
  161. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  162. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  163. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  164. #define CONFIG_SYS_BAUDRATE_TABLE \
  165. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  166. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  167. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  168. /*
  169. * I2C
  170. */
  171. #define CONFIG_SYS_I2C
  172. #define CONFIG_SYS_I2C_FSL
  173. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  174. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  175. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  176. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  177. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  178. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  179. /* I2C DS7505 temperature sensor */
  180. #define CONFIG_SYS_I2C_LM75_ADDR 0x48
  181. /* I2C ADT7461 temperature sensor */
  182. #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
  183. /* I2C EEPROM - AT24C128B */
  184. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  185. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  186. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  187. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  188. /* I2C RTC */
  189. #define CONFIG_RTC_M41T11 1
  190. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  191. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  192. /* GPIO */
  193. #define CONFIG_PCA953X
  194. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  195. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  196. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  197. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  198. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  199. /*
  200. * GPIO pin definitions, PU = pulled high, PD = pulled low
  201. */
  202. /* PCA9557 @ 0x18*/
  203. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  204. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
  205. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  206. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
  207. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  208. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
  209. /* PCA9557 @ 0x1e*/
  210. #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
  211. #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
  212. #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
  213. #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
  214. #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
  215. #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
  216. #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
  217. /* PCA9557 @ 0x1f */
  218. #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
  219. #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
  220. #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
  221. #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
  222. #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
  223. #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
  224. #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
  225. #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
  226. /*
  227. * General PCI
  228. * Memory space is mapped 1-1, but I/O space must start from 0.
  229. */
  230. /* controller 1 - PEX8112 or XMC, depending on build option */
  231. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  232. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  233. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  234. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  235. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  236. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  237. /*
  238. * Networking options
  239. */
  240. #define CONFIG_TSEC_TBI
  241. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  242. #define CONFIG_ETHPRIME "eTSEC2"
  243. /*
  244. * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
  245. * 1000mbps SGMII link
  246. */
  247. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  248. TBICR_PHY_RESET \
  249. | TBICR_FULL_DUPLEX \
  250. | TBICR_SPEED1_SET \
  251. )
  252. #define CONFIG_TSEC1 1
  253. #define CONFIG_TSEC1_NAME "eTSEC1"
  254. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  255. #define TSEC1_PHY_ADDR 1
  256. #define TSEC1_PHYIDX 0
  257. #define CONFIG_HAS_ETH0
  258. #define CONFIG_TSEC2 1
  259. #define CONFIG_TSEC2_NAME "eTSEC2"
  260. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  261. #define TSEC2_PHY_ADDR 2
  262. #define TSEC2_PHYIDX 0
  263. #define CONFIG_HAS_ETH1
  264. #define CONFIG_TSEC3 1
  265. #define CONFIG_TSEC3_NAME "eTSEC3"
  266. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  267. #define TSEC3_PHY_ADDR 3
  268. #define TSEC3_PHYIDX 0
  269. #define CONFIG_HAS_ETH2
  270. /*
  271. * USB
  272. */
  273. #define CONFIG_USB_EHCI_FSL
  274. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  275. /*
  276. * Miscellaneous configurable options
  277. */
  278. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  279. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  280. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  281. /*
  282. * For booting Linux, the board info and command line data
  283. * have to be in the first 16 MB of memory, since this is
  284. * the maximum mapped by the Linux kernel during initialization.
  285. */
  286. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  287. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  288. /*
  289. * Environment Configuration
  290. */
  291. /*
  292. * Flash memory map:
  293. * fff80000 - ffffffff Pri U-Boot (512 KB)
  294. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  295. * fff00000 - fff3ffff Pri FDT (256KB)
  296. * fef00000 - ffefffff Pri OS image (16MB)
  297. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  298. *
  299. * f7f80000 - f7ffffff Sec U-Boot (512 KB)
  300. * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
  301. * f7f00000 - f7f3ffff Sec FDT (256KB)
  302. * f6f00000 - f7efffff Sec OS image (16MB)
  303. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  304. */
  305. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  306. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
  307. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  308. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
  309. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  310. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  311. #define CONFIG_PROG_UBOOT1 \
  312. "$download_cmd $loadaddr $ubootfile; " \
  313. "if test $? -eq 0; then " \
  314. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  315. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  316. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  317. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  318. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  319. "if test $? -ne 0; then " \
  320. "echo PROGRAM FAILED; " \
  321. "else; " \
  322. "echo PROGRAM SUCCEEDED; " \
  323. "fi; " \
  324. "else; " \
  325. "echo DOWNLOAD FAILED; " \
  326. "fi;"
  327. #define CONFIG_PROG_UBOOT2 \
  328. "$download_cmd $loadaddr $ubootfile; " \
  329. "if test $? -eq 0; then " \
  330. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  331. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  332. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  333. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  334. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  335. "if test $? -ne 0; then " \
  336. "echo PROGRAM FAILED; " \
  337. "else; " \
  338. "echo PROGRAM SUCCEEDED; " \
  339. "fi; " \
  340. "else; " \
  341. "echo DOWNLOAD FAILED; " \
  342. "fi;"
  343. #define CONFIG_BOOT_OS_NET \
  344. "$download_cmd $osaddr $osfile; " \
  345. "if test $? -eq 0; then " \
  346. "if test -n $fdtaddr; then " \
  347. "$download_cmd $fdtaddr $fdtfile; " \
  348. "if test $? -eq 0; then " \
  349. "bootm $osaddr - $fdtaddr; " \
  350. "else; " \
  351. "echo FDT DOWNLOAD FAILED; " \
  352. "fi; " \
  353. "else; " \
  354. "bootm $osaddr; " \
  355. "fi; " \
  356. "else; " \
  357. "echo OS DOWNLOAD FAILED; " \
  358. "fi;"
  359. #define CONFIG_PROG_OS1 \
  360. "$download_cmd $osaddr $osfile; " \
  361. "if test $? -eq 0; then " \
  362. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  363. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  364. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  365. "if test $? -ne 0; then " \
  366. "echo OS PROGRAM FAILED; " \
  367. "else; " \
  368. "echo OS PROGRAM SUCCEEDED; " \
  369. "fi; " \
  370. "else; " \
  371. "echo OS DOWNLOAD FAILED; " \
  372. "fi;"
  373. #define CONFIG_PROG_OS2 \
  374. "$download_cmd $osaddr $osfile; " \
  375. "if test $? -eq 0; then " \
  376. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  377. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  378. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  379. "if test $? -ne 0; then " \
  380. "echo OS PROGRAM FAILED; " \
  381. "else; " \
  382. "echo OS PROGRAM SUCCEEDED; " \
  383. "fi; " \
  384. "else; " \
  385. "echo OS DOWNLOAD FAILED; " \
  386. "fi;"
  387. #define CONFIG_PROG_FDT1 \
  388. "$download_cmd $fdtaddr $fdtfile; " \
  389. "if test $? -eq 0; then " \
  390. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  391. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  392. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  393. "if test $? -ne 0; then " \
  394. "echo FDT PROGRAM FAILED; " \
  395. "else; " \
  396. "echo FDT PROGRAM SUCCEEDED; " \
  397. "fi; " \
  398. "else; " \
  399. "echo FDT DOWNLOAD FAILED; " \
  400. "fi;"
  401. #define CONFIG_PROG_FDT2 \
  402. "$download_cmd $fdtaddr $fdtfile; " \
  403. "if test $? -eq 0; then " \
  404. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  405. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  406. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  407. "if test $? -ne 0; then " \
  408. "echo FDT PROGRAM FAILED; " \
  409. "else; " \
  410. "echo FDT PROGRAM SUCCEEDED; " \
  411. "fi; " \
  412. "else; " \
  413. "echo FDT DOWNLOAD FAILED; " \
  414. "fi;"
  415. #define CONFIG_EXTRA_ENV_SETTINGS \
  416. "autoload=yes\0" \
  417. "download_cmd=tftp\0" \
  418. "console_args=console=ttyS0,115200\0" \
  419. "root_args=root=/dev/nfs rw\0" \
  420. "misc_args=ip=on\0" \
  421. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  422. "bootfile=/home/user/file\0" \
  423. "osfile=/home/user/board.uImage\0" \
  424. "fdtfile=/home/user/board.dtb\0" \
  425. "ubootfile=/home/user/u-boot.bin\0" \
  426. "fdtaddr=0x1e00000\0" \
  427. "osaddr=0x1000000\0" \
  428. "loadaddr=0x1000000\0" \
  429. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  430. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  431. "prog_os1="CONFIG_PROG_OS1"\0" \
  432. "prog_os2="CONFIG_PROG_OS2"\0" \
  433. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  434. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  435. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  436. "bootcmd_flash1=run set_bootargs; " \
  437. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  438. "bootcmd_flash2=run set_bootargs; " \
  439. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  440. "bootcmd=run bootcmd_flash1\0"
  441. #endif /* __CONFIG_H */