t4qds.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * Corenet DS style board configuration file
  7. */
  8. #ifndef __T4QDS_H
  9. #define __T4QDS_H
  10. /* High Level Configuration Options */
  11. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  12. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  13. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  14. #endif
  15. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  16. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  17. #define CONFIG_PCIE1 /* PCIE controller 1 */
  18. #define CONFIG_PCIE2 /* PCIE controller 2 */
  19. #define CONFIG_PCIE3 /* PCIE controller 3 */
  20. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  21. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  22. #define CONFIG_SYS_SRIO
  23. #define CONFIG_SRIO1 /* SRIO port 1 */
  24. #define CONFIG_SRIO2 /* SRIO port 2 */
  25. #define CONFIG_ENV_OVERWRITE
  26. /*
  27. * These can be toggled for performance analysis, otherwise use default.
  28. */
  29. #define CONFIG_SYS_CACHE_STASHING
  30. #define CONFIG_BTB /* toggle branch predition */
  31. #ifdef CONFIG_DDR_ECC
  32. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  33. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  34. #endif
  35. #define CONFIG_ENABLE_36BIT_PHYS
  36. /*
  37. * Config the L3 Cache as L3 SRAM
  38. */
  39. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  40. #define CONFIG_SYS_L3_SIZE (512 << 10)
  41. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  42. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  43. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  44. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  45. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  46. #define CONFIG_SYS_DCSRBAR 0xf0000000
  47. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  48. /*
  49. * DDR Setup
  50. */
  51. #define CONFIG_VERY_BIG_RAM
  52. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  53. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  54. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  55. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  56. #define CONFIG_DDR_SPD
  57. /*
  58. * IFC Definitions
  59. */
  60. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  61. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  62. #ifdef CONFIG_SPL_BUILD
  63. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  64. #else
  65. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  66. #endif
  67. #define CONFIG_HWCONFIG
  68. /* define to use L1 as initial stack */
  69. #define CONFIG_L1_INIT_RAM
  70. #define CONFIG_SYS_INIT_RAM_LOCK
  71. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  72. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  73. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  74. /* The assembler doesn't like typecast */
  75. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  76. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  77. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  78. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  79. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  80. GENERATED_GBL_DATA_SIZE)
  81. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  82. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  83. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  84. /* Serial Port - controlled on board with jumper J8
  85. * open - index 2
  86. * shorted - index 1
  87. */
  88. #define CONFIG_SYS_NS16550_SERIAL
  89. #define CONFIG_SYS_NS16550_REG_SIZE 1
  90. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  91. #define CONFIG_SYS_BAUDRATE_TABLE \
  92. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  93. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  94. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  95. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  96. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  97. /* I2C */
  98. #define CONFIG_SYS_I2C
  99. #define CONFIG_SYS_I2C_FSL
  100. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  101. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  102. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  103. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  104. /*
  105. * RapidIO
  106. */
  107. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  108. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  109. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  110. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  111. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  112. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  113. /*
  114. * General PCI
  115. * Memory space is mapped 1-1, but I/O space must start from 0.
  116. */
  117. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  118. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  119. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  120. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  121. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  122. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  123. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  124. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  125. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  126. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  127. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  128. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  129. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  130. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  131. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  132. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  133. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  134. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  135. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  136. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  137. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  138. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  139. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  140. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  141. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  142. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  143. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  144. /* controller 4, Base address 203000 */
  145. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  146. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  147. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  148. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  149. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  150. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  151. #ifdef CONFIG_PCI
  152. #define CONFIG_PCI_INDIRECT_BRIDGE
  153. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  154. #endif /* CONFIG_PCI */
  155. /* SATA */
  156. #ifdef CONFIG_FSL_SATA_V2
  157. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  158. #define CONFIG_SATA1
  159. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  160. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  161. #define CONFIG_SATA2
  162. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  163. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  164. #define CONFIG_LBA48
  165. #endif
  166. #ifdef CONFIG_FMAN_ENET
  167. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  168. #endif
  169. /*
  170. * Environment
  171. */
  172. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  173. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  174. /*
  175. * Miscellaneous configurable options
  176. */
  177. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  178. /*
  179. * For booting Linux, the board info and command line data
  180. * have to be in the first 64 MB of memory, since this is
  181. * the maximum mapped by the Linux kernel during initialization.
  182. */
  183. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  184. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  185. #ifdef CONFIG_CMD_KGDB
  186. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  187. #endif
  188. /*
  189. * Environment Configuration
  190. */
  191. #define CONFIG_ROOTPATH "/opt/nfsroot"
  192. #define CONFIG_BOOTFILE "uImage"
  193. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  194. /* default location for tftp and bootm */
  195. #define CONFIG_LOADADDR 1000000
  196. #define CONFIG_HVBOOT \
  197. "setenv bootargs config-addr=0x60000000; " \
  198. "bootm 0x01000000 - 0x00f00000"
  199. #endif /* __CONFIG_H */