ls1088ardb.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017, 2020 NXP
  4. */
  5. #ifndef __LS1088A_RDB_H
  6. #define __LS1088A_RDB_H
  7. #include "ls1088a_common.h"
  8. #define CONFIG_SYS_MMC_ENV_DEV 0
  9. #if defined(CONFIG_TFABOOT) || \
  10. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  11. #ifndef CONFIG_SPL_BUILD
  12. #define CONFIG_QIXIS_I2C_ACCESS
  13. #endif
  14. #define SYS_NO_FLASH
  15. #endif
  16. #define CONFIG_SYS_CLK_FREQ 100000000
  17. #define CONFIG_DDR_CLK_FREQ 100000000
  18. #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
  19. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  20. #define CONFIG_DDR_SPD
  21. #ifdef CONFIG_EMU
  22. #define CONFIG_SYS_FSL_DDR_EMU
  23. #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
  24. #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
  25. #else
  26. #define CONFIG_DDR_ECC
  27. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  28. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  29. #endif
  30. #define SPD_EEPROM_ADDRESS 0x51
  31. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  32. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  33. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  34. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  35. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  36. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
  37. #define CONFIG_SYS_NOR0_CSPR \
  38. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  39. CSPR_PORT_SIZE_16 | \
  40. CSPR_MSEL_NOR | \
  41. CSPR_V)
  42. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  43. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  44. CSPR_PORT_SIZE_16 | \
  45. CSPR_MSEL_NOR | \
  46. CSPR_V)
  47. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
  48. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  49. FTIM0_NOR_TEADC(0x1) | \
  50. FTIM0_NOR_TEAHC(0x1))
  51. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
  52. FTIM1_NOR_TRAD_NOR(0x1))
  53. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
  54. FTIM2_NOR_TCH(0x0) | \
  55. FTIM2_NOR_TWP(0x1))
  56. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  57. #define CONFIG_SYS_IFC_CCR 0x01000000
  58. #ifndef SYS_NO_FLASH
  59. #define CONFIG_SYS_FLASH_QUIET_TEST
  60. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  61. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  62. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  63. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  64. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  65. #define CONFIG_SYS_FLASH_EMPTY_INFO
  66. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  67. #endif
  68. #endif
  69. #ifndef SPL_NO_IFC
  70. #define CONFIG_NAND_FSL_IFC
  71. #endif
  72. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  73. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  74. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  75. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  76. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  77. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  78. | CSPR_V)
  79. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  80. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  81. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  82. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  83. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  84. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  85. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  86. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  87. #define CONFIG_SYS_NAND_ONFI_DETECTION
  88. /* ONFI NAND Flash mode0 Timing Params */
  89. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  90. FTIM0_NAND_TWP(0x18) | \
  91. FTIM0_NAND_TWCHT(0x07) | \
  92. FTIM0_NAND_TWH(0x0a))
  93. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  94. FTIM1_NAND_TWBE(0x39) | \
  95. FTIM1_NAND_TRR(0x0e) | \
  96. FTIM1_NAND_TRP(0x18))
  97. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  98. FTIM2_NAND_TREH(0x0a) | \
  99. FTIM2_NAND_TWHRE(0x1e))
  100. #define CONFIG_SYS_NAND_FTIM3 0x0
  101. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  102. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  103. #define CONFIG_MTD_NAND_VERIFY_WRITE
  104. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  105. #ifndef SPL_NO_QIXIS
  106. #define CONFIG_FSL_QIXIS
  107. #endif
  108. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  109. #define QIXIS_BRDCFG4_OFFSET 0x54
  110. #define QIXIS_LBMAP_SWITCH 2
  111. #define QIXIS_QMAP_MASK 0xe0
  112. #define QIXIS_QMAP_SHIFT 5
  113. #define QIXIS_LBMAP_MASK 0x1f
  114. #define QIXIS_LBMAP_SHIFT 5
  115. #define QIXIS_LBMAP_DFLTBANK 0x00
  116. #define QIXIS_LBMAP_ALTBANK 0x20
  117. #define QIXIS_LBMAP_SD 0x00
  118. #define QIXIS_LBMAP_EMMC 0x00
  119. #define QIXIS_LBMAP_SD_QSPI 0x00
  120. #define QIXIS_LBMAP_QSPI 0x00
  121. #define QIXIS_RCW_SRC_SD 0x40
  122. #define QIXIS_RCW_SRC_EMMC 0x41
  123. #define QIXIS_RCW_SRC_QSPI 0x62
  124. #define QIXIS_RST_CTL_RESET 0x31
  125. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  126. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  127. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  128. #define QIXIS_RST_FORCE_MEM 0x01
  129. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  130. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  131. | CSPR_PORT_SIZE_8 \
  132. | CSPR_MSEL_GPCM \
  133. | CSPR_V)
  134. #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  135. | CSPR_PORT_SIZE_8 \
  136. | CSPR_MSEL_GPCM \
  137. | CSPR_V)
  138. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
  139. #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
  140. /* QIXIS Timing parameters*/
  141. #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  142. FTIM0_GPCM_TEADC(0x0e) | \
  143. FTIM0_GPCM_TEAHC(0x0e))
  144. #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  145. FTIM1_GPCM_TRAD(0x3f))
  146. #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  147. FTIM2_GPCM_TCH(0xf) | \
  148. FTIM2_GPCM_TWP(0x3E))
  149. #define SYS_FPGA_CS_FTIM3 0x0
  150. #if defined(CONFIG_TFABOOT) || \
  151. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  152. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  153. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  154. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  155. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  156. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  157. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  158. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  159. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  160. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
  161. #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
  162. #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
  163. #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
  164. #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
  165. #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
  166. #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
  167. #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
  168. #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
  169. #else
  170. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  171. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  172. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  173. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  174. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  175. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  176. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  177. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  178. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  179. #endif
  180. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  181. #define I2C_MUX_CH_VOL_MONITOR 0xA
  182. /* Voltage monitor on channel 2*/
  183. #define I2C_VOL_MONITOR_ADDR 0x63
  184. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  185. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  186. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  187. #define I2C_SVDD_MONITOR_ADDR 0x4F
  188. #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
  189. #define CONFIG_VID
  190. /* The lowest and highest voltage allowed for LS1088ARDB */
  191. #define VDD_MV_MIN 819
  192. #define VDD_MV_MAX 1212
  193. #define CONFIG_VOL_MONITOR_LTC3882_SET
  194. #define CONFIG_VOL_MONITOR_LTC3882_READ
  195. /* PM Bus commands code for LTC3882*/
  196. #define PMBUS_CMD_PAGE 0x0
  197. #define PMBUS_CMD_READ_VOUT 0x8B
  198. #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
  199. #define PMBUS_CMD_VOUT_COMMAND 0x21
  200. #define PWM_CHANNEL0 0x0
  201. /*
  202. * I2C bus multiplexer
  203. */
  204. #define I2C_MUX_PCA_ADDR_PRI 0x77
  205. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  206. #define I2C_RETIMER_ADDR 0x18
  207. #define I2C_MUX_CH_DEFAULT 0x8
  208. #define I2C_MUX_CH5 0xD
  209. #ifndef SPL_NO_RTC
  210. /*
  211. * RTC configuration
  212. */
  213. #define RTC
  214. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  215. #endif
  216. /* EEPROM */
  217. #define CONFIG_ID_EEPROM
  218. #define CONFIG_SYS_I2C_EEPROM_NXID
  219. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  220. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  221. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  222. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  223. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  224. #ifdef CONFIG_SPL_BUILD
  225. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  226. #else
  227. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  228. #endif
  229. #define CONFIG_FSL_MEMAC
  230. #ifndef SPL_NO_ENV
  231. /* Initial environment variables */
  232. #ifdef CONFIG_TFABOOT
  233. #define QSPI_MC_INIT_CMD \
  234. "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  235. "sf read 0x80100000 0xE00000 0x100000;" \
  236. "env exists secureboot && " \
  237. "sf read 0x80640000 0x640000 0x40000 && " \
  238. "sf read 0x80680000 0x680000 0x40000 && " \
  239. "esbc_validate 0x80640000 && " \
  240. "esbc_validate 0x80680000 ;" \
  241. "fsl_mc start mc 0x80000000 0x80100000\0"
  242. #define SD_MC_INIT_CMD \
  243. "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  244. "mmc read 0x80100000 0x7000 0x800;" \
  245. "env exists secureboot && " \
  246. "mmc read 0x80640000 0x3200 0x20 && " \
  247. "mmc read 0x80680000 0x3400 0x20 && " \
  248. "esbc_validate 0x80640000 && " \
  249. "esbc_validate 0x80680000 ;" \
  250. "fsl_mc start mc 0x80000000 0x80100000\0"
  251. #else
  252. #if defined(CONFIG_QSPI_BOOT)
  253. #define MC_INIT_CMD \
  254. "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  255. "sf read 0x80100000 0xE00000 0x100000;" \
  256. "env exists secureboot && " \
  257. "sf read 0x80640000 0x640000 0x40000 && " \
  258. "sf read 0x80680000 0x680000 0x40000 && " \
  259. "esbc_validate 0x80640000 && " \
  260. "esbc_validate 0x80680000 ;" \
  261. "fsl_mc start mc 0x80000000 0x80100000\0" \
  262. "mcmemsize=0x70000000\0"
  263. #elif defined(CONFIG_SD_BOOT)
  264. #define MC_INIT_CMD \
  265. "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  266. "mmc read 0x80100000 0x7000 0x800;" \
  267. "env exists secureboot && " \
  268. "mmc read 0x80640000 0x3200 0x20 && " \
  269. "mmc read 0x80680000 0x3400 0x20 && " \
  270. "esbc_validate 0x80640000 && " \
  271. "esbc_validate 0x80680000 ;" \
  272. "fsl_mc start mc 0x80000000 0x80100000\0" \
  273. "mcmemsize=0x70000000\0"
  274. #endif
  275. #endif /* CONFIG_TFABOOT */
  276. #undef CONFIG_EXTRA_ENV_SETTINGS
  277. #ifdef CONFIG_TFABOOT
  278. #define CONFIG_EXTRA_ENV_SETTINGS \
  279. "BOARD=ls1088ardb\0" \
  280. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  281. "ramdisk_addr=0x800000\0" \
  282. "ramdisk_size=0x2000000\0" \
  283. "fdt_high=0xa0000000\0" \
  284. "initrd_high=0xffffffffffffffff\0" \
  285. "fdt_addr=0x64f00000\0" \
  286. "kernel_addr=0x1000000\0" \
  287. "kernel_addr_sd=0x8000\0" \
  288. "kernelhdr_addr_sd=0x3000\0" \
  289. "kernel_start=0x580100000\0" \
  290. "kernelheader_start=0x580600000\0" \
  291. "scriptaddr=0x80000000\0" \
  292. "scripthdraddr=0x80080000\0" \
  293. "fdtheader_addr_r=0x80100000\0" \
  294. "kernelheader_addr=0x600000\0" \
  295. "kernelheader_addr_r=0x80200000\0" \
  296. "kernel_addr_r=0x81000000\0" \
  297. "kernelheader_size=0x40000\0" \
  298. "fdt_addr_r=0x90000000\0" \
  299. "load_addr=0xa0000000\0" \
  300. "kernel_size=0x2800000\0" \
  301. "kernel_size_sd=0x14000\0" \
  302. "kernelhdr_size_sd=0x20\0" \
  303. QSPI_MC_INIT_CMD \
  304. "mcmemsize=0x70000000\0" \
  305. BOOTENV \
  306. "boot_scripts=ls1088ardb_boot.scr\0" \
  307. "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
  308. "scan_dev_for_boot_part=" \
  309. "part list ${devtype} ${devnum} devplist; " \
  310. "env exists devplist || setenv devplist 1; " \
  311. "for distro_bootpart in ${devplist}; do " \
  312. "if fstype ${devtype} " \
  313. "${devnum}:${distro_bootpart} " \
  314. "bootfstype; then " \
  315. "run scan_dev_for_boot; " \
  316. "fi; " \
  317. "done\0" \
  318. "boot_a_script=" \
  319. "load ${devtype} ${devnum}:${distro_bootpart} " \
  320. "${scriptaddr} ${prefix}${script}; " \
  321. "env exists secureboot && load ${devtype} " \
  322. "${devnum}:${distro_bootpart} " \
  323. "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
  324. "env exists secureboot " \
  325. "&& esbc_validate ${scripthdraddr};" \
  326. "source ${scriptaddr}\0" \
  327. "installer=load mmc 0:2 $load_addr " \
  328. "/flex_installer_arm64.itb; " \
  329. "env exists mcinitcmd && run mcinitcmd && " \
  330. "mmc read 0x80001000 0x6800 0x800;" \
  331. "fsl_mc lazyapply dpl 0x80001000;" \
  332. "bootm $load_addr#ls1088ardb\0" \
  333. "qspi_bootcmd=echo Trying load from qspi..;" \
  334. "sf probe && sf read $load_addr " \
  335. "$kernel_addr $kernel_size ; env exists secureboot " \
  336. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  337. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  338. "bootm $load_addr#$BOARD\0" \
  339. "sd_bootcmd=echo Trying load from sd card..;" \
  340. "mmcinfo; mmc read $load_addr " \
  341. "$kernel_addr_sd $kernel_size_sd ;" \
  342. "env exists secureboot && mmc read $kernelheader_addr_r "\
  343. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  344. " && esbc_validate ${kernelheader_addr_r};" \
  345. "bootm $load_addr#$BOARD\0"
  346. #else
  347. #define CONFIG_EXTRA_ENV_SETTINGS \
  348. "BOARD=ls1088ardb\0" \
  349. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  350. "ramdisk_addr=0x800000\0" \
  351. "ramdisk_size=0x2000000\0" \
  352. "fdt_high=0xa0000000\0" \
  353. "initrd_high=0xffffffffffffffff\0" \
  354. "fdt_addr=0x64f00000\0" \
  355. "kernel_addr=0x1000000\0" \
  356. "kernel_addr_sd=0x8000\0" \
  357. "kernelhdr_addr_sd=0x3000\0" \
  358. "kernel_start=0x580100000\0" \
  359. "kernelheader_start=0x580800000\0" \
  360. "scriptaddr=0x80000000\0" \
  361. "scripthdraddr=0x80080000\0" \
  362. "fdtheader_addr_r=0x80100000\0" \
  363. "kernelheader_addr=0x600000\0" \
  364. "kernelheader_addr_r=0x80200000\0" \
  365. "kernel_addr_r=0x81000000\0" \
  366. "kernelheader_size=0x40000\0" \
  367. "fdt_addr_r=0x90000000\0" \
  368. "load_addr=0xa0000000\0" \
  369. "kernel_size=0x2800000\0" \
  370. "kernel_size_sd=0x14000\0" \
  371. "kernelhdr_size_sd=0x20\0" \
  372. MC_INIT_CMD \
  373. BOOTENV \
  374. "boot_scripts=ls1088ardb_boot.scr\0" \
  375. "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
  376. "scan_dev_for_boot_part=" \
  377. "part list ${devtype} ${devnum} devplist; " \
  378. "env exists devplist || setenv devplist 1; " \
  379. "for distro_bootpart in ${devplist}; do " \
  380. "if fstype ${devtype} " \
  381. "${devnum}:${distro_bootpart} " \
  382. "bootfstype; then " \
  383. "run scan_dev_for_boot; " \
  384. "fi; " \
  385. "done\0" \
  386. "boot_a_script=" \
  387. "load ${devtype} ${devnum}:${distro_bootpart} " \
  388. "${scriptaddr} ${prefix}${script}; " \
  389. "env exists secureboot && load ${devtype} " \
  390. "${devnum}:${distro_bootpart} " \
  391. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  392. "&& esbc_validate ${scripthdraddr};" \
  393. "source ${scriptaddr}\0" \
  394. "installer=load mmc 0:2 $load_addr " \
  395. "/flex_installer_arm64.itb; " \
  396. "env exists mcinitcmd && run mcinitcmd && " \
  397. "mmc read 0x80001000 0x6800 0x800;" \
  398. "fsl_mc lazyapply dpl 0x80001000;" \
  399. "bootm $load_addr#ls1088ardb\0" \
  400. "qspi_bootcmd=echo Trying load from qspi..;" \
  401. "sf probe && sf read $load_addr " \
  402. "$kernel_addr $kernel_size ; env exists secureboot " \
  403. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  404. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  405. "bootm $load_addr#$BOARD\0" \
  406. "sd_bootcmd=echo Trying load from sd card..;" \
  407. "mmcinfo; mmc read $load_addr " \
  408. "$kernel_addr_sd $kernel_size_sd ;" \
  409. "env exists secureboot && mmc read $kernelheader_addr_r "\
  410. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  411. " && esbc_validate ${kernelheader_addr_r};" \
  412. "bootm $load_addr#$BOARD\0"
  413. #endif /* CONFIG_TFABOOT */
  414. #undef CONFIG_BOOTCOMMAND
  415. #ifdef CONFIG_TFABOOT
  416. #define QSPI_NOR_BOOTCOMMAND \
  417. "sf read 0x80001000 0xd00000 0x100000;" \
  418. "env exists mcinitcmd && env exists secureboot " \
  419. " && sf read 0x806C0000 0x6C0000 0x100000 " \
  420. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  421. "&& fsl_mc lazyapply dpl 0x80001000;" \
  422. "run distro_bootcmd;run qspi_bootcmd;" \
  423. "env exists secureboot && esbc_halt;"
  424. #define SD_BOOTCOMMAND \
  425. "env exists mcinitcmd && mmcinfo; " \
  426. "mmc read 0x80001000 0x6800 0x800; " \
  427. "env exists mcinitcmd && env exists secureboot " \
  428. " && mmc read 0x806C0000 0x3600 0x20 " \
  429. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  430. "&& fsl_mc lazyapply dpl 0x80001000;" \
  431. "run distro_bootcmd;run sd_bootcmd;" \
  432. "env exists secureboot && esbc_halt;"
  433. #else
  434. #if defined(CONFIG_QSPI_BOOT)
  435. /* Try to boot an on-QSPI kernel first, then do normal distro boot */
  436. #define CONFIG_BOOTCOMMAND \
  437. "sf read 0x80001000 0xd00000 0x100000;" \
  438. "env exists mcinitcmd && env exists secureboot " \
  439. " && sf read 0x806C0000 0x6C0000 0x100000 " \
  440. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  441. "&& fsl_mc lazyapply dpl 0x80001000;" \
  442. "run distro_bootcmd;run qspi_bootcmd;" \
  443. "env exists secureboot && esbc_halt;"
  444. /* Try to boot an on-SD kernel first, then do normal distro boot */
  445. #elif defined(CONFIG_SD_BOOT)
  446. #define CONFIG_BOOTCOMMAND \
  447. "env exists mcinitcmd && mmcinfo; " \
  448. "mmc read 0x80001000 0x6800 0x800; " \
  449. "env exists mcinitcmd && env exists secureboot " \
  450. " && mmc read 0x806C0000 0x3600 0x20 " \
  451. "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
  452. "&& fsl_mc lazyapply dpl 0x80001000;" \
  453. "run distro_bootcmd;run sd_bootcmd;" \
  454. "env exists secureboot && esbc_halt;"
  455. #endif
  456. #endif /* CONFIG_TFABOOT */
  457. /* MAC/PHY configuration */
  458. #ifdef CONFIG_FSL_MC_ENET
  459. #define AQ_PHY_ADDR1 0x00
  460. #define AQR105_IRQ_MASK 0x00000004
  461. #define QSGMII1_PORT1_PHY_ADDR 0x0c
  462. #define QSGMII1_PORT2_PHY_ADDR 0x0d
  463. #define QSGMII1_PORT3_PHY_ADDR 0x0e
  464. #define QSGMII1_PORT4_PHY_ADDR 0x0f
  465. #define QSGMII2_PORT1_PHY_ADDR 0x1c
  466. #define QSGMII2_PORT2_PHY_ADDR 0x1d
  467. #define QSGMII2_PORT3_PHY_ADDR 0x1e
  468. #define QSGMII2_PORT4_PHY_ADDR 0x1f
  469. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  470. #define CONFIG_PHY_GIGE
  471. #endif
  472. #endif
  473. /* MMC */
  474. #ifdef CONFIG_MMC
  475. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  476. #endif
  477. #ifndef SPL_NO_ENV
  478. #define BOOT_TARGET_DEVICES(func) \
  479. func(MMC, mmc, 0) \
  480. func(SCSI, scsi, 0) \
  481. func(DHCP, dhcp, na)
  482. #include <config_distro_bootcmd.h>
  483. #endif
  484. #include <asm/fsl_secure_boot.h>
  485. #endif /* __LS1088A_RDB_H */