ls1028a_common.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019-2020 NXP
  4. */
  5. #ifndef __L1028A_COMMON_H
  6. #define __L1028A_COMMON_H
  7. #define CONFIG_REMAKE_ELF
  8. #define CONFIG_FSL_LAYERSCAPE
  9. #define CONFIG_MP
  10. #include <asm/arch/stream_id_lsch3.h>
  11. #include <asm/arch/config.h>
  12. #include <asm/arch/soc.h>
  13. /* Link Definitions */
  14. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  15. #define CONFIG_SKIP_LOWLEVEL_INIT
  16. #define CONFIG_VERY_BIG_RAM
  17. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  18. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  19. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  20. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
  21. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  22. /*
  23. * SMP Definitinos
  24. */
  25. #define CPU_RELEASE_ADDR secondary_boot_func
  26. /* Generic Timer Definitions */
  27. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  28. /* Size of malloc() pool */
  29. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
  30. /* I2C */
  31. #ifndef CONFIG_DM_I2C
  32. #define CONFIG_SYS_I2C
  33. #endif
  34. /* Serial Port */
  35. #define CONFIG_SYS_NS16550_SERIAL
  36. #define CONFIG_SYS_NS16550_REG_SIZE 1
  37. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  38. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  39. /* Miscellaneous configurable options */
  40. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  41. /* Physical Memory Map */
  42. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  43. #define CONFIG_HWCONFIG
  44. #define HWCONFIG_BUFFER_SIZE 128
  45. /* Allow to overwrite serial and ethaddr */
  46. #define CONFIG_ENV_OVERWRITE
  47. #define BOOT_TARGET_DEVICES(func) \
  48. func(MMC, mmc, 0) \
  49. func(MMC, mmc, 1) \
  50. func(USB, usb, 0) \
  51. func(DHCP, dhcp, na)
  52. #include <config_distro_bootcmd.h>
  53. #undef CONFIG_BOOTCOMMAND
  54. #define XSPI_NOR_BOOTCOMMAND \
  55. "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
  56. "env exists secureboot && esbc_halt;;"
  57. #define SD_BOOTCOMMAND \
  58. "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
  59. "env exists secureboot && esbc_halt;"
  60. #define SD2_BOOTCOMMAND \
  61. "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
  62. "env exists secureboot && esbc_halt;"
  63. /* Monitor Command Prompt */
  64. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  65. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  66. sizeof(CONFIG_SYS_PROMPT) + 16)
  67. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  68. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  69. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  70. /* MMC */
  71. #ifdef CONFIG_MMC
  72. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  73. #endif
  74. #define CONFIG_SYS_MMC_ENV_DEV 0
  75. #define OCRAM_NONSECURE_SIZE 0x00010000
  76. #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  77. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  78. /* I2C bus multiplexer */
  79. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  80. #define I2C_MUX_CH_DEFAULT 0x8
  81. /* EEPROM */
  82. #define CONFIG_ID_EEPROM
  83. #define CONFIG_SYS_I2C_EEPROM_NXID
  84. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  85. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  86. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  87. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  88. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  89. /* DisplayPort */
  90. #define DP_PWD_EN_DEFAULT_MASK 0x8
  91. #ifdef CONFIG_NXP_ESBC
  92. #include <asm/fsl_secure_boot.h>
  93. #endif
  94. /* Ethernet */
  95. /* smallest ENETC BD ring has 8 entries */
  96. #define CONFIG_SYS_RX_ETH_BUFFER 8
  97. #endif /* __L1028A_COMMON_H */