ls1021atwr.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_PSCI_1_0
  9. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  10. #define CONFIG_SYS_FSL_CLK
  11. #define CONFIG_SKIP_LOWLEVEL_INIT
  12. #define CONFIG_DEEP_SLEEP
  13. /*
  14. * Size of malloc() pool
  15. */
  16. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  17. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  18. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  19. #define CONFIG_SYS_CLK_FREQ 100000000
  20. #define CONFIG_DDR_CLK_FREQ 100000000
  21. #define DDR_SDRAM_CFG 0x470c0008
  22. #define DDR_CS0_BNDS 0x008000bf
  23. #define DDR_CS0_CONFIG 0x80014302
  24. #define DDR_TIMING_CFG_0 0x50550004
  25. #define DDR_TIMING_CFG_1 0xbcb38c56
  26. #define DDR_TIMING_CFG_2 0x0040d120
  27. #define DDR_TIMING_CFG_3 0x010e1000
  28. #define DDR_TIMING_CFG_4 0x00000001
  29. #define DDR_TIMING_CFG_5 0x03401400
  30. #define DDR_SDRAM_CFG_2 0x00401010
  31. #define DDR_SDRAM_MODE 0x00061c60
  32. #define DDR_SDRAM_MODE_2 0x00180000
  33. #define DDR_SDRAM_INTERVAL 0x18600618
  34. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  35. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  36. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  37. #define DDR_DDR_CDR1 0x80040000
  38. #define DDR_DDR_CDR2 0x00000001
  39. #define DDR_SDRAM_CLK_CNTL 0x02000000
  40. #define DDR_DDR_ZQ_CNTL 0x89080600
  41. #define DDR_CS0_CONFIG_2 0
  42. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  43. #define SDRAM_CFG2_D_INIT 0x00000010
  44. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  45. #define SDRAM_CFG2_FRC_SR 0x80000000
  46. #define SDRAM_CFG_BI 0x00000001
  47. #ifdef CONFIG_RAMBOOT_PBL
  48. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
  49. #endif
  50. #ifdef CONFIG_SD_BOOT
  51. #ifdef CONFIG_SD_BOOT_QSPI
  52. #define CONFIG_SYS_FSL_PBL_RCW \
  53. board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  54. #else
  55. #define CONFIG_SYS_FSL_PBL_RCW \
  56. board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  57. #endif
  58. #ifdef CONFIG_NXP_ESBC
  59. /*
  60. * HDR would be appended at end of image and copied to DDR along
  61. * with U-Boot image.
  62. */
  63. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  64. #endif /* ifdef CONFIG_NXP_ESBC */
  65. #define CONFIG_SPL_MAX_SIZE 0x1a000
  66. #define CONFIG_SPL_STACK 0x1001d000
  67. #define CONFIG_SPL_PAD_TO 0x1c000
  68. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  69. CONFIG_SYS_MONITOR_LEN)
  70. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  71. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  72. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  73. #ifdef CONFIG_U_BOOT_HDR_SIZE
  74. /*
  75. * HDR would be appended at end of image and copied to DDR along
  76. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  77. * size increases then increase this size in case of secure boot as
  78. * it uses raw u-boot image instead of fit image.
  79. */
  80. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  81. #else
  82. #define CONFIG_SYS_MONITOR_LEN 0x100000
  83. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  84. #endif
  85. #define PHYS_SDRAM 0x80000000
  86. #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
  87. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  88. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  89. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  90. /*
  91. * IFC Definitions
  92. */
  93. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  94. #define CONFIG_FSL_IFC
  95. #define CONFIG_SYS_FLASH_BASE 0x60000000
  96. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  97. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  98. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  99. CSPR_PORT_SIZE_16 | \
  100. CSPR_MSEL_NOR | \
  101. CSPR_V)
  102. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  103. /* NOR Flash Timing Params */
  104. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  105. CSOR_NOR_TRHZ_80)
  106. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  107. FTIM0_NOR_TEADC(0x5) | \
  108. FTIM0_NOR_TAVDS(0x0) | \
  109. FTIM0_NOR_TEAHC(0x5))
  110. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  111. FTIM1_NOR_TRAD_NOR(0x1A) | \
  112. FTIM1_NOR_TSEQRAD_NOR(0x13))
  113. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  114. FTIM2_NOR_TCH(0x4) | \
  115. FTIM2_NOR_TWP(0x1c) | \
  116. FTIM2_NOR_TWPH(0x0e))
  117. #define CONFIG_SYS_NOR_FTIM3 0
  118. #define CONFIG_SYS_FLASH_QUIET_TEST
  119. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  120. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  121. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  122. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  123. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  124. #define CONFIG_SYS_FLASH_EMPTY_INFO
  125. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  126. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  127. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  128. #endif
  129. /* CPLD */
  130. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  131. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  132. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  133. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  134. CSPR_PORT_SIZE_8 | \
  135. CSPR_MSEL_GPCM | \
  136. CSPR_V)
  137. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  138. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  139. CSOR_NOR_NOR_MODE_AVD_NOR | \
  140. CSOR_NOR_TRHZ_80)
  141. /* CPLD Timing parameters for IFC GPCM */
  142. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  143. FTIM0_GPCM_TEADC(0xf) | \
  144. FTIM0_GPCM_TEAHC(0xf))
  145. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  146. FTIM1_GPCM_TRAD(0x3f))
  147. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  148. FTIM2_GPCM_TCH(0xf) | \
  149. FTIM2_GPCM_TWP(0xff))
  150. #define CONFIG_SYS_FPGA_FTIM3 0x0
  151. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  152. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  153. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  154. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  155. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  156. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  157. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  158. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  159. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
  160. #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
  161. #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
  162. #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
  163. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
  164. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
  165. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
  166. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
  167. /*
  168. * Serial Port
  169. */
  170. #ifdef CONFIG_LPUART
  171. #define CONFIG_LPUART_32B_REG
  172. #else
  173. #define CONFIG_SYS_NS16550_SERIAL
  174. #ifndef CONFIG_DM_SERIAL
  175. #define CONFIG_SYS_NS16550_REG_SIZE 1
  176. #endif
  177. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  178. #endif
  179. /*
  180. * I2C
  181. */
  182. #ifndef CONFIG_DM_I2C
  183. #define CONFIG_SYS_I2C
  184. #else
  185. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  186. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  187. #endif
  188. #define CONFIG_SYS_I2C_MXC
  189. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  190. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  191. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  192. /* EEPROM */
  193. #define CONFIG_ID_EEPROM
  194. #define CONFIG_SYS_I2C_EEPROM_NXID
  195. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  196. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  197. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  198. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  199. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  200. /*
  201. * MMC
  202. */
  203. /*
  204. * Video
  205. */
  206. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  207. #define CONFIG_VIDEO_LOGO
  208. #define CONFIG_VIDEO_BMP_LOGO
  209. #define CONFIG_FSL_DCU_SII9022A
  210. #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
  211. #define CONFIG_SYS_I2C_DVI_ADDR 0x39
  212. #endif
  213. /*
  214. * eTSEC
  215. */
  216. #ifdef CONFIG_TSEC_ENET
  217. #define CONFIG_ETHPRIME "ethernet@2d10000"
  218. #endif
  219. /* PCIe */
  220. #define CONFIG_PCIE1 /* PCIE controller 1 */
  221. #define CONFIG_PCIE2 /* PCIE controller 2 */
  222. #ifdef CONFIG_PCI
  223. #define CONFIG_PCI_SCAN_SHOW
  224. #endif
  225. #define CONFIG_CMDLINE_TAG
  226. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  227. #define CONFIG_LAYERSCAPE_NS_ACCESS
  228. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  229. #define COUNTER_FREQUENCY 12500000
  230. #define CONFIG_HWCONFIG
  231. #define HWCONFIG_BUFFER_SIZE 256
  232. #define CONFIG_FSL_DEVICE_DISABLE
  233. #define BOOT_TARGET_DEVICES(func) \
  234. func(MMC, mmc, 0) \
  235. func(USB, usb, 0) \
  236. func(DHCP, dhcp, na)
  237. #include <config_distro_bootcmd.h>
  238. #ifdef CONFIG_LPUART
  239. #define CONFIG_EXTRA_ENV_SETTINGS \
  240. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
  241. "cma=64M@0x0-0xb0000000\0" \
  242. "initrd_high=0xffffffff\0" \
  243. "fdt_addr=0x64f00000\0" \
  244. "kernel_addr=0x65000000\0" \
  245. "scriptaddr=0x80000000\0" \
  246. "scripthdraddr=0x80080000\0" \
  247. "fdtheader_addr_r=0x80100000\0" \
  248. "kernelheader_addr_r=0x80200000\0" \
  249. "kernel_addr_r=0x81000000\0" \
  250. "fdt_addr_r=0x90000000\0" \
  251. "ramdisk_addr_r=0xa0000000\0" \
  252. "load_addr=0xa0000000\0" \
  253. "kernel_size=0x2800000\0" \
  254. "kernel_addr_sd=0x8000\0" \
  255. "kernel_size_sd=0x14000\0" \
  256. "othbootargs=cma=64M@0x0-0xb0000000\0" \
  257. BOOTENV \
  258. "boot_scripts=ls1021atwr_boot.scr\0" \
  259. "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
  260. "scan_dev_for_boot_part=" \
  261. "part list ${devtype} ${devnum} devplist; " \
  262. "env exists devplist || setenv devplist 1; " \
  263. "for distro_bootpart in ${devplist}; do " \
  264. "if fstype ${devtype} " \
  265. "${devnum}:${distro_bootpart} " \
  266. "bootfstype; then " \
  267. "run scan_dev_for_boot; " \
  268. "fi; " \
  269. "done\0" \
  270. "scan_dev_for_boot=" \
  271. "echo Scanning ${devtype} " \
  272. "${devnum}:${distro_bootpart}...; " \
  273. "for prefix in ${boot_prefixes}; do " \
  274. "run scan_dev_for_scripts; " \
  275. "done;" \
  276. "\0" \
  277. "boot_a_script=" \
  278. "load ${devtype} ${devnum}:${distro_bootpart} " \
  279. "${scriptaddr} ${prefix}${script}; " \
  280. "env exists secureboot && load ${devtype} " \
  281. "${devnum}:${distro_bootpart} " \
  282. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  283. "env exists secureboot " \
  284. "&& esbc_validate ${scripthdraddr};" \
  285. "source ${scriptaddr}\0" \
  286. "installer=load mmc 0:2 $load_addr " \
  287. "/flex_installer_arm32.itb; " \
  288. "bootm $load_addr#ls1021atwr\0" \
  289. "qspi_bootcmd=echo Trying load from qspi..;" \
  290. "sf probe && sf read $load_addr " \
  291. "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
  292. "nor_bootcmd=echo Trying load from nor..;" \
  293. "cp.b $kernel_addr $load_addr " \
  294. "$kernel_size && bootm $load_addr#$board\0"
  295. #else
  296. #define CONFIG_EXTRA_ENV_SETTINGS \
  297. "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
  298. "cma=64M@0x0-0xb0000000\0" \
  299. "initrd_high=0xffffffff\0" \
  300. "fdt_addr=0x64f00000\0" \
  301. "kernel_addr=0x61000000\0" \
  302. "kernelheader_addr=0x60800000\0" \
  303. "scriptaddr=0x80000000\0" \
  304. "scripthdraddr=0x80080000\0" \
  305. "fdtheader_addr_r=0x80100000\0" \
  306. "kernelheader_addr_r=0x80200000\0" \
  307. "kernel_addr_r=0x81000000\0" \
  308. "kernelheader_size=0x40000\0" \
  309. "fdt_addr_r=0x90000000\0" \
  310. "ramdisk_addr_r=0xa0000000\0" \
  311. "load_addr=0xa0000000\0" \
  312. "kernel_size=0x2800000\0" \
  313. "kernel_addr_sd=0x8000\0" \
  314. "kernel_size_sd=0x14000\0" \
  315. "kernelhdr_addr_sd=0x4000\0" \
  316. "kernelhdr_size_sd=0x10\0" \
  317. "othbootargs=cma=64M@0x0-0xb0000000\0" \
  318. BOOTENV \
  319. "boot_scripts=ls1021atwr_boot.scr\0" \
  320. "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
  321. "scan_dev_for_boot_part=" \
  322. "part list ${devtype} ${devnum} devplist; " \
  323. "env exists devplist || setenv devplist 1; " \
  324. "for distro_bootpart in ${devplist}; do " \
  325. "if fstype ${devtype} " \
  326. "${devnum}:${distro_bootpart} " \
  327. "bootfstype; then " \
  328. "run scan_dev_for_boot; " \
  329. "fi; " \
  330. "done\0" \
  331. "scan_dev_for_boot=" \
  332. "echo Scanning ${devtype} " \
  333. "${devnum}:${distro_bootpart}...; " \
  334. "for prefix in ${boot_prefixes}; do " \
  335. "run scan_dev_for_scripts; " \
  336. "done;" \
  337. "\0" \
  338. "boot_a_script=" \
  339. "load ${devtype} ${devnum}:${distro_bootpart} " \
  340. "${scriptaddr} ${prefix}${script}; " \
  341. "env exists secureboot && load ${devtype} " \
  342. "${devnum}:${distro_bootpart} " \
  343. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  344. "&& esbc_validate ${scripthdraddr};" \
  345. "source ${scriptaddr}\0" \
  346. "qspi_bootcmd=echo Trying load from qspi..;" \
  347. "sf probe && sf read $load_addr " \
  348. "$kernel_addr $kernel_size; env exists secureboot " \
  349. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  350. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  351. "bootm $load_addr#$board\0" \
  352. "nor_bootcmd=echo Trying load from nor..;" \
  353. "cp.b $kernel_addr $load_addr " \
  354. "$kernel_size; env exists secureboot " \
  355. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  356. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  357. "bootm $load_addr#$board\0" \
  358. "sd_bootcmd=echo Trying load from SD ..;" \
  359. "mmcinfo && mmc read $load_addr " \
  360. "$kernel_addr_sd $kernel_size_sd && " \
  361. "env exists secureboot && mmc read $kernelheader_addr_r " \
  362. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  363. " && esbc_validate ${kernelheader_addr_r};" \
  364. "bootm $load_addr#$board\0"
  365. #endif
  366. #undef CONFIG_BOOTCOMMAND
  367. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  368. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  369. "env exists secureboot && esbc_halt"
  370. #elif defined(CONFIG_SD_BOOT)
  371. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  372. "env exists secureboot && esbc_halt;"
  373. #else
  374. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
  375. "env exists secureboot && esbc_halt;"
  376. #endif
  377. /*
  378. * Miscellaneous configurable options
  379. */
  380. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  381. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  382. #define CONFIG_LS102XA_STREAM_ID
  383. #define CONFIG_SYS_INIT_SP_OFFSET \
  384. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  385. #define CONFIG_SYS_INIT_SP_ADDR \
  386. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  387. #ifdef CONFIG_SPL_BUILD
  388. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  389. #undef CONFIG_DM_I2C
  390. #else
  391. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  392. #endif
  393. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  394. /*
  395. * Environment
  396. */
  397. #define CONFIG_ENV_OVERWRITE
  398. #if defined(CONFIG_SD_BOOT)
  399. #define CONFIG_SYS_MMC_ENV_DEV 0
  400. #endif
  401. #include <asm/fsl_secure_boot.h>
  402. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  403. #endif