ls1021aqds.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_PSCI_1_0
  9. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  10. #define CONFIG_SYS_FSL_CLK
  11. #define CONFIG_SKIP_LOWLEVEL_INIT
  12. #define CONFIG_DEEP_SLEEP
  13. /*
  14. * Size of malloc() pool
  15. */
  16. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  17. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  18. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  19. #ifndef __ASSEMBLY__
  20. unsigned long get_board_sys_clk(void);
  21. unsigned long get_board_ddr_clk(void);
  22. #endif
  23. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  24. #define CONFIG_SYS_CLK_FREQ 100000000
  25. #define CONFIG_DDR_CLK_FREQ 100000000
  26. #define CONFIG_QIXIS_I2C_ACCESS
  27. #else
  28. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  29. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  30. #endif
  31. #ifdef CONFIG_RAMBOOT_PBL
  32. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
  33. #endif
  34. #ifdef CONFIG_SD_BOOT
  35. #ifdef CONFIG_SD_BOOT_QSPI
  36. #define CONFIG_SYS_FSL_PBL_RCW \
  37. board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  38. #else
  39. #define CONFIG_SYS_FSL_PBL_RCW \
  40. board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  41. #endif
  42. #define CONFIG_SPL_MAX_SIZE 0x1a000
  43. #define CONFIG_SPL_STACK 0x1001d000
  44. #define CONFIG_SPL_PAD_TO 0x1c000
  45. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  46. CONFIG_SYS_MONITOR_LEN)
  47. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  48. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  49. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  50. #define CONFIG_SYS_MONITOR_LEN 0xc0000
  51. #endif
  52. #ifdef CONFIG_NAND_BOOT
  53. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  54. #define CONFIG_SPL_MAX_SIZE 0x1a000
  55. #define CONFIG_SPL_STACK 0x1001d000
  56. #define CONFIG_SPL_PAD_TO 0x1c000
  57. #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
  58. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  59. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  60. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  61. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  62. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  63. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  64. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  65. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  66. #define CONFIG_SYS_MONITOR_LEN 0x80000
  67. #endif
  68. #define CONFIG_DDR_SPD
  69. #define SPD_EEPROM_ADDRESS 0x51
  70. #define CONFIG_SYS_SPD_BUS_NUM 0
  71. #ifndef CONFIG_SYS_FSL_DDR4
  72. #define CONFIG_SYS_DDR_RAW_TIMING
  73. #endif
  74. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  75. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  76. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  77. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  78. #define CONFIG_DDR_ECC
  79. #ifdef CONFIG_DDR_ECC
  80. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  81. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  82. #endif
  83. /*
  84. * IFC Definitions
  85. */
  86. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  87. #define CONFIG_FSL_IFC
  88. #define CONFIG_SYS_FLASH_BASE 0x60000000
  89. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  90. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  91. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  92. CSPR_PORT_SIZE_16 | \
  93. CSPR_MSEL_NOR | \
  94. CSPR_V)
  95. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  96. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  97. + 0x8000000) | \
  98. CSPR_PORT_SIZE_16 | \
  99. CSPR_MSEL_NOR | \
  100. CSPR_V)
  101. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  102. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  103. CSOR_NOR_TRHZ_80)
  104. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  105. FTIM0_NOR_TEADC(0x5) | \
  106. FTIM0_NOR_TEAHC(0x5))
  107. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  108. FTIM1_NOR_TRAD_NOR(0x1a) | \
  109. FTIM1_NOR_TSEQRAD_NOR(0x13))
  110. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  111. FTIM2_NOR_TCH(0x4) | \
  112. FTIM2_NOR_TWPH(0xe) | \
  113. FTIM2_NOR_TWP(0x1c))
  114. #define CONFIG_SYS_NOR_FTIM3 0
  115. #define CONFIG_SYS_FLASH_QUIET_TEST
  116. #define CONFIG_FLASH_SHOW_PROGRESS 45
  117. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  118. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  119. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  120. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  121. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  122. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  123. #define CONFIG_SYS_FLASH_EMPTY_INFO
  124. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  125. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  126. /*
  127. * NAND Flash Definitions
  128. */
  129. #define CONFIG_NAND_FSL_IFC
  130. #define CONFIG_SYS_NAND_BASE 0x7e800000
  131. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  132. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  133. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  134. | CSPR_PORT_SIZE_8 \
  135. | CSPR_MSEL_NAND \
  136. | CSPR_V)
  137. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  138. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  139. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  140. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  141. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  142. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  143. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  144. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  145. #define CONFIG_SYS_NAND_ONFI_DETECTION
  146. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  147. FTIM0_NAND_TWP(0x18) | \
  148. FTIM0_NAND_TWCHT(0x7) | \
  149. FTIM0_NAND_TWH(0xa))
  150. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  151. FTIM1_NAND_TWBE(0x39) | \
  152. FTIM1_NAND_TRR(0xe) | \
  153. FTIM1_NAND_TRP(0x18))
  154. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  155. FTIM2_NAND_TREH(0xa) | \
  156. FTIM2_NAND_TWHRE(0x1e))
  157. #define CONFIG_SYS_NAND_FTIM3 0x0
  158. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  159. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  160. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  161. #endif
  162. /*
  163. * QIXIS Definitions
  164. */
  165. #define CONFIG_FSL_QIXIS
  166. #ifdef CONFIG_FSL_QIXIS
  167. #define QIXIS_BASE 0x7fb00000
  168. #define QIXIS_BASE_PHYS QIXIS_BASE
  169. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  170. #define QIXIS_LBMAP_SWITCH 6
  171. #define QIXIS_LBMAP_MASK 0x0f
  172. #define QIXIS_LBMAP_SHIFT 0
  173. #define QIXIS_LBMAP_DFLTBANK 0x00
  174. #define QIXIS_LBMAP_ALTBANK 0x04
  175. #define QIXIS_PWR_CTL 0x21
  176. #define QIXIS_PWR_CTL_POWEROFF 0x80
  177. #define QIXIS_RST_CTL_RESET 0x44
  178. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  179. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  180. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  181. #define QIXIS_CTL_SYS 0x5
  182. #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
  183. #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
  184. #define QIXIS_RST_FORCE_3 0x45
  185. #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
  186. #define QIXIS_PWR_CTL2 0x21
  187. #define QIXIS_PWR_CTL2_PCTL 0x2
  188. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  189. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  190. CSPR_PORT_SIZE_8 | \
  191. CSPR_MSEL_GPCM | \
  192. CSPR_V)
  193. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  194. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  195. CSOR_NOR_NOR_MODE_AVD_NOR | \
  196. CSOR_NOR_TRHZ_80)
  197. /*
  198. * QIXIS Timing parameters for IFC GPCM
  199. */
  200. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
  201. FTIM0_GPCM_TEADC(0xe) | \
  202. FTIM0_GPCM_TEAHC(0xe))
  203. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
  204. FTIM1_GPCM_TRAD(0x1f))
  205. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
  206. FTIM2_GPCM_TCH(0xe) | \
  207. FTIM2_GPCM_TWP(0xf0))
  208. #define CONFIG_SYS_FPGA_FTIM3 0x0
  209. #endif
  210. #if defined(CONFIG_NAND_BOOT)
  211. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  212. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  213. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  214. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  215. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  216. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  217. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  218. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  219. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  220. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  221. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  222. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  223. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  224. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  225. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  226. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  227. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  228. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  229. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  230. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  231. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  232. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  233. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  234. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  235. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  236. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  237. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  238. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  239. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  240. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  241. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  242. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  243. #else
  244. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  245. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  246. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  247. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  248. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  249. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  250. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  251. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  252. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  253. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  254. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  255. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  256. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  257. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  258. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  259. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  260. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  261. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  262. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  263. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  264. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  265. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  266. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  267. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  268. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  269. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  270. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  271. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  272. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  273. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  274. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  275. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  276. #endif
  277. /*
  278. * Serial Port
  279. */
  280. #ifdef CONFIG_LPUART
  281. #define CONFIG_LPUART_32B_REG
  282. #else
  283. #define CONFIG_SYS_NS16550_SERIAL
  284. #ifndef CONFIG_DM_SERIAL
  285. #define CONFIG_SYS_NS16550_REG_SIZE 1
  286. #endif
  287. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  288. #endif
  289. /*
  290. * I2C
  291. */
  292. #ifndef CONFIG_DM_I2C
  293. #define CONFIG_SYS_I2C
  294. #else
  295. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  296. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  297. #endif
  298. #define CONFIG_SYS_I2C_MXC
  299. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  300. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  301. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  302. /* EEPROM */
  303. #define CONFIG_ID_EEPROM
  304. #define CONFIG_SYS_I2C_EEPROM_NXID
  305. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  306. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  307. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  308. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  309. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  310. /*
  311. * I2C bus multiplexer
  312. */
  313. #define I2C_MUX_PCA_ADDR_PRI 0x77
  314. #define I2C_MUX_CH_DEFAULT 0x8
  315. #define I2C_MUX_CH_CH7301 0xC
  316. /*
  317. * MMC
  318. */
  319. /*
  320. * Video
  321. */
  322. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  323. #define CONFIG_VIDEO_LOGO
  324. #define CONFIG_VIDEO_BMP_LOGO
  325. #define CONFIG_FSL_DIU_CH7301
  326. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  327. #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
  328. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  329. #endif
  330. /*
  331. * eTSEC
  332. */
  333. #ifdef CONFIG_TSEC_ENET
  334. #define CONFIG_MII_DEFAULT_TSEC 3
  335. #define CONFIG_TSEC1 1
  336. #define CONFIG_TSEC1_NAME "eTSEC1"
  337. #define CONFIG_TSEC2 1
  338. #define CONFIG_TSEC2_NAME "eTSEC2"
  339. #define CONFIG_TSEC3 1
  340. #define CONFIG_TSEC3_NAME "eTSEC3"
  341. #define TSEC1_PHY_ADDR 1
  342. #define TSEC2_PHY_ADDR 2
  343. #define TSEC3_PHY_ADDR 3
  344. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  345. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  346. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  347. #define TSEC1_PHYIDX 0
  348. #define TSEC2_PHYIDX 0
  349. #define TSEC3_PHYIDX 0
  350. #define CONFIG_ETHPRIME "eTSEC1"
  351. #define CONFIG_HAS_ETH0
  352. #define CONFIG_HAS_ETH1
  353. #define CONFIG_HAS_ETH2
  354. #define CONFIG_FSL_SGMII_RISER 1
  355. #define SGMII_RISER_PHY_OFFSET 0x1b
  356. #ifdef CONFIG_FSL_SGMII_RISER
  357. #define CONFIG_SYS_TBIPA_VALUE 8
  358. #endif
  359. #endif
  360. /* PCIe */
  361. #define CONFIG_PCIE1 /* PCIE controller 1 */
  362. #define CONFIG_PCIE2 /* PCIE controller 2 */
  363. #ifdef CONFIG_PCI
  364. #define CONFIG_PCI_SCAN_SHOW
  365. #endif
  366. #define CONFIG_CMDLINE_TAG
  367. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  368. #define CONFIG_LAYERSCAPE_NS_ACCESS
  369. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  370. #define COUNTER_FREQUENCY 12500000
  371. #define CONFIG_HWCONFIG
  372. #define HWCONFIG_BUFFER_SIZE 256
  373. #define CONFIG_FSL_DEVICE_DISABLE
  374. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  375. #ifdef CONFIG_LPUART
  376. #define CONFIG_EXTRA_ENV_SETTINGS \
  377. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
  378. "initrd_high=0xffffffff\0" \
  379. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  380. #else
  381. #define CONFIG_EXTRA_ENV_SETTINGS \
  382. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  383. "initrd_high=0xffffffff\0" \
  384. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  385. #endif
  386. /*
  387. * Miscellaneous configurable options
  388. */
  389. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  390. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  391. #define CONFIG_LS102XA_STREAM_ID
  392. #define CONFIG_SYS_INIT_SP_OFFSET \
  393. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  394. #define CONFIG_SYS_INIT_SP_ADDR \
  395. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  396. #ifdef CONFIG_SPL_BUILD
  397. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  398. #else
  399. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  400. #endif
  401. /*
  402. * Environment
  403. */
  404. #define CONFIG_ENV_OVERWRITE
  405. #if defined(CONFIG_SD_BOOT)
  406. #define CONFIG_SYS_MMC_ENV_DEV 0
  407. #endif
  408. #include <asm/fsl_secure_boot.h>
  409. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  410. #endif