da850evm.h 6.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on davinci_dvevm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * Board
  13. */
  14. /*
  15. * SoC Configuration
  16. */
  17. #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  18. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  19. #define CONFIG_SYS_OSCIN_FREQ 24000000
  20. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  21. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  22. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  23. #ifdef CONFIG_MTD_NOR_FLASH
  24. #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
  25. #endif
  26. /*
  27. * Memory Info
  28. */
  29. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  30. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  31. #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
  32. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  33. #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  34. #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  35. /* memtest start addr */
  36. /* memtest will be run on 16MB */
  37. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  38. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  39. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  40. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  41. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  42. DAVINCI_SYSCFG_SUSPSRC_I2C)
  43. /*
  44. * PLL configuration
  45. */
  46. #define CONFIG_SYS_DA850_PLL0_PLLM 24
  47. #define CONFIG_SYS_DA850_PLL1_PLLM 21
  48. /*
  49. * DDR2 memory configuration
  50. */
  51. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  52. DV_DDR_PHY_EXT_STRBEN | \
  53. (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  54. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  55. (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
  56. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  57. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  58. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  59. (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
  60. (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
  61. (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  62. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  63. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  64. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  65. (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  66. (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
  67. (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  68. (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
  69. (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  70. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  71. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  72. (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  73. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  74. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  75. (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
  76. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  77. (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  78. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  79. (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  80. (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  81. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
  82. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  83. /*
  84. * Serial Driver info
  85. */
  86. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  87. #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
  88. /*
  89. * I2C Configuration
  90. */
  91. #ifndef CONFIG_SPL_BUILD
  92. #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
  93. #endif
  94. /*
  95. * Flash & Environment
  96. */
  97. #ifdef CONFIG_MTD_RAW_NAND
  98. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  99. #define CONFIG_SYS_NAND_PAGE_2K
  100. #define CONFIG_SYS_NAND_CS 3
  101. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  102. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  103. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  104. #undef CONFIG_SYS_NAND_HW_ECC
  105. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  106. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  107. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  108. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  109. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  110. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
  111. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  112. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  113. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  114. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  115. CONFIG_SYS_MALLOC_LEN - \
  116. GENERATED_GBL_DATA_SIZE)
  117. #define CONFIG_SYS_NAND_ECCPOS { \
  118. 24, 25, 26, 27, 28, \
  119. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
  120. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
  121. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
  122. 59, 60, 61, 62, 63 }
  123. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  124. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  125. #define CONFIG_SYS_NAND_ECCSIZE 512
  126. #define CONFIG_SYS_NAND_ECCBYTES 10
  127. #define CONFIG_SYS_NAND_OOBSIZE 64
  128. #define CONFIG_SPL_NAND_BASE
  129. #define CONFIG_SPL_NAND_DRIVERS
  130. #define CONFIG_SPL_NAND_ECC
  131. #define CONFIG_SPL_NAND_LOAD
  132. #ifndef CONFIG_SPL_BUILD
  133. #define CONFIG_SYS_NAND_SELF_INIT
  134. #endif
  135. #endif
  136. /*
  137. * Network & Ethernet Configuration
  138. */
  139. #ifdef CONFIG_DRIVER_TI_EMAC
  140. #define CONFIG_BOOTP_SEND_HOSTNAME
  141. #define CONFIG_NET_RETRY_COUNT 10
  142. #endif
  143. #ifdef CONFIG_MTD_NOR_FLASH
  144. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  145. #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
  146. #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
  147. #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
  148. #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
  149. + 3)
  150. #endif
  151. /*
  152. * U-Boot general configuration
  153. */
  154. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  155. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  156. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  157. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  158. /*
  159. * Linux Information
  160. */
  161. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  162. #define CONFIG_HWCONFIG /* enable hwconfig */
  163. #define CONFIG_CMDLINE_TAG
  164. #define CONFIG_REVISION_TAG
  165. #define CONFIG_SETUP_MEMORY_TAGS
  166. #define CONFIG_BOOTCOMMAND \
  167. "run envboot; " \
  168. "run mmcboot; "
  169. #define DEFAULT_LINUX_BOOT_ENV \
  170. "loadaddr=0xc0700000\0" \
  171. "fdtaddr=0xc0600000\0" \
  172. "scriptaddr=0xc0600000\0"
  173. #include <environment/ti/mmc.h>
  174. #define CONFIG_EXTRA_ENV_SETTINGS \
  175. DEFAULT_LINUX_BOOT_ENV \
  176. DEFAULT_MMC_TI_ARGS \
  177. "bootpart=0:2\0" \
  178. "bootdir=/boot\0" \
  179. "bootfile=zImage\0" \
  180. "fdtfile=da850-evm.dtb\0" \
  181. "boot_fdt=yes\0" \
  182. "boot_fit=0\0" \
  183. "console=ttyS2,115200n8\0" \
  184. "hwconfig=dsp:wake=yes"
  185. #ifdef CONFIG_CMD_BDI
  186. #define CONFIG_CLOCKS
  187. #endif
  188. /* USB Configs */
  189. #define CONFIG_USB_OHCI_NEW
  190. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  191. #ifdef CONFIG_SPL_BUILD
  192. /* defines for SPL */
  193. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  194. CONFIG_SYS_MALLOC_LEN)
  195. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  196. #define CONFIG_SPL_STACK 0x8001ff00
  197. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  198. #define CONFIG_SPL_PAD_TO 32768
  199. #endif
  200. /* Load U-Boot Image From MMC */
  201. /* additions for new relocation code, must added to all boards */
  202. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  203. #ifdef CONFIG_MTD_NOR_FLASH
  204. #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
  205. #else
  206. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  207. GENERATED_GBL_DATA_SIZE)
  208. #endif /* CONFIG_MTD_NOR_FLASH */
  209. #include <asm/arch/hardware.h>
  210. #endif /* __CONFIG_H */