cyrus.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Based on corenet_ds.h
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #include <linux/stringify.h>
  8. #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  9. #error Must call Cyrus CONFIG with a specific CPU enabled.
  10. #endif
  11. #define CONFIG_SDCARD
  12. #define CONFIG_FSL_SATA_V2
  13. #define CONFIG_PCIE3
  14. #define CONFIG_PCIE4
  15. #ifdef CONFIG_ARCH_P5020
  16. #define CONFIG_SYS_FSL_RAID_ENGINE
  17. #define CONFIG_SYS_DPAA_RMAN
  18. #endif
  19. #define CONFIG_SYS_DPAA_PME
  20. /*
  21. * Corenet DS style board configuration file
  22. */
  23. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  24. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25. #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  26. #if defined(CONFIG_ARCH_P5020)
  27. #define CONFIG_SYS_CLK_FREQ 133000000
  28. #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  29. #elif defined(CONFIG_ARCH_P5040)
  30. #define CONFIG_SYS_CLK_FREQ 100000000
  31. #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  32. #endif
  33. /* High Level Configuration Options */
  34. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  35. #define CONFIG_SYS_MMC_MAX_DEVICE 1
  36. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  37. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  38. #define CONFIG_PCIE1 /* PCIE controller 1 */
  39. #define CONFIG_PCIE2 /* PCIE controller 2 */
  40. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  41. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  42. #define CONFIG_ENV_OVERWRITE
  43. #if defined(CONFIG_SDCARD)
  44. #define CONFIG_FSL_FIXED_MMC_LOCATION
  45. #define CONFIG_SYS_MMC_ENV_DEV 0
  46. #endif
  47. /*
  48. * These can be toggled for performance analysis, otherwise use default.
  49. */
  50. #define CONFIG_SYS_CACHE_STASHING
  51. #define CONFIG_BACKSIDE_L2_CACHE
  52. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  53. #define CONFIG_BTB /* toggle branch predition */
  54. #define CONFIG_DDR_ECC
  55. #ifdef CONFIG_DDR_ECC
  56. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  57. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  58. #endif
  59. #define CONFIG_ENABLE_36BIT_PHYS
  60. /* test POST memory test */
  61. #undef CONFIG_POST
  62. /*
  63. * Config the L3 Cache as L3 SRAM
  64. */
  65. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  66. #ifdef CONFIG_PHYS_64BIT
  67. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  68. #else
  69. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  70. #endif
  71. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  72. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  73. #ifdef CONFIG_PHYS_64BIT
  74. #define CONFIG_SYS_DCSRBAR 0xf0000000
  75. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  76. #endif
  77. /*
  78. * DDR Setup
  79. */
  80. #define CONFIG_VERY_BIG_RAM
  81. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  82. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  83. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  84. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  85. #define CONFIG_DDR_SPD
  86. #define CONFIG_SYS_SPD_BUS_NUM 1
  87. #define SPD_EEPROM_ADDRESS1 0x51
  88. #define SPD_EEPROM_ADDRESS2 0x52
  89. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  90. /*
  91. * Local Bus Definitions
  92. */
  93. #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
  94. #ifdef CONFIG_PHYS_64BIT
  95. #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
  96. #else
  97. #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
  98. #endif
  99. #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
  100. #ifdef CONFIG_PHYS_64BIT
  101. #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
  102. #else
  103. #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
  104. #endif
  105. /* Set the local bus clock 1/16 of platform clock */
  106. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
  107. #define CONFIG_SYS_BR0_PRELIM \
  108. (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
  109. #define CONFIG_SYS_BR1_PRELIM \
  110. (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
  111. #define CONFIG_SYS_OR0_PRELIM 0xfff00010
  112. #define CONFIG_SYS_OR1_PRELIM 0xfff00010
  113. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  114. #if defined(CONFIG_RAMBOOT_PBL)
  115. #define CONFIG_SYS_RAMBOOT
  116. #endif
  117. #define CONFIG_HWCONFIG
  118. /* define to use L1 as initial stack */
  119. #define CONFIG_L1_INIT_RAM
  120. #define CONFIG_SYS_INIT_RAM_LOCK
  121. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  122. #ifdef CONFIG_PHYS_64BIT
  123. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  124. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  125. /* The assembler doesn't like typecast */
  126. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  127. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  128. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  129. #else
  130. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  131. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  132. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  133. #endif
  134. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  135. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  136. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  137. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  138. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  139. /* Serial Port - controlled on board with jumper J8
  140. * open - index 2
  141. * shorted - index 1
  142. */
  143. #define CONFIG_SYS_NS16550_SERIAL
  144. #define CONFIG_SYS_NS16550_REG_SIZE 1
  145. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  146. #define CONFIG_SYS_BAUDRATE_TABLE \
  147. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  148. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  149. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  150. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  151. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  152. /* I2C */
  153. #define CONFIG_SYS_I2C
  154. #define CONFIG_SYS_I2C_FSL
  155. #define CONFIG_I2C_MULTI_BUS
  156. #define CONFIG_I2C_CMD_TREE
  157. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
  158. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  159. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  160. #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
  161. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  162. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  163. #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
  164. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  165. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  166. #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
  167. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  168. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  169. #define CONFIG_ID_EEPROM
  170. #define CONFIG_SYS_I2C_EEPROM_NXID
  171. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  172. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  173. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  174. #define CONFIG_SYS_I2C_GENERIC_MAC
  175. #define CONFIG_SYS_I2C_MAC1_BUS 3
  176. #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
  177. #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
  178. #define CONFIG_SYS_I2C_MAC2_BUS 0
  179. #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
  180. #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
  181. #define CONFIG_RTC_MCP79411 1
  182. #define CONFIG_SYS_RTC_BUS_NUM 3
  183. #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
  184. /*
  185. * eSPI - Enhanced SPI
  186. */
  187. /*
  188. * General PCI
  189. * Memory space is mapped 1-1, but I/O space must start from 0.
  190. */
  191. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  192. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  193. #ifdef CONFIG_PHYS_64BIT
  194. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  195. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  196. #else
  197. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  198. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  199. #endif
  200. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  201. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  202. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  203. #ifdef CONFIG_PHYS_64BIT
  204. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  205. #else
  206. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  207. #endif
  208. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  209. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  210. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  211. #ifdef CONFIG_PHYS_64BIT
  212. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  213. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  214. #else
  215. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  216. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  217. #endif
  218. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  219. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  220. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  221. #ifdef CONFIG_PHYS_64BIT
  222. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  223. #else
  224. #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  225. #endif
  226. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  227. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  228. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  229. #ifdef CONFIG_PHYS_64BIT
  230. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  231. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  232. #else
  233. #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
  234. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
  235. #endif
  236. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  237. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  238. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  239. #ifdef CONFIG_PHYS_64BIT
  240. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  241. #else
  242. #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  243. #endif
  244. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  245. /* controller 4, Base address 203000 */
  246. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  247. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  248. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  249. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  250. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  251. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  252. /* Qman/Bman */
  253. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  254. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  255. #ifdef CONFIG_PHYS_64BIT
  256. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  257. #else
  258. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  259. #endif
  260. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  261. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  262. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  263. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  264. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  265. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  266. CONFIG_SYS_BMAN_CENA_SIZE)
  267. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  268. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  269. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  270. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  271. #ifdef CONFIG_PHYS_64BIT
  272. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  273. #else
  274. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  275. #endif
  276. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  277. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  278. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  279. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  280. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  281. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  282. CONFIG_SYS_QMAN_CENA_SIZE)
  283. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  284. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  285. #define CONFIG_SYS_DPAA_FMAN
  286. /* Default address of microcode for the Linux Fman driver */
  287. /*
  288. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  289. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  290. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  291. */
  292. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  293. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  294. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  295. #ifdef CONFIG_PCI
  296. #define CONFIG_PCI_INDIRECT_BRIDGE
  297. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  298. #endif /* CONFIG_PCI */
  299. /* SATA */
  300. #ifdef CONFIG_FSL_SATA_V2
  301. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  302. #define CONFIG_SATA1
  303. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  304. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  305. #define CONFIG_SATA2
  306. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  307. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  308. #define CONFIG_LBA48
  309. #endif
  310. #ifdef CONFIG_FMAN_ENET
  311. #define CONFIG_SYS_TBIPA_VALUE 8
  312. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  313. #endif
  314. /*
  315. * Environment
  316. */
  317. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  318. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  319. /*
  320. * USB
  321. */
  322. #define CONFIG_HAS_FSL_DR_USB
  323. #define CONFIG_HAS_FSL_MPH_USB
  324. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  325. #define CONFIG_USB_EHCI_FSL
  326. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  327. #define CONFIG_EHCI_IS_TDI
  328. /* _VIA_CONTROL_EP */
  329. #endif
  330. #ifdef CONFIG_MMC
  331. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  332. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  333. #endif
  334. /*
  335. * Miscellaneous configurable options
  336. */
  337. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  338. /*
  339. * For booting Linux, the board info and command line data
  340. * have to be in the first 64 MB of memory, since this is
  341. * the maximum mapped by the Linux kernel during initialization.
  342. */
  343. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  344. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  345. #ifdef CONFIG_CMD_KGDB
  346. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  347. #endif
  348. /*
  349. * Environment Configuration
  350. */
  351. #define CONFIG_ROOTPATH "/opt/nfsroot"
  352. #define CONFIG_BOOTFILE "uImage"
  353. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  354. /* default location for tftp and bootm */
  355. #define CONFIG_LOADADDR 1000000
  356. #define __USB_PHY_TYPE utmi
  357. #define CONFIG_EXTRA_ENV_SETTINGS \
  358. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  359. "bank_intlv=cs0_cs1;" \
  360. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  361. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  362. "netdev=eth0\0" \
  363. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  364. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  365. "consoledev=ttyS0\0" \
  366. "ramdiskaddr=2000000\0" \
  367. "fdtaddr=1e00000\0" \
  368. "bdev=sda3\0"
  369. #define CONFIG_HDBOOT \
  370. "setenv bootargs root=/dev/$bdev rw " \
  371. "console=$consoledev,$baudrate $othbootargs;" \
  372. "tftp $loadaddr $bootfile;" \
  373. "tftp $fdtaddr $fdtfile;" \
  374. "bootm $loadaddr - $fdtaddr"
  375. #define CONFIG_NFSBOOTCOMMAND \
  376. "setenv bootargs root=/dev/nfs rw " \
  377. "nfsroot=$serverip:$rootpath " \
  378. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  379. "console=$consoledev,$baudrate $othbootargs;" \
  380. "tftp $loadaddr $bootfile;" \
  381. "tftp $fdtaddr $fdtfile;" \
  382. "bootm $loadaddr - $fdtaddr"
  383. #define CONFIG_RAMBOOTCOMMAND \
  384. "setenv bootargs root=/dev/ram rw " \
  385. "console=$consoledev,$baudrate $othbootargs;" \
  386. "tftp $ramdiskaddr $ramdiskfile;" \
  387. "tftp $loadaddr $bootfile;" \
  388. "tftp $fdtaddr $fdtfile;" \
  389. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  390. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  391. #include <asm/fsl_secure_boot.h>
  392. #endif /* __CONFIG_H */