corenet_ds.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * Corenet DS style board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #include "../board/freescale/common/ics307_clk.h"
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #ifdef CONFIG_NXP_ESBC
  15. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  16. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  17. #ifdef CONFIG_MTD_RAW_NAND
  18. #define CONFIG_RAMBOOT_NAND
  19. #endif
  20. #define CONFIG_BOOTSCRIPT_COPY_RAM
  21. #else
  22. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  25. #if defined(CONFIG_TARGET_P3041DS)
  26. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  27. #elif defined(CONFIG_TARGET_P4080DS)
  28. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  29. #elif defined(CONFIG_TARGET_P5020DS)
  30. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  31. #elif defined(CONFIG_TARGET_P5040DS)
  32. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  33. #endif
  34. #endif
  35. #endif
  36. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  37. /* Set 1M boot space */
  38. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  39. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  40. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  41. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  42. #endif
  43. /* High Level Configuration Options */
  44. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  45. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  47. #endif
  48. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  49. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  50. #define CONFIG_PCIE1 /* PCIE controller 1 */
  51. #define CONFIG_PCIE2 /* PCIE controller 2 */
  52. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  53. #define CONFIG_ENV_OVERWRITE
  54. #if defined(CONFIG_SPIFLASH)
  55. #elif defined(CONFIG_SDCARD)
  56. #define CONFIG_FSL_FIXED_MMC_LOCATION
  57. #define CONFIG_SYS_MMC_ENV_DEV 0
  58. #endif
  59. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  60. /*
  61. * These can be toggled for performance analysis, otherwise use default.
  62. */
  63. #define CONFIG_SYS_CACHE_STASHING
  64. #define CONFIG_BACKSIDE_L2_CACHE
  65. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  66. #define CONFIG_BTB /* toggle branch predition */
  67. #define CONFIG_DDR_ECC
  68. #ifdef CONFIG_DDR_ECC
  69. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  70. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  71. #endif
  72. #define CONFIG_ENABLE_36BIT_PHYS
  73. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  74. /*
  75. * Config the L3 Cache as L3 SRAM
  76. */
  77. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  78. #ifdef CONFIG_PHYS_64BIT
  79. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  80. #else
  81. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  82. #endif
  83. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  84. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  85. #ifdef CONFIG_PHYS_64BIT
  86. #define CONFIG_SYS_DCSRBAR 0xf0000000
  87. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  88. #endif
  89. /* EEPROM */
  90. #define CONFIG_ID_EEPROM
  91. #define CONFIG_SYS_I2C_EEPROM_NXID
  92. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  93. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  94. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  95. /*
  96. * DDR Setup
  97. */
  98. #define CONFIG_VERY_BIG_RAM
  99. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  100. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  101. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  102. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  103. #define CONFIG_DDR_SPD
  104. #define CONFIG_SYS_SPD_BUS_NUM 1
  105. #define SPD_EEPROM_ADDRESS1 0x51
  106. #define SPD_EEPROM_ADDRESS2 0x52
  107. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  108. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  109. /*
  110. * Local Bus Definitions
  111. */
  112. /* Set the local bus clock 1/8 of platform clock */
  113. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  114. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
  115. #ifdef CONFIG_PHYS_64BIT
  116. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  117. #else
  118. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  119. #endif
  120. #define CONFIG_SYS_FLASH_BR_PRELIM \
  121. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  122. | BR_PS_16 | BR_V)
  123. #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  124. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  125. #define CONFIG_SYS_BR1_PRELIM \
  126. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  127. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  128. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  129. #ifdef CONFIG_PHYS_64BIT
  130. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  131. #else
  132. #define PIXIS_BASE_PHYS PIXIS_BASE
  133. #endif
  134. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  135. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  136. #define PIXIS_LBMAP_SWITCH 7
  137. #define PIXIS_LBMAP_MASK 0xf0
  138. #define PIXIS_LBMAP_SHIFT 4
  139. #define PIXIS_LBMAP_ALTBANK 0x40
  140. #define CONFIG_SYS_FLASH_QUIET_TEST
  141. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  142. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  143. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  144. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  145. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  146. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  147. #if defined(CONFIG_RAMBOOT_PBL)
  148. #define CONFIG_SYS_RAMBOOT
  149. #endif
  150. /* Nand Flash */
  151. #ifdef CONFIG_NAND_FSL_ELBC
  152. #define CONFIG_SYS_NAND_BASE 0xffa00000
  153. #ifdef CONFIG_PHYS_64BIT
  154. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  155. #else
  156. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  157. #endif
  158. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  159. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  160. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  161. /* NAND flash config */
  162. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  163. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  164. | BR_PS_8 /* Port Size = 8 bit */ \
  165. | BR_MS_FCM /* MSEL = FCM */ \
  166. | BR_V) /* valid */
  167. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  168. | OR_FCM_PGS /* Large Page*/ \
  169. | OR_FCM_CSCT \
  170. | OR_FCM_CST \
  171. | OR_FCM_CHT \
  172. | OR_FCM_SCY_1 \
  173. | OR_FCM_TRLX \
  174. | OR_FCM_EHTR)
  175. #ifdef CONFIG_MTD_RAW_NAND
  176. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  177. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  178. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  179. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  180. #else
  181. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  182. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  183. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  184. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  185. #endif
  186. #else
  187. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  188. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  189. #endif /* CONFIG_NAND_FSL_ELBC */
  190. #define CONFIG_SYS_FLASH_EMPTY_INFO
  191. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  192. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  193. #define CONFIG_HWCONFIG
  194. /* define to use L1 as initial stack */
  195. #define CONFIG_L1_INIT_RAM
  196. #define CONFIG_SYS_INIT_RAM_LOCK
  197. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  198. #ifdef CONFIG_PHYS_64BIT
  199. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  200. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  201. /* The assembler doesn't like typecast */
  202. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  203. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  204. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  205. #else
  206. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  207. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  208. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  209. #endif
  210. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  211. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  212. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  213. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  214. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  215. /* Serial Port - controlled on board with jumper J8
  216. * open - index 2
  217. * shorted - index 1
  218. */
  219. #define CONFIG_SYS_NS16550_SERIAL
  220. #define CONFIG_SYS_NS16550_REG_SIZE 1
  221. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  222. #define CONFIG_SYS_BAUDRATE_TABLE \
  223. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  224. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  225. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  226. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  227. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  228. /* I2C */
  229. #ifndef CONFIG_DM_I2C
  230. #define CONFIG_SYS_I2C
  231. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  232. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  233. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  234. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  235. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  236. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  237. #else
  238. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  239. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  240. #endif
  241. #define CONFIG_SYS_I2C_FSL
  242. /*
  243. * RapidIO
  244. */
  245. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  246. #ifdef CONFIG_PHYS_64BIT
  247. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  248. #else
  249. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  250. #endif
  251. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  252. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  253. #ifdef CONFIG_PHYS_64BIT
  254. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  255. #else
  256. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  257. #endif
  258. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  259. /*
  260. * for slave u-boot IMAGE instored in master memory space,
  261. * PHYS must be aligned based on the SIZE
  262. */
  263. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  264. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  265. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  266. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  267. /*
  268. * for slave UCODE and ENV instored in master memory space,
  269. * PHYS must be aligned based on the SIZE
  270. */
  271. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  272. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  273. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  274. /* slave core release by master*/
  275. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  276. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  277. /*
  278. * SRIO_PCIE_BOOT - SLAVE
  279. */
  280. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  281. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  282. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  283. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  284. #endif
  285. /*
  286. * eSPI - Enhanced SPI
  287. */
  288. /*
  289. * General PCI
  290. * Memory space is mapped 1-1, but I/O space must start from 0.
  291. */
  292. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  293. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  294. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  295. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  296. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  297. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  298. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  299. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  300. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  301. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  302. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  303. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  304. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  305. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  306. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  307. /* controller 4, Base address 203000 */
  308. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  309. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  310. /* Qman/Bman */
  311. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  312. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  313. #ifdef CONFIG_PHYS_64BIT
  314. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  315. #else
  316. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  317. #endif
  318. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  319. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  320. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  321. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  322. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  323. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  324. CONFIG_SYS_BMAN_CENA_SIZE)
  325. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  326. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  327. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  328. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  329. #ifdef CONFIG_PHYS_64BIT
  330. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  331. #else
  332. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  333. #endif
  334. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  335. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  336. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  337. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  338. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  339. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  340. CONFIG_SYS_QMAN_CENA_SIZE)
  341. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  342. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  343. #define CONFIG_SYS_DPAA_FMAN
  344. #define CONFIG_SYS_DPAA_PME
  345. /* Default address of microcode for the Linux Fman driver */
  346. #if defined(CONFIG_SPIFLASH)
  347. /*
  348. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  349. * env, so we got 0x110000.
  350. */
  351. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  352. #elif defined(CONFIG_SDCARD)
  353. /*
  354. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  355. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  356. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  357. */
  358. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  359. #elif defined(CONFIG_MTD_RAW_NAND)
  360. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  361. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  362. /*
  363. * Slave has no ucode locally, it can fetch this from remote. When implementing
  364. * in two corenet boards, slave's ucode could be stored in master's memory
  365. * space, the address can be mapped from slave TLB->slave LAW->
  366. * slave SRIO or PCIE outbound window->master inbound window->
  367. * master LAW->the ucode address in master's memory space.
  368. */
  369. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  370. #else
  371. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  372. #endif
  373. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  374. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  375. #ifdef CONFIG_PCI
  376. #if !defined(CONFIG_DM_PCI)
  377. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  378. #define CONFIG_PCI_INDIRECT_BRIDGE
  379. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  380. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  381. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  382. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  383. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  384. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  385. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  386. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  387. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  388. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  389. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  390. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  391. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  392. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  393. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  394. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  395. #endif
  396. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  397. #endif /* CONFIG_PCI */
  398. /* SATA */
  399. #ifdef CONFIG_FSL_SATA_V2
  400. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  401. #define CONFIG_SATA1
  402. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  403. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  404. #define CONFIG_SATA2
  405. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  406. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  407. #define CONFIG_LBA48
  408. #endif
  409. #ifdef CONFIG_FMAN_ENET
  410. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
  411. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
  412. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
  413. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
  414. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
  415. #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
  416. #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
  417. #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
  418. #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
  419. #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
  420. #define CONFIG_SYS_TBIPA_VALUE 8
  421. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  422. #endif
  423. /*
  424. * Environment
  425. */
  426. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  427. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  428. /*
  429. * USB
  430. */
  431. #define CONFIG_HAS_FSL_DR_USB
  432. #define CONFIG_HAS_FSL_MPH_USB
  433. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  434. #define CONFIG_USB_EHCI_FSL
  435. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  436. #endif
  437. #ifdef CONFIG_MMC
  438. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  439. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  440. #endif
  441. /*
  442. * Miscellaneous configurable options
  443. */
  444. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  445. /*
  446. * For booting Linux, the board info and command line data
  447. * have to be in the first 64 MB of memory, since this is
  448. * the maximum mapped by the Linux kernel during initialization.
  449. */
  450. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  451. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  452. #ifdef CONFIG_CMD_KGDB
  453. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  454. #endif
  455. /*
  456. * Environment Configuration
  457. */
  458. #define CONFIG_ROOTPATH "/opt/nfsroot"
  459. #define CONFIG_BOOTFILE "uImage"
  460. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  461. /* default location for tftp and bootm */
  462. #define CONFIG_LOADADDR 1000000
  463. #ifdef CONFIG_TARGET_P4080DS
  464. #define __USB_PHY_TYPE ulpi
  465. #else
  466. #define __USB_PHY_TYPE utmi
  467. #endif
  468. #define CONFIG_EXTRA_ENV_SETTINGS \
  469. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  470. "bank_intlv=cs0_cs1;" \
  471. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  472. "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  473. "netdev=eth0\0" \
  474. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  475. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  476. "tftpflash=tftpboot $loadaddr $uboot && " \
  477. "protect off $ubootaddr +$filesize && " \
  478. "erase $ubootaddr +$filesize && " \
  479. "cp.b $loadaddr $ubootaddr $filesize && " \
  480. "protect on $ubootaddr +$filesize && " \
  481. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  482. "consoledev=ttyS0\0" \
  483. "ramdiskaddr=2000000\0" \
  484. "ramdiskfile=p4080ds/ramdisk.uboot\0" \
  485. "fdtaddr=1e00000\0" \
  486. "fdtfile=p4080ds/p4080ds.dtb\0" \
  487. "bdev=sda3\0"
  488. #define CONFIG_HDBOOT \
  489. "setenv bootargs root=/dev/$bdev rw " \
  490. "console=$consoledev,$baudrate $othbootargs;" \
  491. "tftp $loadaddr $bootfile;" \
  492. "tftp $fdtaddr $fdtfile;" \
  493. "bootm $loadaddr - $fdtaddr"
  494. #define CONFIG_NFSBOOTCOMMAND \
  495. "setenv bootargs root=/dev/nfs rw " \
  496. "nfsroot=$serverip:$rootpath " \
  497. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  498. "console=$consoledev,$baudrate $othbootargs;" \
  499. "tftp $loadaddr $bootfile;" \
  500. "tftp $fdtaddr $fdtfile;" \
  501. "bootm $loadaddr - $fdtaddr"
  502. #define CONFIG_RAMBOOTCOMMAND \
  503. "setenv bootargs root=/dev/ram rw " \
  504. "console=$consoledev,$baudrate $othbootargs;" \
  505. "tftp $ramdiskaddr $ramdiskfile;" \
  506. "tftp $loadaddr $bootfile;" \
  507. "tftp $fdtaddr $fdtfile;" \
  508. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  509. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  510. #include <asm/fsl_secure_boot.h>
  511. #endif /* __CONFIG_H */