T208xRDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T2080 RDB/PCIe board configuration file
  8. */
  9. #ifndef __T2080RDB_H
  10. #define __T2080RDB_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #define CONFIG_FSL_SATA_V2
  14. /* High Level Configuration Options */
  15. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  16. #define CONFIG_ENABLE_36BIT_PHYS
  17. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  18. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  19. #define CONFIG_ENV_OVERWRITE
  20. #ifdef CONFIG_RAMBOOT_PBL
  21. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  22. #define CONFIG_SPL_FLUSH_IMAGE
  23. #define CONFIG_SPL_PAD_TO 0x40000
  24. #define CONFIG_SPL_MAX_SIZE 0x28000
  25. #define RESET_VECTOR_OFFSET 0x27FFC
  26. #define BOOT_PAGE_OFFSET 0x27000
  27. #ifdef CONFIG_SPL_BUILD
  28. #define CONFIG_SPL_SKIP_RELOCATE
  29. #define CONFIG_SPL_COMMON_INIT_DDR
  30. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  31. #endif
  32. #ifdef CONFIG_MTD_RAW_NAND
  33. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  34. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  35. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  36. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  37. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  38. #endif
  39. #ifdef CONFIG_SPIFLASH
  40. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  41. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  42. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  43. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  44. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  45. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  46. #ifndef CONFIG_SPL_BUILD
  47. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48. #endif
  49. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  50. #endif
  51. #ifdef CONFIG_SDCARD
  52. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  53. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  54. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  55. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  56. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  57. #ifndef CONFIG_SPL_BUILD
  58. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  59. #endif
  60. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  61. #endif
  62. #endif /* CONFIG_RAMBOOT_PBL */
  63. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  64. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  65. /* Set 1M boot space */
  66. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  67. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  68. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  69. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  70. #endif
  71. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  72. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  73. #endif
  74. /*
  75. * These can be toggled for performance analysis, otherwise use default.
  76. */
  77. #define CONFIG_SYS_CACHE_STASHING
  78. #define CONFIG_BTB /* toggle branch predition */
  79. #define CONFIG_DDR_ECC
  80. #ifdef CONFIG_DDR_ECC
  81. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  82. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  83. #endif
  84. #if defined(CONFIG_SPIFLASH)
  85. #elif defined(CONFIG_SDCARD)
  86. #define CONFIG_SYS_MMC_ENV_DEV 0
  87. #endif
  88. #ifndef __ASSEMBLY__
  89. unsigned long get_board_sys_clk(void);
  90. unsigned long get_board_ddr_clk(void);
  91. #endif
  92. #define CONFIG_SYS_CLK_FREQ 66660000
  93. #define CONFIG_DDR_CLK_FREQ 133330000
  94. /*
  95. * Config the L3 Cache as L3 SRAM
  96. */
  97. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  98. #define CONFIG_SYS_L3_SIZE (512 << 10)
  99. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  100. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  101. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  102. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  103. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  104. #define CONFIG_SYS_DCSRBAR 0xf0000000
  105. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  106. /* EEPROM */
  107. #define CONFIG_ID_EEPROM
  108. #define CONFIG_SYS_I2C_EEPROM_NXID
  109. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  110. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  111. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  112. /*
  113. * DDR Setup
  114. */
  115. #define CONFIG_VERY_BIG_RAM
  116. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  117. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  118. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  119. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  120. #define CONFIG_DDR_SPD
  121. #define CONFIG_SYS_SPD_BUS_NUM 0
  122. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  123. #define SPD_EEPROM_ADDRESS1 0x51
  124. #define SPD_EEPROM_ADDRESS2 0x52
  125. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  126. #define CTRL_INTLV_PREFERED cacheline
  127. /*
  128. * IFC Definitions
  129. */
  130. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  131. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  132. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  133. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  134. CSPR_PORT_SIZE_16 | \
  135. CSPR_MSEL_NOR | \
  136. CSPR_V)
  137. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  138. /* NOR Flash Timing Params */
  139. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  140. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  141. FTIM0_NOR_TEADC(0x5) | \
  142. FTIM0_NOR_TEAHC(0x5))
  143. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  144. FTIM1_NOR_TRAD_NOR(0x1A) |\
  145. FTIM1_NOR_TSEQRAD_NOR(0x13))
  146. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  147. FTIM2_NOR_TCH(0x4) | \
  148. FTIM2_NOR_TWPH(0x0E) | \
  149. FTIM2_NOR_TWP(0x1c))
  150. #define CONFIG_SYS_NOR_FTIM3 0x0
  151. #define CONFIG_SYS_FLASH_QUIET_TEST
  152. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  153. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  154. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  155. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  156. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  157. #define CONFIG_SYS_FLASH_EMPTY_INFO
  158. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  159. /* CPLD on IFC */
  160. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  161. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  162. #define CONFIG_SYS_CSPR2_EXT (0xf)
  163. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  164. | CSPR_PORT_SIZE_8 \
  165. | CSPR_MSEL_GPCM \
  166. | CSPR_V)
  167. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  168. #define CONFIG_SYS_CSOR2 0x0
  169. /* CPLD Timing parameters for IFC CS2 */
  170. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  171. FTIM0_GPCM_TEADC(0x0e) | \
  172. FTIM0_GPCM_TEAHC(0x0e))
  173. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  174. FTIM1_GPCM_TRAD(0x1f))
  175. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  176. FTIM2_GPCM_TCH(0x8) | \
  177. FTIM2_GPCM_TWP(0x1f))
  178. #define CONFIG_SYS_CS2_FTIM3 0x0
  179. /* NAND Flash on IFC */
  180. #define CONFIG_NAND_FSL_IFC
  181. #define CONFIG_SYS_NAND_BASE 0xff800000
  182. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  183. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  184. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  185. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  186. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  187. | CSPR_V)
  188. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  189. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  190. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  191. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  192. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  193. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  194. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  195. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  196. #define CONFIG_SYS_NAND_ONFI_DETECTION
  197. /* ONFI NAND Flash mode0 Timing Params */
  198. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  199. FTIM0_NAND_TWP(0x18) | \
  200. FTIM0_NAND_TWCHT(0x07) | \
  201. FTIM0_NAND_TWH(0x0a))
  202. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  203. FTIM1_NAND_TWBE(0x39) | \
  204. FTIM1_NAND_TRR(0x0e) | \
  205. FTIM1_NAND_TRP(0x18))
  206. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  207. FTIM2_NAND_TREH(0x0a) | \
  208. FTIM2_NAND_TWHRE(0x1e))
  209. #define CONFIG_SYS_NAND_FTIM3 0x0
  210. #define CONFIG_SYS_NAND_DDR_LAW 11
  211. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  212. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  213. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  214. #if defined(CONFIG_MTD_RAW_NAND)
  215. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  216. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  217. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  218. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  219. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  220. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  221. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  222. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  223. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  224. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  225. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  226. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  227. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  228. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  229. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  230. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  231. #else
  232. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  233. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  234. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  235. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  236. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  237. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  238. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  239. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  240. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  241. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  242. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  243. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  244. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  245. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  246. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  247. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  248. #endif
  249. #if defined(CONFIG_RAMBOOT_PBL)
  250. #define CONFIG_SYS_RAMBOOT
  251. #endif
  252. #ifdef CONFIG_SPL_BUILD
  253. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  254. #else
  255. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  256. #endif
  257. #define CONFIG_HWCONFIG
  258. /* define to use L1 as initial stack */
  259. #define CONFIG_L1_INIT_RAM
  260. #define CONFIG_SYS_INIT_RAM_LOCK
  261. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  262. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  263. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  264. /* The assembler doesn't like typecast */
  265. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  266. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  267. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  268. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  269. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  270. GENERATED_GBL_DATA_SIZE)
  271. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  272. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  273. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  274. /*
  275. * Serial Port
  276. */
  277. #define CONFIG_SYS_NS16550_SERIAL
  278. #define CONFIG_SYS_NS16550_REG_SIZE 1
  279. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  280. #define CONFIG_SYS_BAUDRATE_TABLE \
  281. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  282. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  283. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  284. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  285. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  286. /*
  287. * I2C
  288. */
  289. #ifndef CONFIG_DM_I2C
  290. #define CONFIG_SYS_I2C
  291. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  292. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  293. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  294. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  295. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  296. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  297. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  298. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  299. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  300. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  301. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  302. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  303. #else
  304. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  305. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  306. #endif
  307. #define CONFIG_SYS_I2C_FSL
  308. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  309. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  310. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  311. #define I2C_MUX_CH_DEFAULT 0x8
  312. #define I2C_MUX_CH_VOL_MONITOR 0xa
  313. #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
  314. #ifndef CONFIG_SPL_BUILD
  315. #define CONFIG_VID
  316. #endif
  317. #define CONFIG_VOL_MONITOR_IR36021_SET
  318. #define CONFIG_VOL_MONITOR_IR36021_READ
  319. /* The lowest and highest voltage allowed for T208xRDB */
  320. #define VDD_MV_MIN 819
  321. #define VDD_MV_MAX 1212
  322. /*
  323. * RapidIO
  324. */
  325. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  326. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  327. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  328. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  329. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  330. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  331. /*
  332. * for slave u-boot IMAGE instored in master memory space,
  333. * PHYS must be aligned based on the SIZE
  334. */
  335. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  336. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  337. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  338. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  339. /*
  340. * for slave UCODE and ENV instored in master memory space,
  341. * PHYS must be aligned based on the SIZE
  342. */
  343. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  344. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  345. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  346. /* slave core release by master*/
  347. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  348. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  349. /*
  350. * SRIO_PCIE_BOOT - SLAVE
  351. */
  352. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  353. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  354. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  355. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  356. #endif
  357. /*
  358. * eSPI - Enhanced SPI
  359. */
  360. /*
  361. * General PCI
  362. * Memory space is mapped 1-1, but I/O space must start from 0.
  363. */
  364. #define CONFIG_PCIE1 /* PCIE controller 1 */
  365. #define CONFIG_PCIE2 /* PCIE controller 2 */
  366. #define CONFIG_PCIE3 /* PCIE controller 3 */
  367. #define CONFIG_PCIE4 /* PCIE controller 4 */
  368. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  369. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  370. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  371. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  372. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  373. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  374. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  375. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  376. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  377. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  378. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  379. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  380. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  381. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  382. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  383. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  384. /* controller 4, Base address 203000 */
  385. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  386. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  387. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  388. #ifdef CONFIG_PCI
  389. #if !defined(CONFIG_DM_PCI)
  390. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  391. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  392. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  393. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  394. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  395. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  396. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  397. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  398. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  399. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  400. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  401. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  402. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  403. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  404. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  405. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  406. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  407. #define CONFIG_PCI_INDIRECT_BRIDGE
  408. #endif
  409. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  410. #endif
  411. /* Qman/Bman */
  412. #ifndef CONFIG_NOBQFMAN
  413. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  414. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  415. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  416. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  417. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  418. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  419. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  420. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  421. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  422. CONFIG_SYS_BMAN_CENA_SIZE)
  423. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  424. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  425. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  426. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  427. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  428. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  429. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  430. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  431. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  432. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  433. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  434. CONFIG_SYS_QMAN_CENA_SIZE)
  435. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  436. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  437. #define CONFIG_SYS_DPAA_FMAN
  438. #define CONFIG_SYS_DPAA_PME
  439. #define CONFIG_SYS_PMAN
  440. #define CONFIG_SYS_DPAA_DCE
  441. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  442. #define CONFIG_SYS_INTERLAKEN
  443. /* Default address of microcode for the Linux Fman driver */
  444. #if defined(CONFIG_SPIFLASH)
  445. /*
  446. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  447. * env, so we got 0x110000.
  448. */
  449. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  450. #define CONFIG_CORTINA_FW_ADDR 0x120000
  451. #elif defined(CONFIG_SDCARD)
  452. /*
  453. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  454. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  455. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  456. */
  457. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  458. #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
  459. #elif defined(CONFIG_MTD_RAW_NAND)
  460. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  461. #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  462. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  463. /*
  464. * Slave has no ucode locally, it can fetch this from remote. When implementing
  465. * in two corenet boards, slave's ucode could be stored in master's memory
  466. * space, the address can be mapped from slave TLB->slave LAW->
  467. * slave SRIO or PCIE outbound window->master inbound window->
  468. * master LAW->the ucode address in master's memory space.
  469. */
  470. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  471. #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
  472. #else
  473. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  474. #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
  475. #endif
  476. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  477. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  478. #endif /* CONFIG_NOBQFMAN */
  479. #ifdef CONFIG_SYS_DPAA_FMAN
  480. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  481. #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  482. #define RGMII_PHY2_ADDR 0x02
  483. #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  484. #define CORTINA_PHY_ADDR2 0x0d
  485. #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
  486. #define FM1_10GEC4_PHY_ADDR 0x01
  487. #endif
  488. #ifdef CONFIG_FMAN_ENET
  489. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  490. #endif
  491. /*
  492. * SATA
  493. */
  494. #ifdef CONFIG_FSL_SATA_V2
  495. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  496. #define CONFIG_SATA1
  497. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  498. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  499. #define CONFIG_SATA2
  500. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  501. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  502. #define CONFIG_LBA48
  503. #endif
  504. /*
  505. * USB
  506. */
  507. #ifdef CONFIG_USB_EHCI_HCD
  508. #define CONFIG_USB_EHCI_FSL
  509. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  510. #define CONFIG_HAS_FSL_DR_USB
  511. #endif
  512. /*
  513. * SDHC
  514. */
  515. #ifdef CONFIG_MMC
  516. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  517. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  518. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  519. #endif
  520. /*
  521. * Dynamic MTD Partition support with mtdparts
  522. */
  523. /*
  524. * Environment
  525. */
  526. /*
  527. * Miscellaneous configurable options
  528. */
  529. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  530. /*
  531. * For booting Linux, the board info and command line data
  532. * have to be in the first 64 MB of memory, since this is
  533. * the maximum mapped by the Linux kernel during initialization.
  534. */
  535. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  536. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  537. #ifdef CONFIG_CMD_KGDB
  538. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  539. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  540. #endif
  541. /*
  542. * Environment Configuration
  543. */
  544. #define CONFIG_ROOTPATH "/opt/nfsroot"
  545. #define CONFIG_BOOTFILE "uImage"
  546. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  547. /* default location for tftp and bootm */
  548. #define CONFIG_LOADADDR 1000000
  549. #define __USB_PHY_TYPE utmi
  550. #define CONFIG_EXTRA_ENV_SETTINGS \
  551. "hwconfig=fsl_ddr:" \
  552. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  553. "bank_intlv=auto;" \
  554. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  555. "netdev=eth0\0" \
  556. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  557. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  558. "tftpflash=tftpboot $loadaddr $uboot && " \
  559. "protect off $ubootaddr +$filesize && " \
  560. "erase $ubootaddr +$filesize && " \
  561. "cp.b $loadaddr $ubootaddr $filesize && " \
  562. "protect on $ubootaddr +$filesize && " \
  563. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  564. "consoledev=ttyS0\0" \
  565. "ramdiskaddr=2000000\0" \
  566. "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  567. "fdtaddr=1e00000\0" \
  568. "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  569. "bdev=sda3\0"
  570. /*
  571. * For emulation this causes u-boot to jump to the start of the
  572. * proof point app code automatically
  573. */
  574. #define CONFIG_PROOF_POINTS \
  575. "setenv bootargs root=/dev/$bdev rw " \
  576. "console=$consoledev,$baudrate $othbootargs;" \
  577. "cpu 1 release 0x29000000 - - -;" \
  578. "cpu 2 release 0x29000000 - - -;" \
  579. "cpu 3 release 0x29000000 - - -;" \
  580. "cpu 4 release 0x29000000 - - -;" \
  581. "cpu 5 release 0x29000000 - - -;" \
  582. "cpu 6 release 0x29000000 - - -;" \
  583. "cpu 7 release 0x29000000 - - -;" \
  584. "go 0x29000000"
  585. #define CONFIG_HVBOOT \
  586. "setenv bootargs config-addr=0x60000000; " \
  587. "bootm 0x01000000 - 0x00f00000"
  588. #define CONFIG_ALU \
  589. "setenv bootargs root=/dev/$bdev rw " \
  590. "console=$consoledev,$baudrate $othbootargs;" \
  591. "cpu 1 release 0x01000000 - - -;" \
  592. "cpu 2 release 0x01000000 - - -;" \
  593. "cpu 3 release 0x01000000 - - -;" \
  594. "cpu 4 release 0x01000000 - - -;" \
  595. "cpu 5 release 0x01000000 - - -;" \
  596. "cpu 6 release 0x01000000 - - -;" \
  597. "cpu 7 release 0x01000000 - - -;" \
  598. "go 0x01000000"
  599. #define CONFIG_LINUX \
  600. "setenv bootargs root=/dev/ram rw " \
  601. "console=$consoledev,$baudrate $othbootargs;" \
  602. "setenv ramdiskaddr 0x02000000;" \
  603. "setenv fdtaddr 0x00c00000;" \
  604. "setenv loadaddr 0x1000000;" \
  605. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  606. #define CONFIG_HDBOOT \
  607. "setenv bootargs root=/dev/$bdev rw " \
  608. "console=$consoledev,$baudrate $othbootargs;" \
  609. "tftp $loadaddr $bootfile;" \
  610. "tftp $fdtaddr $fdtfile;" \
  611. "bootm $loadaddr - $fdtaddr"
  612. #define CONFIG_NFSBOOTCOMMAND \
  613. "setenv bootargs root=/dev/nfs rw " \
  614. "nfsroot=$serverip:$rootpath " \
  615. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  616. "console=$consoledev,$baudrate $othbootargs;" \
  617. "tftp $loadaddr $bootfile;" \
  618. "tftp $fdtaddr $fdtfile;" \
  619. "bootm $loadaddr - $fdtaddr"
  620. #define CONFIG_RAMBOOTCOMMAND \
  621. "setenv bootargs root=/dev/ram rw " \
  622. "console=$consoledev,$baudrate $othbootargs;" \
  623. "tftp $ramdiskaddr $ramdiskfile;" \
  624. "tftp $loadaddr $bootfile;" \
  625. "tftp $fdtaddr $fdtfile;" \
  626. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  627. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  628. #include <asm/fsl_secure_boot.h>
  629. #endif /* __T2080RDB_H */