T102xRDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * T1024/T1023 RDB board configuration file
  8. */
  9. #ifndef __T1024RDB_H
  10. #define __T1024RDB_H
  11. #include <linux/stringify.h>
  12. /* High Level Configuration Options */
  13. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  14. #define CONFIG_ENABLE_36BIT_PHYS
  15. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  16. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  17. #define CONFIG_ENV_OVERWRITE
  18. /* support deep sleep */
  19. #ifdef CONFIG_ARCH_T1024
  20. #define CONFIG_DEEP_SLEEP
  21. #endif
  22. #ifdef CONFIG_RAMBOOT_PBL
  23. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  24. #define CONFIG_SPL_FLUSH_IMAGE
  25. #define CONFIG_SPL_PAD_TO 0x40000
  26. #define CONFIG_SPL_MAX_SIZE 0x28000
  27. #define RESET_VECTOR_OFFSET 0x27FFC
  28. #define BOOT_PAGE_OFFSET 0x27000
  29. #ifdef CONFIG_SPL_BUILD
  30. #define CONFIG_SPL_SKIP_RELOCATE
  31. #define CONFIG_SPL_COMMON_INIT_DDR
  32. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  33. #endif
  34. #ifdef CONFIG_MTD_RAW_NAND
  35. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  36. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  37. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  38. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  39. #if defined(CONFIG_TARGET_T1024RDB)
  40. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  41. #elif defined(CONFIG_TARGET_T1023RDB)
  42. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  43. #endif
  44. #endif
  45. #ifdef CONFIG_SPIFLASH
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  47. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  48. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  49. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  51. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  52. #ifndef CONFIG_SPL_BUILD
  53. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54. #endif
  55. #if defined(CONFIG_TARGET_T1024RDB)
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  57. #elif defined(CONFIG_TARGET_T1023RDB)
  58. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  59. #endif
  60. #endif
  61. #ifdef CONFIG_SDCARD
  62. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  63. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  64. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  65. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  66. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  67. #ifndef CONFIG_SPL_BUILD
  68. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  69. #endif
  70. #if defined(CONFIG_TARGET_T1024RDB)
  71. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  72. #elif defined(CONFIG_TARGET_T1023RDB)
  73. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  74. #endif
  75. #endif
  76. #endif /* CONFIG_RAMBOOT_PBL */
  77. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  78. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  79. #endif
  80. /* PCIe Boot - Master */
  81. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  82. /*
  83. * for slave u-boot IMAGE instored in master memory space,
  84. * PHYS must be aligned based on the SIZE
  85. */
  86. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  87. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  88. #ifdef CONFIG_PHYS_64BIT
  89. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  90. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  91. #else
  92. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  93. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  94. #endif
  95. /*
  96. * for slave UCODE and ENV instored in master memory space,
  97. * PHYS must be aligned based on the SIZE
  98. */
  99. #ifdef CONFIG_PHYS_64BIT
  100. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  101. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  102. #else
  103. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  104. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
  105. #endif
  106. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  107. /* slave core release by master*/
  108. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  109. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  110. /* PCIe Boot - Slave */
  111. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  112. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  113. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  114. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  115. /* Set 1M boot space for PCIe boot */
  116. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  117. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  118. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  119. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  120. #endif
  121. #if defined(CONFIG_SPIFLASH)
  122. #elif defined(CONFIG_SDCARD)
  123. #define CONFIG_SYS_MMC_ENV_DEV 0
  124. #endif
  125. #ifndef __ASSEMBLY__
  126. unsigned long get_board_sys_clk(void);
  127. unsigned long get_board_ddr_clk(void);
  128. #endif
  129. #define CONFIG_SYS_CLK_FREQ 100000000
  130. #define CONFIG_DDR_CLK_FREQ 100000000
  131. /*
  132. * These can be toggled for performance analysis, otherwise use default.
  133. */
  134. #define CONFIG_SYS_CACHE_STASHING
  135. #define CONFIG_BACKSIDE_L2_CACHE
  136. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  137. #define CONFIG_BTB /* toggle branch predition */
  138. #define CONFIG_DDR_ECC
  139. #ifdef CONFIG_DDR_ECC
  140. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  141. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  142. #endif
  143. /*
  144. * Config the L3 Cache as L3 SRAM
  145. */
  146. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  147. #define CONFIG_SYS_L3_SIZE (256 << 10)
  148. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  149. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  150. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  151. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  152. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  153. #ifdef CONFIG_PHYS_64BIT
  154. #define CONFIG_SYS_DCSRBAR 0xf0000000
  155. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  156. #endif
  157. /* EEPROM */
  158. #define CONFIG_ID_EEPROM
  159. #define CONFIG_SYS_I2C_EEPROM_NXID
  160. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  161. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  162. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  163. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  164. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  165. /*
  166. * DDR Setup
  167. */
  168. #define CONFIG_VERY_BIG_RAM
  169. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  170. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  171. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  172. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  173. #if defined(CONFIG_TARGET_T1024RDB)
  174. #define CONFIG_DDR_SPD
  175. #define CONFIG_SYS_SPD_BUS_NUM 0
  176. #define SPD_EEPROM_ADDRESS 0x51
  177. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  178. #elif defined(CONFIG_TARGET_T1023RDB)
  179. #define CONFIG_SYS_DDR_RAW_TIMING
  180. #define CONFIG_SYS_SDRAM_SIZE 2048
  181. #endif
  182. /*
  183. * IFC Definitions
  184. */
  185. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  186. #ifdef CONFIG_PHYS_64BIT
  187. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  188. #else
  189. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  190. #endif
  191. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  192. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  193. CSPR_PORT_SIZE_16 | \
  194. CSPR_MSEL_NOR | \
  195. CSPR_V)
  196. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  197. /* NOR Flash Timing Params */
  198. #if defined(CONFIG_TARGET_T1024RDB)
  199. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  200. #elif defined(CONFIG_TARGET_T1023RDB)
  201. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
  202. CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
  203. #endif
  204. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  205. FTIM0_NOR_TEADC(0x5) | \
  206. FTIM0_NOR_TEAHC(0x5))
  207. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  208. FTIM1_NOR_TRAD_NOR(0x1A) |\
  209. FTIM1_NOR_TSEQRAD_NOR(0x13))
  210. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  211. FTIM2_NOR_TCH(0x4) | \
  212. FTIM2_NOR_TWPH(0x0E) | \
  213. FTIM2_NOR_TWP(0x1c))
  214. #define CONFIG_SYS_NOR_FTIM3 0x0
  215. #define CONFIG_SYS_FLASH_QUIET_TEST
  216. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  217. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  218. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  219. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  220. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  221. #define CONFIG_SYS_FLASH_EMPTY_INFO
  222. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  223. #ifdef CONFIG_TARGET_T1024RDB
  224. /* CPLD on IFC */
  225. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  226. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  227. #define CONFIG_SYS_CSPR2_EXT (0xf)
  228. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  229. | CSPR_PORT_SIZE_8 \
  230. | CSPR_MSEL_GPCM \
  231. | CSPR_V)
  232. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  233. #define CONFIG_SYS_CSOR2 0x0
  234. /* CPLD Timing parameters for IFC CS2 */
  235. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  236. FTIM0_GPCM_TEADC(0x0e) | \
  237. FTIM0_GPCM_TEAHC(0x0e))
  238. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  239. FTIM1_GPCM_TRAD(0x1f))
  240. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  241. FTIM2_GPCM_TCH(0x8) | \
  242. FTIM2_GPCM_TWP(0x1f))
  243. #define CONFIG_SYS_CS2_FTIM3 0x0
  244. #endif
  245. /* NAND Flash on IFC */
  246. #define CONFIG_NAND_FSL_IFC
  247. #define CONFIG_SYS_NAND_BASE 0xff800000
  248. #ifdef CONFIG_PHYS_64BIT
  249. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  250. #else
  251. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  252. #endif
  253. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  254. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  255. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  256. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  257. | CSPR_V)
  258. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  259. #if defined(CONFIG_TARGET_T1024RDB)
  260. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  261. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  262. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  263. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  264. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  265. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  266. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  267. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  268. #elif defined(CONFIG_TARGET_T1023RDB)
  269. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  270. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  271. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  272. | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
  273. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  274. | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
  275. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  276. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  277. #endif
  278. #define CONFIG_SYS_NAND_ONFI_DETECTION
  279. /* ONFI NAND Flash mode0 Timing Params */
  280. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  281. FTIM0_NAND_TWP(0x18) | \
  282. FTIM0_NAND_TWCHT(0x07) | \
  283. FTIM0_NAND_TWH(0x0a))
  284. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  285. FTIM1_NAND_TWBE(0x39) | \
  286. FTIM1_NAND_TRR(0x0e) | \
  287. FTIM1_NAND_TRP(0x18))
  288. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  289. FTIM2_NAND_TREH(0x0a) | \
  290. FTIM2_NAND_TWHRE(0x1e))
  291. #define CONFIG_SYS_NAND_FTIM3 0x0
  292. #define CONFIG_SYS_NAND_DDR_LAW 11
  293. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  294. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  295. #if defined(CONFIG_MTD_RAW_NAND)
  296. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  297. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  298. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  299. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  300. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  301. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  302. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  303. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  304. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  305. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  306. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  307. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  308. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  309. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  310. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  311. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  312. #else
  313. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  314. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  315. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  316. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  317. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  318. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  319. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  320. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  321. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  322. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  323. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  324. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  325. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  326. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  327. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  328. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  329. #endif
  330. #ifdef CONFIG_SPL_BUILD
  331. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  332. #else
  333. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  334. #endif
  335. #if defined(CONFIG_RAMBOOT_PBL)
  336. #define CONFIG_SYS_RAMBOOT
  337. #endif
  338. #define CONFIG_HWCONFIG
  339. /* define to use L1 as initial stack */
  340. #define CONFIG_L1_INIT_RAM
  341. #define CONFIG_SYS_INIT_RAM_LOCK
  342. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  343. #ifdef CONFIG_PHYS_64BIT
  344. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  345. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  346. /* The assembler doesn't like typecast */
  347. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  348. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  349. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  350. #else
  351. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  352. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  353. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  354. #endif
  355. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  356. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  357. GENERATED_GBL_DATA_SIZE)
  358. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  359. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  360. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  361. /* Serial Port */
  362. #define CONFIG_SYS_NS16550_SERIAL
  363. #define CONFIG_SYS_NS16550_REG_SIZE 1
  364. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  365. #define CONFIG_SYS_BAUDRATE_TABLE \
  366. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  367. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  368. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  369. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  370. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  371. /* Video */
  372. #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
  373. #ifdef CONFIG_FSL_DIU_FB
  374. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  375. #define CONFIG_VIDEO_LOGO
  376. #define CONFIG_VIDEO_BMP_LOGO
  377. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  378. /*
  379. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  380. * disable empty flash sector detection, which is I/O-intensive.
  381. */
  382. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  383. #endif
  384. /* I2C */
  385. #ifndef CONFIG_DM_I2C
  386. #define CONFIG_SYS_I2C
  387. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  388. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  389. #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
  390. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  391. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  392. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  393. #else
  394. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  395. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  396. #endif
  397. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  398. #define I2C_PCA6408_BUS_NUM 1
  399. #define I2C_PCA6408_ADDR 0x20
  400. /* I2C bus multiplexer */
  401. #define I2C_MUX_CH_DEFAULT 0x8
  402. /*
  403. * RTC configuration
  404. */
  405. #define RTC
  406. #define CONFIG_RTC_DS1337 1
  407. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  408. /*
  409. * eSPI - Enhanced SPI
  410. */
  411. /*
  412. * General PCIe
  413. * Memory space is mapped 1-1, but I/O space must start from 0.
  414. */
  415. #define CONFIG_PCIE1 /* PCIE controller 1 */
  416. #define CONFIG_PCIE2 /* PCIE controller 2 */
  417. #define CONFIG_PCIE3 /* PCIE controller 3 */
  418. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  419. #ifdef CONFIG_PCI
  420. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  421. #ifdef CONFIG_PCIE1
  422. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  423. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  424. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  425. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  426. #endif
  427. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  428. #ifdef CONFIG_PCIE2
  429. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  430. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  431. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  432. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  433. #endif
  434. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  435. #ifdef CONFIG_PCIE3
  436. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  437. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  438. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  439. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  440. #endif
  441. #if !defined(CONFIG_DM_PCI)
  442. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  443. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  444. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  445. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  446. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  447. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  448. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  449. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  450. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  451. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  452. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  453. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  454. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  455. #define CONFIG_PCI_INDIRECT_BRIDGE
  456. #endif
  457. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  458. #endif /* CONFIG_PCI */
  459. /*
  460. * USB
  461. */
  462. #define CONFIG_HAS_FSL_DR_USB
  463. #ifdef CONFIG_HAS_FSL_DR_USB
  464. #define CONFIG_USB_EHCI_FSL
  465. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  466. #endif
  467. /*
  468. * SDHC
  469. */
  470. #ifdef CONFIG_MMC
  471. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  472. #endif
  473. /* Qman/Bman */
  474. #ifndef CONFIG_NOBQFMAN
  475. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  476. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  477. #ifdef CONFIG_PHYS_64BIT
  478. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  479. #else
  480. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  481. #endif
  482. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  483. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  484. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  485. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  486. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  487. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  488. CONFIG_SYS_BMAN_CENA_SIZE)
  489. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  490. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  491. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  492. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  493. #ifdef CONFIG_PHYS_64BIT
  494. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  495. #else
  496. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  497. #endif
  498. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  499. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  500. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  501. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  502. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  503. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  504. CONFIG_SYS_QMAN_CENA_SIZE)
  505. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  506. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  507. #define CONFIG_SYS_DPAA_FMAN
  508. /* Default address of microcode for the Linux FMan driver */
  509. #if defined(CONFIG_SPIFLASH)
  510. /*
  511. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  512. * env, so we got 0x110000.
  513. */
  514. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  515. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  516. #elif defined(CONFIG_SDCARD)
  517. /*
  518. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  519. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  520. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  521. */
  522. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  523. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  524. #elif defined(CONFIG_MTD_RAW_NAND)
  525. #if defined(CONFIG_TARGET_T1024RDB)
  526. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  527. #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  528. #elif defined(CONFIG_TARGET_T1023RDB)
  529. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  530. #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  531. #endif
  532. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  533. /*
  534. * Slave has no ucode locally, it can fetch this from remote. When implementing
  535. * in two corenet boards, slave's ucode could be stored in master's memory
  536. * space, the address can be mapped from slave TLB->slave LAW->
  537. * slave SRIO or PCIE outbound window->master inbound window->
  538. * master LAW->the ucode address in master's memory space.
  539. */
  540. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  541. #else
  542. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  543. #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
  544. #endif
  545. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  546. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  547. #endif /* CONFIG_NOBQFMAN */
  548. #ifdef CONFIG_SYS_DPAA_FMAN
  549. #if defined(CONFIG_TARGET_T1024RDB)
  550. #define RGMII_PHY1_ADDR 0x2
  551. #define RGMII_PHY2_ADDR 0x6
  552. #define SGMII_AQR_PHY_ADDR 0x2
  553. #define FM1_10GEC1_PHY_ADDR 0x1
  554. #elif defined(CONFIG_TARGET_T1023RDB)
  555. #define RGMII_PHY1_ADDR 0x1
  556. #define SGMII_RTK_PHY_ADDR 0x3
  557. #define SGMII_AQR_PHY_ADDR 0x2
  558. #endif
  559. #endif
  560. #ifdef CONFIG_FMAN_ENET
  561. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  562. #endif
  563. /*
  564. * Dynamic MTD Partition support with mtdparts
  565. */
  566. /*
  567. * Environment
  568. */
  569. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  570. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  571. /*
  572. * Miscellaneous configurable options
  573. */
  574. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  575. /*
  576. * For booting Linux, the board info and command line data
  577. * have to be in the first 64 MB of memory, since this is
  578. * the maximum mapped by the Linux kernel during initialization.
  579. */
  580. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  581. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  582. #ifdef CONFIG_CMD_KGDB
  583. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  584. #endif
  585. /*
  586. * Environment Configuration
  587. */
  588. #define CONFIG_ROOTPATH "/opt/nfsroot"
  589. #define CONFIG_BOOTFILE "uImage"
  590. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  591. #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
  592. #define __USB_PHY_TYPE utmi
  593. #ifdef CONFIG_ARCH_T1024
  594. #define CONFIG_BOARDNAME t1024rdb
  595. #define BANK_INTLV cs0_cs1
  596. #else
  597. #define CONFIG_BOARDNAME t1023rdb
  598. #define BANK_INTLV null
  599. #endif
  600. #define CONFIG_EXTRA_ENV_SETTINGS \
  601. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  602. "bank_intlv=" __stringify(BANK_INTLV) "\0" \
  603. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  604. "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
  605. "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
  606. __stringify(CONFIG_BOARDNAME) ".dtb\0" \
  607. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  608. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  609. "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
  610. "netdev=eth0\0" \
  611. "tftpflash=tftpboot $loadaddr $uboot && " \
  612. "protect off $ubootaddr +$filesize && " \
  613. "erase $ubootaddr +$filesize && " \
  614. "cp.b $loadaddr $ubootaddr $filesize && " \
  615. "protect on $ubootaddr +$filesize && " \
  616. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  617. "consoledev=ttyS0\0" \
  618. "ramdiskaddr=2000000\0" \
  619. "fdtaddr=1e00000\0" \
  620. "bdev=sda3\0"
  621. #define CONFIG_LINUX \
  622. "setenv bootargs root=/dev/ram rw " \
  623. "console=$consoledev,$baudrate $othbootargs;" \
  624. "setenv ramdiskaddr 0x02000000;" \
  625. "setenv fdtaddr 0x00c00000;" \
  626. "setenv loadaddr 0x1000000;" \
  627. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  628. #define CONFIG_NFSBOOTCOMMAND \
  629. "setenv bootargs root=/dev/nfs rw " \
  630. "nfsroot=$serverip:$rootpath " \
  631. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  632. "console=$consoledev,$baudrate $othbootargs;" \
  633. "tftp $loadaddr $bootfile;" \
  634. "tftp $fdtaddr $fdtfile;" \
  635. "bootm $loadaddr - $fdtaddr"
  636. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  637. #include <asm/fsl_secure_boot.h>
  638. #endif /* __T1024RDB_H */