P1023RDB.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Authors: Roy Zang <tie-fei.zang@freescale.com>
  6. * Chunhe Lan <Chunhe.Lan@freescale.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <linux/stringify.h>
  11. #ifndef CONFIG_SYS_MONITOR_BASE
  12. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  13. #endif
  14. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  15. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  16. #endif
  17. /* High Level Configuration Options */
  18. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  19. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  20. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  21. #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
  22. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  23. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  24. #ifndef __ASSEMBLY__
  25. extern unsigned long get_clock_freq(void);
  26. #endif
  27. #define CONFIG_SYS_CLK_FREQ 66666666
  28. #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
  29. /*
  30. * These can be toggled for performance analysis, otherwise use default.
  31. */
  32. #define CONFIG_L2_CACHE /* toggle L2 cache */
  33. #define CONFIG_BTB /* toggle branch predition */
  34. #define CONFIG_HWCONFIG
  35. #define CONFIG_ENABLE_36BIT_PHYS
  36. /* Implement conversion of addresses in the LBC */
  37. #define CONFIG_SYS_LBC_LBCR 0x00000000
  38. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  39. /* DDR Setup */
  40. #define CONFIG_VERY_BIG_RAM
  41. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  42. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  43. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  44. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  45. #define CONFIG_DDR_SPD
  46. #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
  47. #define CONFIG_SYS_SPD_BUS_NUM 0
  48. #define SPD_EEPROM_ADDRESS 0x50
  49. #define CONFIG_SYS_DDR_RAW_TIMING
  50. /*
  51. * Memory map
  52. *
  53. * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
  54. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  55. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  56. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  57. * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
  58. * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
  59. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
  60. *
  61. * Localbus non-cacheable
  62. *
  63. * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
  64. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  65. */
  66. /*
  67. * Local Bus Definitions
  68. */
  69. #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
  70. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  71. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  72. | BR_PS_16 | BR_V)
  73. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  74. #define CONFIG_SYS_FLASH_EMPTY_INFO
  75. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  76. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  77. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  78. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  79. #define CONFIG_SYS_INIT_RAM_LOCK
  80. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  81. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
  82. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  83. GENERATED_GBL_DATA_SIZE)
  84. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  85. #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
  86. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
  87. #define CONFIG_SYS_NAND_BASE 0xffa00000
  88. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  89. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  90. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  91. #define CONFIG_NAND_FSL_ELBC
  92. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  93. /* NAND flash config */
  94. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  95. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  96. | BR_PS_8 /* Port Size = 8bit */ \
  97. | BR_MS_FCM /* MSEL = FCM */ \
  98. | BR_V) /* valid */
  99. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
  100. | OR_FCM_PGS \
  101. | OR_FCM_CSCT \
  102. | OR_FCM_CST \
  103. | OR_FCM_CHT \
  104. | OR_FCM_SCY_1 \
  105. | OR_FCM_TRLX \
  106. | OR_FCM_EHTR)
  107. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  108. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  109. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  110. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  111. /* Serial Port */
  112. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  113. #define CONFIG_SYS_NS16550_SERIAL
  114. #define CONFIG_SYS_NS16550_REG_SIZE 1
  115. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  116. #define CONFIG_SYS_BAUDRATE_TABLE \
  117. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  118. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  119. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  120. /* I2C */
  121. #define CONFIG_SYS_I2C
  122. #define CONFIG_SYS_I2C_FSL
  123. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  124. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  125. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  126. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  127. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  128. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  129. /*
  130. * I2C2 EEPROM
  131. */
  132. #define CONFIG_ID_EEPROM
  133. #ifdef CONFIG_ID_EEPROM
  134. #define CONFIG_SYS_I2C_EEPROM_NXID
  135. #endif
  136. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  137. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  138. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  139. /*
  140. * General PCI
  141. * Memory space is mapped 1-1, but I/O space must start from 0.
  142. */
  143. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  144. #define CONFIG_SYS_PCIE3_NAME "Slot 3"
  145. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  146. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  147. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  148. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  149. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  150. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  151. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  152. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  153. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  154. #define CONFIG_SYS_PCIE2_NAME "Slot 2"
  155. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  156. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  157. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  158. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  159. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  160. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  161. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  162. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  163. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  164. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  165. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  166. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  167. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  168. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  169. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  170. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  171. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  172. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  173. #if defined(CONFIG_PCI)
  174. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  175. #endif /* CONFIG_PCI */
  176. /*
  177. * Environment
  178. */
  179. #define CONFIG_ENV_OVERWRITE
  180. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  181. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  182. /*
  183. * USB
  184. */
  185. #define CONFIG_HAS_FSL_DR_USB
  186. #ifdef CONFIG_HAS_FSL_DR_USB
  187. #ifdef CONFIG_USB_EHCI_HCD
  188. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  189. #define CONFIG_USB_EHCI_FSL
  190. #endif
  191. #endif
  192. /*
  193. * Miscellaneous configurable options
  194. */
  195. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  196. /*
  197. * For booting Linux, the board info and command line data
  198. * have to be in the first 64 MB of memory, since this is
  199. * the maximum mapped by the Linux kernel during initialization.
  200. */
  201. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  202. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  203. /*
  204. * Environment Configuration
  205. */
  206. #define CONFIG_BOOTFILE "uImage"
  207. #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
  208. /* default location for tftp and bootm */
  209. #define CONFIG_LOADADDR 1000000
  210. /* Qman/Bman */
  211. #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
  212. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  213. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  214. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  215. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  216. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  217. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  218. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  219. CONFIG_SYS_QMAN_CENA_SIZE)
  220. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  221. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  222. #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
  223. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  224. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  225. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  226. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  227. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  228. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  229. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  230. CONFIG_SYS_BMAN_CENA_SIZE)
  231. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  232. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  233. /* For FM */
  234. #define CONFIG_SYS_DPAA_FMAN
  235. /* Default address of microcode for the Linux Fman driver */
  236. /* QE microcode/firmware address */
  237. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  238. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  239. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  240. #ifdef CONFIG_FMAN_ENET
  241. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
  242. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
  243. #define CONFIG_SYS_TBIPA_VALUE 8
  244. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  245. #endif
  246. #define CONFIG_EXTRA_ENV_SETTINGS \
  247. "netdev=eth0\0" \
  248. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  249. "loadaddr=1000000\0" \
  250. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  251. "tftpflash=tftpboot $loadaddr $uboot; " \
  252. "protect off $ubootaddr +$filesize; " \
  253. "erase $ubootaddr +$filesize; " \
  254. "cp.b $loadaddr $ubootaddr $filesize; " \
  255. "protect on $ubootaddr +$filesize; " \
  256. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  257. "consoledev=ttyS0\0" \
  258. "ramdiskaddr=2000000\0" \
  259. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  260. "fdtaddr=1e00000\0" \
  261. "fdtfile=p1023rdb.dtb\0" \
  262. "othbootargs=ramdisk_size=600000\0" \
  263. "bdev=sda1\0" \
  264. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  265. #define CONFIG_HDBOOT \
  266. "setenv bootargs root=/dev/$bdev rw " \
  267. "console=$consoledev,$baudrate $othbootargs;" \
  268. "tftp $loadaddr $bootfile;" \
  269. "tftp $fdtaddr $fdtfile;" \
  270. "bootm $loadaddr - $fdtaddr"
  271. #define CONFIG_NFSBOOTCOMMAND \
  272. "setenv bootargs root=/dev/nfs rw " \
  273. "nfsroot=$serverip:$rootpath " \
  274. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  275. "console=$consoledev,$baudrate $othbootargs;" \
  276. "tftp $loadaddr $bootfile;" \
  277. "tftp $fdtaddr $fdtfile;" \
  278. "bootm $loadaddr - $fdtaddr"
  279. #define CONFIG_RAMBOOTCOMMAND \
  280. "setenv bootargs root=/dev/ram rw " \
  281. "console=$consoledev,$baudrate $othbootargs;" \
  282. "tftp $ramdiskaddr $ramdiskfile;" \
  283. "tftp $loadaddr $bootfile;" \
  284. "tftp $fdtaddr $fdtfile;" \
  285. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  286. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  287. #endif /* __CONFIG_H */