MPC8548CDS.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * mpc8548cds board configuration file
  8. *
  9. * Please refer to doc/README.mpc85xxcds for more info.
  10. *
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #define CONFIG_SYS_SRIO
  15. #define CONFIG_SRIO1 /* SRIO port 1 */
  16. #define CONFIG_PCI1 /* PCI controller 1 */
  17. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  18. #undef CONFIG_PCI2
  19. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  20. #define CONFIG_ENV_OVERWRITE
  21. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  22. #define CONFIG_FSL_VIA
  23. #ifndef __ASSEMBLY__
  24. #include <linux/stringify.h>
  25. extern unsigned long get_clock_freq(void);
  26. #endif
  27. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  28. /*
  29. * These can be toggled for performance analysis, otherwise use default.
  30. */
  31. #define CONFIG_L2_CACHE /* toggle L2 cache */
  32. #define CONFIG_BTB /* toggle branch predition */
  33. /*
  34. * Only possible on E500 Version 2 or newer cores.
  35. */
  36. #define CONFIG_ENABLE_36BIT_PHYS 1
  37. #define CONFIG_SYS_CCSRBAR 0xe0000000
  38. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  39. /* DDR Setup */
  40. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  41. #define CONFIG_DDR_SPD
  42. #define CONFIG_DDR_ECC
  43. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  44. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  45. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  46. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  47. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  48. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  49. /* I2C addresses of SPD EEPROMs */
  50. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  51. /* Make sure required options are set */
  52. #ifndef CONFIG_SPD_EEPROM
  53. #error ("CONFIG_SPD_EEPROM is required")
  54. #endif
  55. /*
  56. * Physical Address Map
  57. *
  58. * 32bit:
  59. * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
  60. * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
  61. * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
  62. * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
  63. * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
  64. * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
  65. * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
  66. * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
  67. * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
  68. * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
  69. * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
  70. *
  71. * 36bit:
  72. * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
  73. * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
  74. * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
  75. * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
  76. * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
  77. * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
  78. * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
  79. * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
  80. * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
  81. * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
  82. * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
  83. *
  84. */
  85. /*
  86. * Local Bus Definitions
  87. */
  88. /*
  89. * FLASH on the Local Bus
  90. * Two banks, 8M each, using the CFI driver.
  91. * Boot from BR0/OR0 bank at 0xff00_0000
  92. * Alternate BR1/OR1 bank at 0xff80_0000
  93. *
  94. * BR0, BR1:
  95. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  96. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  97. * Port Size = 16 bits = BRx[19:20] = 10
  98. * Use GPCM = BRx[24:26] = 000
  99. * Valid = BRx[31] = 1
  100. *
  101. * 0 4 8 12 16 20 24 28
  102. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  103. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  104. *
  105. * OR0, OR1:
  106. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  107. * Reserved ORx[17:18] = 11, confusion here?
  108. * CSNT = ORx[20] = 1
  109. * ACS = half cycle delay = ORx[21:22] = 11
  110. * SCY = 6 = ORx[24:27] = 0110
  111. * TRLX = use relaxed timing = ORx[29] = 1
  112. * EAD = use external address latch delay = OR[31] = 1
  113. *
  114. * 0 4 8 12 16 20 24 28
  115. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  116. */
  117. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  118. #ifdef CONFIG_PHYS_64BIT
  119. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
  120. #else
  121. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  122. #endif
  123. #define CONFIG_SYS_BR0_PRELIM \
  124. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
  125. #define CONFIG_SYS_BR1_PRELIM \
  126. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  127. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  128. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  129. #define CONFIG_SYS_FLASH_BANKS_LIST \
  130. {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
  131. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  132. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  133. #undef CONFIG_SYS_FLASH_CHECKSUM
  134. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  135. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  136. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  137. #define CONFIG_SYS_FLASH_EMPTY_INFO
  138. #define CONFIG_HWCONFIG /* enable hwconfig */
  139. /*
  140. * SDRAM on the Local Bus
  141. */
  142. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  143. #ifdef CONFIG_PHYS_64BIT
  144. #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
  145. #else
  146. #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
  147. #endif
  148. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  149. /*
  150. * Base Register 2 and Option Register 2 configure SDRAM.
  151. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  152. *
  153. * For BR2, need:
  154. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  155. * port-size = 32-bits = BR2[19:20] = 11
  156. * no parity checking = BR2[21:22] = 00
  157. * SDRAM for MSEL = BR2[24:26] = 011
  158. * Valid = BR[31] = 1
  159. *
  160. * 0 4 8 12 16 20 24 28
  161. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  162. *
  163. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  164. * FIXME: the top 17 bits of BR2.
  165. */
  166. #define CONFIG_SYS_BR2_PRELIM \
  167. (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
  168. | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
  169. /*
  170. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  171. *
  172. * For OR2, need:
  173. * 64MB mask for AM, OR2[0:7] = 1111 1100
  174. * XAM, OR2[17:18] = 11
  175. * 9 columns OR2[19-21] = 010
  176. * 13 rows OR2[23-25] = 100
  177. * EAD set for extra time OR[31] = 1
  178. *
  179. * 0 4 8 12 16 20 24 28
  180. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  181. */
  182. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  183. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  184. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  185. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  186. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  187. /*
  188. * Common settings for all Local Bus SDRAM commands.
  189. * At run time, either BSMA1516 (for CPU 1.1)
  190. * or BSMA1617 (for CPU 1.0) (old)
  191. * is OR'ed in too.
  192. */
  193. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  194. | LSDMR_PRETOACT7 \
  195. | LSDMR_ACTTORW7 \
  196. | LSDMR_BL8 \
  197. | LSDMR_WRC4 \
  198. | LSDMR_CL3 \
  199. | LSDMR_RFEN \
  200. )
  201. /*
  202. * The CADMUS registers are connected to CS3 on CDS.
  203. * The new memory map places CADMUS at 0xf8000000.
  204. *
  205. * For BR3, need:
  206. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  207. * port-size = 8-bits = BR[19:20] = 01
  208. * no parity checking = BR[21:22] = 00
  209. * GPMC for MSEL = BR[24:26] = 000
  210. * Valid = BR[31] = 1
  211. *
  212. * 0 4 8 12 16 20 24 28
  213. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  214. *
  215. * For OR3, need:
  216. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  217. * disable buffer ctrl OR[19] = 0
  218. * CSNT OR[20] = 1
  219. * ACS OR[21:22] = 11
  220. * XACS OR[23] = 1
  221. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  222. * SETA OR[28] = 0
  223. * TRLX OR[29] = 1
  224. * EHTR OR[30] = 1
  225. * EAD extra time OR[31] = 1
  226. *
  227. * 0 4 8 12 16 20 24 28
  228. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  229. */
  230. #define CONFIG_FSL_CADMUS
  231. #define CADMUS_BASE_ADDR 0xf8000000
  232. #ifdef CONFIG_PHYS_64BIT
  233. #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
  234. #else
  235. #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
  236. #endif
  237. #define CONFIG_SYS_BR3_PRELIM \
  238. (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
  239. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  240. #define CONFIG_SYS_INIT_RAM_LOCK 1
  241. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  242. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  243. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  244. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  245. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  246. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  247. /* Serial Port */
  248. #define CONFIG_SYS_NS16550_SERIAL
  249. #define CONFIG_SYS_NS16550_REG_SIZE 1
  250. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  251. #define CONFIG_SYS_BAUDRATE_TABLE \
  252. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  253. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  254. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  255. /*
  256. * I2C
  257. */
  258. #ifndef CONFIG_DM_I2C
  259. #define CONFIG_SYS_I2C
  260. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  261. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  262. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  263. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  264. #else
  265. #define CONFIG_SYS_SPD_BUS_NUM 0
  266. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  267. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  268. #endif
  269. #define CONFIG_SYS_I2C_FSL
  270. /* EEPROM */
  271. #define CONFIG_ID_EEPROM
  272. #define CONFIG_SYS_I2C_EEPROM_CCID
  273. #define CONFIG_SYS_ID_EEPROM
  274. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  275. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  276. /*
  277. * General PCI
  278. * Memory space is mapped 1-1, but I/O space must start from 0.
  279. */
  280. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  281. #ifdef CONFIG_PHYS_64BIT
  282. #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
  283. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
  284. #else
  285. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  286. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  287. #endif
  288. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  289. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  290. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  291. #ifdef CONFIG_PHYS_64BIT
  292. #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
  293. #else
  294. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  295. #endif
  296. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  297. #ifdef CONFIG_PCIE1
  298. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  299. #ifdef CONFIG_PHYS_64BIT
  300. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
  301. #else
  302. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  303. #endif
  304. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
  305. #ifdef CONFIG_PHYS_64BIT
  306. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
  307. #else
  308. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  309. #endif
  310. #endif
  311. /*
  312. * RapidIO MMU
  313. */
  314. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
  315. #ifdef CONFIG_PHYS_64BIT
  316. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
  317. #else
  318. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
  319. #endif
  320. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
  321. #ifdef CONFIG_LEGACY
  322. #define BRIDGE_ID 17
  323. #define VIA_ID 2
  324. #else
  325. #define BRIDGE_ID 28
  326. #define VIA_ID 4
  327. #endif
  328. #if defined(CONFIG_PCI)
  329. #undef CONFIG_TULIP
  330. #if !defined(CONFIG_DM_PCI)
  331. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  332. #define CONFIG_PCI_INDIRECT_BRIDGE 1
  333. #define CONFIG_SYS_PCIE1_NAME "Slot"
  334. #ifdef CONFIG_PHYS_64BIT
  335. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  336. #else
  337. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  338. #endif
  339. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  340. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  341. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  342. #endif
  343. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  344. #endif /* CONFIG_PCI */
  345. #if defined(CONFIG_TSEC_ENET)
  346. #define CONFIG_TSEC1 1
  347. #define CONFIG_TSEC1_NAME "eTSEC0"
  348. #define CONFIG_TSEC2 1
  349. #define CONFIG_TSEC2_NAME "eTSEC1"
  350. #define CONFIG_TSEC3 1
  351. #define CONFIG_TSEC3_NAME "eTSEC2"
  352. #define CONFIG_TSEC4
  353. #define CONFIG_TSEC4_NAME "eTSEC3"
  354. #undef CONFIG_MPC85XX_FEC
  355. #define TSEC1_PHY_ADDR 0
  356. #define TSEC2_PHY_ADDR 1
  357. #define TSEC3_PHY_ADDR 2
  358. #define TSEC4_PHY_ADDR 3
  359. #define TSEC1_PHYIDX 0
  360. #define TSEC2_PHYIDX 0
  361. #define TSEC3_PHYIDX 0
  362. #define TSEC4_PHYIDX 0
  363. #define TSEC1_FLAGS TSEC_GIGABIT
  364. #define TSEC2_FLAGS TSEC_GIGABIT
  365. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  366. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  367. /* Options are: eTSEC[0-3] */
  368. #define CONFIG_ETHPRIME "eTSEC0"
  369. #endif /* CONFIG_TSEC_ENET */
  370. /*
  371. * Environment
  372. */
  373. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  374. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  375. /*
  376. * BOOTP options
  377. */
  378. #define CONFIG_BOOTP_BOOTFILESIZE
  379. #undef CONFIG_WATCHDOG /* watchdog disabled */
  380. /*
  381. * Miscellaneous configurable options
  382. */
  383. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  384. /*
  385. * For booting Linux, the board info and command line data
  386. * have to be in the first 64 MB of memory, since this is
  387. * the maximum mapped by the Linux kernel during initialization.
  388. */
  389. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  390. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  391. #if defined(CONFIG_CMD_KGDB)
  392. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  393. #endif
  394. /*
  395. * Environment Configuration
  396. */
  397. #if defined(CONFIG_TSEC_ENET)
  398. #define CONFIG_HAS_ETH0
  399. #define CONFIG_HAS_ETH1
  400. #define CONFIG_HAS_ETH2
  401. #define CONFIG_HAS_ETH3
  402. #endif
  403. #define CONFIG_IPADDR 192.168.1.253
  404. #define CONFIG_HOSTNAME "unknown"
  405. #define CONFIG_ROOTPATH "/nfsroot"
  406. #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
  407. #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
  408. #define CONFIG_SERVERIP 192.168.1.1
  409. #define CONFIG_GATEWAYIP 192.168.1.1
  410. #define CONFIG_NETMASK 255.255.255.0
  411. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  412. #define CONFIG_EXTRA_ENV_SETTINGS \
  413. "hwconfig=fsl_ddr:ecc=off\0" \
  414. "netdev=eth0\0" \
  415. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  416. "tftpflash=tftpboot $loadaddr $uboot; " \
  417. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  418. " +$filesize; " \
  419. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  420. " +$filesize; " \
  421. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  422. " $filesize; " \
  423. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  424. " +$filesize; " \
  425. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  426. " $filesize\0" \
  427. "consoledev=ttyS1\0" \
  428. "ramdiskaddr=2000000\0" \
  429. "ramdiskfile=ramdisk.uboot\0" \
  430. "fdtaddr=1e00000\0" \
  431. "fdtfile=mpc8548cds.dtb\0"
  432. #define CONFIG_NFSBOOTCOMMAND \
  433. "setenv bootargs root=/dev/nfs rw " \
  434. "nfsroot=$serverip:$rootpath " \
  435. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  436. "console=$consoledev,$baudrate $othbootargs;" \
  437. "tftp $loadaddr $bootfile;" \
  438. "tftp $fdtaddr $fdtfile;" \
  439. "bootm $loadaddr - $fdtaddr"
  440. #define CONFIG_RAMBOOTCOMMAND \
  441. "setenv bootargs root=/dev/ram rw " \
  442. "console=$consoledev,$baudrate $othbootargs;" \
  443. "tftp $ramdiskaddr $ramdiskfile;" \
  444. "tftp $loadaddr $bootfile;" \
  445. "tftp $fdtaddr $fdtfile;" \
  446. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  447. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  448. #endif /* __CONFIG_H */