M5249EVB.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the esd TASREG board.
  4. *
  5. * (C) Copyright 2004
  6. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5249EVB_H
  12. #define _M5249EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFTMR
  18. #define CONFIG_MCFUART
  19. #define CONFIG_SYS_UART_PORT (0)
  20. #undef CONFIG_WATCHDOG
  21. #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
  22. /*
  23. * BOOTP options
  24. */
  25. #undef CONFIG_BOOTP_BOOTFILESIZE
  26. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  27. #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
  28. /*
  29. * Clock configuration: enable only one of the following options
  30. */
  31. #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
  32. #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
  33. #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
  34. /*
  35. * Low Level Configuration Settings
  36. * (address mappings, register initial values, etc.)
  37. * You should know what you are doing if you make changes here.
  38. */
  39. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  40. #define CONFIG_SYS_MBAR2 0x80000000
  41. /*-----------------------------------------------------------------------
  42. * Definitions for initial stack pointer and data area (in DPRAM)
  43. */
  44. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  45. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  46. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  47. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  48. #define LDS_BOARD_TEXT \
  49. . = DEFINED(env_offset) ? env_offset : .; \
  50. env/embedded.o(.text);
  51. /*-----------------------------------------------------------------------
  52. * Start addresses for the final memory configuration
  53. * (Set up by the startup code)
  54. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  55. */
  56. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  57. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  58. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  59. #if 0 /* test-only */
  60. #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
  61. #endif
  62. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  63. #define CONFIG_SYS_MONITOR_LEN 0x20000
  64. #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
  65. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  66. /*
  67. * For booting Linux, the board info and command line data
  68. * have to be in the first 8 MB of memory, since this is
  69. * the maximum mapped by the Linux kernel during initialization ??
  70. */
  71. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  72. /*-----------------------------------------------------------------------
  73. * FLASH organization
  74. */
  75. #ifdef CONFIG_SYS_FLASH_CFI
  76. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  77. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  78. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  79. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  80. # define CONFIG_SYS_FLASH_CHECKSUM
  81. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  82. #endif
  83. /*-----------------------------------------------------------------------
  84. * Cache Configuration
  85. */
  86. #define CONFIG_SYS_CACHELINE_SIZE 16
  87. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  88. CONFIG_SYS_INIT_RAM_SIZE - 8)
  89. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  90. CONFIG_SYS_INIT_RAM_SIZE - 4)
  91. #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
  92. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
  93. CF_ADDRMASK(2) | \
  94. CF_ACR_EN | CF_ACR_SM_ALL)
  95. #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
  96. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  97. CF_ACR_EN | CF_ACR_SM_ALL)
  98. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
  99. CF_CACR_DBWE)
  100. /*-----------------------------------------------------------------------
  101. * Memory bank definitions
  102. */
  103. /* CS0 - AMD Flash, address 0xffc00000 */
  104. #define CONFIG_SYS_CS0_BASE 0xffe00000
  105. #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
  106. /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
  107. #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
  108. /* CS1 - FPGA, address 0xe0000000 */
  109. #define CONFIG_SYS_CS1_BASE 0xe0000000
  110. #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
  111. #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
  112. /*-----------------------------------------------------------------------
  113. * Port configuration
  114. */
  115. #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
  116. #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
  117. #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
  118. #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
  119. #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
  120. #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
  121. #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
  122. #endif /* M5249 */