am65-cpsw-nuss.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
  4. *
  5. * Copyright (C) 2019, Texas Instruments, Incorporated
  6. *
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <asm/processor.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <dm/device_compat.h>
  16. #include <dm/lists.h>
  17. #include <dma-uclass.h>
  18. #include <dm/of_access.h>
  19. #include <miiphy.h>
  20. #include <net.h>
  21. #include <phy.h>
  22. #include <power-domain.h>
  23. #include <linux/bitops.h>
  24. #include <linux/soc/ti/ti-udma.h>
  25. #include "cpsw_mdio.h"
  26. #define AM65_CPSW_CPSWNU_MAX_PORTS 2
  27. #define AM65_CPSW_SS_BASE 0x0
  28. #define AM65_CPSW_SGMII_BASE 0x100
  29. #define AM65_CPSW_MDIO_BASE 0xf00
  30. #define AM65_CPSW_XGMII_BASE 0x2100
  31. #define AM65_CPSW_CPSW_NU_BASE 0x20000
  32. #define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
  33. #define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000
  34. #define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET 0x330
  35. #define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
  36. #define AM65_CPSW_CTL_REG 0x4
  37. #define AM65_CPSW_STAT_PORT_EN_REG 0x14
  38. #define AM65_CPSW_PTYPE_REG 0x18
  39. #define AM65_CPSW_CTL_REG_P0_ENABLE BIT(2)
  40. #define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13)
  41. #define AM65_CPSW_CTL_REG_P0_RX_PAD BIT(14)
  42. #define AM65_CPSW_P0_FLOW_ID_REG 0x8
  43. #define AM65_CPSW_PN_RX_MAXLEN_REG 0x24
  44. #define AM65_CPSW_PN_REG_SA_L 0x308
  45. #define AM65_CPSW_PN_REG_SA_H 0x30c
  46. #define AM65_CPSW_ALE_CTL_REG 0x8
  47. #define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
  48. #define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
  49. #define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4)
  50. #define AM65_CPSW_ALE_PN_CTL_REG(x) (0x40 + (x) * 4)
  51. #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3
  52. #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11)
  53. #define AM65_CPSW_ALE_THREADMAPDEF_REG 0x134
  54. #define AM65_CPSW_ALE_DEFTHREAD_EN BIT(15)
  55. #define AM65_CPSW_MACSL_CTL_REG 0x0
  56. #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15)
  57. #define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18)
  58. #define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7)
  59. #define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5)
  60. #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1)
  61. #define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX BIT(0)
  62. #define AM65_CPSW_MACSL_RESET_REG 0x8
  63. #define AM65_CPSW_MACSL_RESET_REG_RESET BIT(0)
  64. #define AM65_CPSW_MACSL_STATUS_REG 0x4
  65. #define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31)
  66. #define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE BIT(30)
  67. #define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE BIT(29)
  68. #define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28)
  69. #define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
  70. (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
  71. AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
  72. AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
  73. AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
  74. #define AM65_CPSW_CPPI_PKT_TYPE 0x7
  75. struct am65_cpsw_port {
  76. fdt_addr_t port_base;
  77. fdt_addr_t macsl_base;
  78. bool disabled;
  79. u32 mac_control;
  80. };
  81. struct am65_cpsw_common {
  82. struct udevice *dev;
  83. fdt_addr_t ss_base;
  84. fdt_addr_t cpsw_base;
  85. fdt_addr_t mdio_base;
  86. fdt_addr_t ale_base;
  87. fdt_addr_t gmii_sel;
  88. fdt_addr_t mac_efuse;
  89. struct clk fclk;
  90. struct power_domain pwrdmn;
  91. u32 port_num;
  92. struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
  93. struct mii_dev *bus;
  94. u32 bus_freq;
  95. struct dma dma_tx;
  96. struct dma dma_rx;
  97. u32 rx_next;
  98. u32 rx_pend;
  99. bool started;
  100. };
  101. struct am65_cpsw_priv {
  102. struct udevice *dev;
  103. struct am65_cpsw_common *cpsw_common;
  104. u32 port_id;
  105. struct phy_device *phydev;
  106. bool has_phy;
  107. ofnode phy_node;
  108. u32 phy_addr;
  109. };
  110. #ifdef PKTSIZE_ALIGN
  111. #define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
  112. #else
  113. #define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
  114. #endif
  115. #ifdef PKTBUFSRX
  116. #define UDMA_RX_DESC_NUM PKTBUFSRX
  117. #else
  118. #define UDMA_RX_DESC_NUM 4
  119. #endif
  120. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  121. ((mac)[2] << 16) | ((mac)[3] << 24))
  122. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  123. static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
  124. unsigned char *addr)
  125. {
  126. writel(mac_hi(addr),
  127. slave->port_base + AM65_CPSW_PN_REG_SA_H);
  128. writel(mac_lo(addr),
  129. slave->port_base + AM65_CPSW_PN_REG_SA_L);
  130. }
  131. int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
  132. {
  133. u32 i = 100;
  134. /* Set the soft reset bit */
  135. writel(AM65_CPSW_MACSL_RESET_REG_RESET,
  136. slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
  137. while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
  138. AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
  139. cpu_relax();
  140. /* Timeout on the reset */
  141. return i;
  142. }
  143. static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
  144. {
  145. u32 i = 100;
  146. while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
  147. AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
  148. cpu_relax();
  149. return i;
  150. }
  151. static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
  152. {
  153. struct am65_cpsw_common *common = priv->cpsw_common;
  154. struct am65_cpsw_port *port = &common->ports[priv->port_id];
  155. struct phy_device *phy = priv->phydev;
  156. u32 mac_control = 0;
  157. if (phy->link) { /* link up */
  158. mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
  159. AM65_CPSW_MACSL_CTL_REG_GMII_EN;
  160. if (phy->speed == 1000)
  161. mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
  162. if (phy->speed == 10 && phy_interface_is_rgmii(phy))
  163. /* Can be used with in band mode only */
  164. mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
  165. if (phy->duplex == DUPLEX_FULL)
  166. mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
  167. if (phy->speed == 100)
  168. mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
  169. }
  170. if (mac_control == port->mac_control)
  171. goto out;
  172. if (mac_control) {
  173. printf("link up on port %d, speed %d, %s duplex\n",
  174. priv->port_id, phy->speed,
  175. (phy->duplex == DUPLEX_FULL) ? "full" : "half");
  176. } else {
  177. printf("link down on port %d\n", priv->port_id);
  178. }
  179. writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
  180. port->mac_control = mac_control;
  181. out:
  182. return phy->link;
  183. }
  184. #define AM65_GMII_SEL_MODE_MII 0
  185. #define AM65_GMII_SEL_MODE_RMII 1
  186. #define AM65_GMII_SEL_MODE_RGMII 2
  187. #define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
  188. static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
  189. phy_interface_t phy_mode, int slave)
  190. {
  191. struct am65_cpsw_common *common = priv->cpsw_common;
  192. u32 reg;
  193. u32 mode = 0;
  194. bool rgmii_id = false;
  195. reg = readl(common->gmii_sel);
  196. dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
  197. switch (phy_mode) {
  198. case PHY_INTERFACE_MODE_RMII:
  199. mode = AM65_GMII_SEL_MODE_RMII;
  200. break;
  201. case PHY_INTERFACE_MODE_RGMII:
  202. case PHY_INTERFACE_MODE_RGMII_RXID:
  203. mode = AM65_GMII_SEL_MODE_RGMII;
  204. break;
  205. case PHY_INTERFACE_MODE_RGMII_ID:
  206. case PHY_INTERFACE_MODE_RGMII_TXID:
  207. mode = AM65_GMII_SEL_MODE_RGMII;
  208. rgmii_id = true;
  209. break;
  210. default:
  211. dev_warn(common->dev,
  212. "Unsupported PHY mode: %u. Defaulting to MII.\n",
  213. phy_mode);
  214. /* fallthrough */
  215. case PHY_INTERFACE_MODE_MII:
  216. mode = AM65_GMII_SEL_MODE_MII;
  217. break;
  218. };
  219. if (rgmii_id)
  220. mode |= AM65_GMII_SEL_RGMII_IDMODE;
  221. reg = mode;
  222. dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
  223. phy_mode, reg);
  224. writel(reg, common->gmii_sel);
  225. reg = readl(common->gmii_sel);
  226. if (reg != mode)
  227. dev_err(common->dev,
  228. "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
  229. mode, reg);
  230. }
  231. static int am65_cpsw_start(struct udevice *dev)
  232. {
  233. struct eth_pdata *pdata = dev_get_platdata(dev);
  234. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  235. struct am65_cpsw_common *common = priv->cpsw_common;
  236. struct am65_cpsw_port *port = &common->ports[priv->port_id];
  237. struct am65_cpsw_port *port0 = &common->ports[0];
  238. struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data;
  239. int ret, i;
  240. ret = power_domain_on(&common->pwrdmn);
  241. if (ret) {
  242. dev_err(dev, "power_domain_on() failed %d\n", ret);
  243. goto out;
  244. }
  245. ret = clk_enable(&common->fclk);
  246. if (ret) {
  247. dev_err(dev, "clk enabled failed %d\n", ret);
  248. goto err_off_pwrdm;
  249. }
  250. common->rx_next = 0;
  251. common->rx_pend = 0;
  252. ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
  253. if (ret) {
  254. dev_err(dev, "TX dma get failed %d\n", ret);
  255. goto err_off_clk;
  256. }
  257. ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
  258. if (ret) {
  259. dev_err(dev, "RX dma get failed %d\n", ret);
  260. goto err_free_tx;
  261. }
  262. for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
  263. ret = dma_prepare_rcv_buf(&common->dma_rx,
  264. net_rx_packets[i],
  265. UDMA_RX_BUF_SIZE);
  266. if (ret) {
  267. dev_err(dev, "RX dma add buf failed %d\n", ret);
  268. goto err_free_tx;
  269. }
  270. }
  271. ret = dma_enable(&common->dma_tx);
  272. if (ret) {
  273. dev_err(dev, "TX dma_enable failed %d\n", ret);
  274. goto err_free_rx;
  275. }
  276. ret = dma_enable(&common->dma_rx);
  277. if (ret) {
  278. dev_err(dev, "RX dma_enable failed %d\n", ret);
  279. goto err_dis_tx;
  280. }
  281. /* Control register */
  282. writel(AM65_CPSW_CTL_REG_P0_ENABLE |
  283. AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
  284. AM65_CPSW_CTL_REG_P0_RX_PAD,
  285. common->cpsw_base + AM65_CPSW_CTL_REG);
  286. /* disable priority elevation */
  287. writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
  288. /* enable statistics */
  289. writel(BIT(0) | BIT(priv->port_id),
  290. common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
  291. /* Port 0 length register */
  292. writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
  293. /* set base flow_id */
  294. dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data);
  295. writel(dma_rx_cfg_data->flow_id_base,
  296. port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
  297. dev_info(dev, "K3 CPSW: rflow_id_base: %u\n",
  298. dma_rx_cfg_data->flow_id_base);
  299. /* Reset and enable the ALE */
  300. writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
  301. AM65_CPSW_ALE_CTL_REG_BYPASS,
  302. common->ale_base + AM65_CPSW_ALE_CTL_REG);
  303. /* port 0 put into forward mode */
  304. writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
  305. common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
  306. writel(AM65_CPSW_ALE_DEFTHREAD_EN,
  307. common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG);
  308. /* PORT x configuration */
  309. /* Port x Max length register */
  310. writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
  311. /* Port x set mac */
  312. am65_cpsw_set_sl_mac(port, pdata->enetaddr);
  313. /* Port x ALE: mac_only, Forwarding */
  314. writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
  315. AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
  316. common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
  317. port->mac_control = 0;
  318. if (!am65_cpsw_macsl_reset(port)) {
  319. dev_err(dev, "mac_sl reset failed\n");
  320. ret = -EFAULT;
  321. goto err_dis_rx;
  322. }
  323. ret = phy_startup(priv->phydev);
  324. if (ret) {
  325. dev_err(dev, "phy_startup failed\n");
  326. goto err_dis_rx;
  327. }
  328. ret = am65_cpsw_update_link(priv);
  329. if (!ret) {
  330. ret = -ENODEV;
  331. goto err_phy_shutdown;
  332. }
  333. common->started = true;
  334. return 0;
  335. err_phy_shutdown:
  336. phy_shutdown(priv->phydev);
  337. err_dis_rx:
  338. /* disable ports */
  339. writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
  340. writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
  341. if (!am65_cpsw_macsl_wait_for_idle(port))
  342. dev_err(dev, "mac_sl idle timeout\n");
  343. writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
  344. writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
  345. writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
  346. dma_disable(&common->dma_rx);
  347. err_dis_tx:
  348. dma_disable(&common->dma_tx);
  349. err_free_rx:
  350. dma_free(&common->dma_rx);
  351. err_free_tx:
  352. dma_free(&common->dma_tx);
  353. err_off_clk:
  354. clk_disable(&common->fclk);
  355. err_off_pwrdm:
  356. power_domain_off(&common->pwrdmn);
  357. out:
  358. dev_err(dev, "%s end error\n", __func__);
  359. return ret;
  360. }
  361. static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
  362. {
  363. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  364. struct am65_cpsw_common *common = priv->cpsw_common;
  365. struct ti_udma_drv_packet_data packet_data;
  366. int ret;
  367. packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
  368. packet_data.dest_tag = priv->port_id;
  369. ret = dma_send(&common->dma_tx, packet, length, &packet_data);
  370. if (ret) {
  371. dev_err(dev, "TX dma_send failed %d\n", ret);
  372. return ret;
  373. }
  374. return 0;
  375. }
  376. static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
  377. {
  378. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  379. struct am65_cpsw_common *common = priv->cpsw_common;
  380. /* try to receive a new packet */
  381. return dma_receive(&common->dma_rx, (void **)packetp, NULL);
  382. }
  383. static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
  384. {
  385. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  386. struct am65_cpsw_common *common = priv->cpsw_common;
  387. int ret;
  388. if (length > 0) {
  389. u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
  390. ret = dma_prepare_rcv_buf(&common->dma_rx,
  391. net_rx_packets[pkt],
  392. UDMA_RX_BUF_SIZE);
  393. if (ret)
  394. dev_err(dev, "RX dma free_pkt failed %d\n", ret);
  395. common->rx_next++;
  396. }
  397. return 0;
  398. }
  399. static void am65_cpsw_stop(struct udevice *dev)
  400. {
  401. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  402. struct am65_cpsw_common *common = priv->cpsw_common;
  403. struct am65_cpsw_port *port = &common->ports[priv->port_id];
  404. if (!common->started)
  405. return;
  406. phy_shutdown(priv->phydev);
  407. writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
  408. writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
  409. if (!am65_cpsw_macsl_wait_for_idle(port))
  410. dev_err(dev, "mac_sl idle timeout\n");
  411. writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
  412. writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
  413. writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
  414. dma_disable(&common->dma_tx);
  415. dma_free(&common->dma_tx);
  416. dma_disable(&common->dma_rx);
  417. dma_free(&common->dma_rx);
  418. common->started = false;
  419. }
  420. static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
  421. {
  422. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  423. struct am65_cpsw_common *common = priv->cpsw_common;
  424. struct eth_pdata *pdata = dev_get_platdata(dev);
  425. u32 mac_hi, mac_lo;
  426. if (common->mac_efuse == FDT_ADDR_T_NONE)
  427. return -1;
  428. mac_lo = readl(common->mac_efuse);
  429. mac_hi = readl(common->mac_efuse + 4);
  430. pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
  431. pdata->enetaddr[1] = mac_hi & 0xff;
  432. pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
  433. pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
  434. pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
  435. pdata->enetaddr[5] = mac_lo & 0xff;
  436. return 0;
  437. }
  438. static const struct eth_ops am65_cpsw_ops = {
  439. .start = am65_cpsw_start,
  440. .send = am65_cpsw_send,
  441. .recv = am65_cpsw_recv,
  442. .free_pkt = am65_cpsw_free_pkt,
  443. .stop = am65_cpsw_stop,
  444. .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
  445. };
  446. static int am65_cpsw_mdio_init(struct udevice *dev)
  447. {
  448. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  449. struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
  450. if (!priv->has_phy || cpsw_common->bus)
  451. return 0;
  452. cpsw_common->bus = cpsw_mdio_init(dev->name,
  453. cpsw_common->mdio_base,
  454. cpsw_common->bus_freq,
  455. clk_get_rate(&cpsw_common->fclk));
  456. if (!cpsw_common->bus)
  457. return -EFAULT;
  458. return 0;
  459. }
  460. static int am65_cpsw_phy_init(struct udevice *dev)
  461. {
  462. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  463. struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
  464. struct eth_pdata *pdata = dev_get_platdata(dev);
  465. struct phy_device *phydev;
  466. u32 supported = PHY_GBIT_FEATURES;
  467. int ret;
  468. phydev = phy_connect(cpsw_common->bus,
  469. priv->phy_addr,
  470. priv->dev,
  471. pdata->phy_interface);
  472. if (!phydev) {
  473. dev_err(dev, "phy_connect() failed\n");
  474. return -ENODEV;
  475. }
  476. phydev->supported &= supported;
  477. if (pdata->max_speed) {
  478. ret = phy_set_supported(phydev, pdata->max_speed);
  479. if (ret)
  480. return ret;
  481. }
  482. phydev->advertising = phydev->supported;
  483. if (ofnode_valid(priv->phy_node))
  484. phydev->node = priv->phy_node;
  485. priv->phydev = phydev;
  486. ret = phy_config(phydev);
  487. if (ret < 0)
  488. pr_err("phy_config() failed: %d", ret);
  489. return ret;
  490. }
  491. static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
  492. {
  493. struct eth_pdata *pdata = dev_get_platdata(dev);
  494. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  495. struct ofnode_phandle_args out_args;
  496. const char *phy_mode;
  497. int ret = 0;
  498. phy_mode = ofnode_read_string(port_np, "phy-mode");
  499. if (phy_mode) {
  500. pdata->phy_interface =
  501. phy_get_interface_by_name(phy_mode);
  502. if (pdata->phy_interface == -1) {
  503. dev_err(dev, "Invalid PHY mode '%s', port %u\n",
  504. phy_mode, priv->port_id);
  505. ret = -EINVAL;
  506. goto out;
  507. }
  508. }
  509. ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
  510. if (pdata->max_speed)
  511. dev_err(dev, "Port %u speed froced to %uMbit\n",
  512. priv->port_id, pdata->max_speed);
  513. priv->has_phy = true;
  514. ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
  515. NULL, 0, 0, &out_args);
  516. if (ret) {
  517. dev_err(dev, "can't parse phy-handle port %u (%d)\n",
  518. priv->port_id, ret);
  519. priv->has_phy = false;
  520. ret = 0;
  521. }
  522. priv->phy_node = out_args.node;
  523. if (priv->has_phy) {
  524. ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
  525. if (ret) {
  526. dev_err(dev, "failed to get phy_addr port %u (%d)\n",
  527. priv->port_id, ret);
  528. goto out;
  529. }
  530. }
  531. out:
  532. return ret;
  533. }
  534. static int am65_cpsw_probe_cpsw(struct udevice *dev)
  535. {
  536. struct am65_cpsw_priv *priv = dev_get_priv(dev);
  537. struct eth_pdata *pdata = dev_get_platdata(dev);
  538. struct am65_cpsw_common *cpsw_common;
  539. ofnode ports_np, node;
  540. int ret, i;
  541. priv->dev = dev;
  542. cpsw_common = calloc(1, sizeof(*priv->cpsw_common));
  543. if (!cpsw_common)
  544. return -ENOMEM;
  545. priv->cpsw_common = cpsw_common;
  546. cpsw_common->dev = dev;
  547. cpsw_common->ss_base = dev_read_addr(dev);
  548. if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
  549. return -EINVAL;
  550. cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
  551. /* no err check - optional */
  552. ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
  553. if (ret) {
  554. dev_err(dev, "failed to get pwrdmn: %d\n", ret);
  555. return ret;
  556. }
  557. ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
  558. if (ret) {
  559. power_domain_free(&cpsw_common->pwrdmn);
  560. dev_err(dev, "failed to get clock %d\n", ret);
  561. return ret;
  562. }
  563. cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
  564. cpsw_common->ale_base = cpsw_common->cpsw_base +
  565. AM65_CPSW_CPSW_NU_ALE_BASE;
  566. cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
  567. ports_np = dev_read_subnode(dev, "ethernet-ports");
  568. if (!ofnode_valid(ports_np)) {
  569. ret = -ENOENT;
  570. goto out;
  571. }
  572. ofnode_for_each_subnode(node, ports_np) {
  573. const char *node_name;
  574. u32 port_id;
  575. bool disabled;
  576. node_name = ofnode_get_name(node);
  577. disabled = !ofnode_is_available(node);
  578. ret = ofnode_read_u32(node, "reg", &port_id);
  579. if (ret) {
  580. dev_err(dev, "%s: failed to get port_id (%d)\n",
  581. node_name, ret);
  582. goto out;
  583. }
  584. if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
  585. dev_err(dev, "%s: invalid port_id (%d)\n",
  586. node_name, port_id);
  587. ret = -EINVAL;
  588. goto out;
  589. }
  590. cpsw_common->port_num++;
  591. if (!port_id)
  592. continue;
  593. priv->port_id = port_id;
  594. cpsw_common->ports[port_id].disabled = disabled;
  595. if (disabled)
  596. continue;
  597. ret = am65_cpsw_ofdata_parse_phy(dev, node);
  598. if (ret)
  599. goto out;
  600. }
  601. for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
  602. struct am65_cpsw_port *port = &cpsw_common->ports[i];
  603. port->port_base = cpsw_common->cpsw_base +
  604. AM65_CPSW_CPSW_NU_PORTS_OFFSET +
  605. (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
  606. port->macsl_base = port->port_base +
  607. AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
  608. }
  609. node = dev_read_subnode(dev, "cpsw-phy-sel");
  610. if (!ofnode_valid(node)) {
  611. dev_err(dev, "can't find cpsw-phy-sel\n");
  612. ret = -ENOENT;
  613. goto out;
  614. }
  615. cpsw_common->gmii_sel = ofnode_get_addr(node);
  616. if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
  617. dev_err(dev, "failed to get gmii_sel base\n");
  618. goto out;
  619. }
  620. cpsw_common->bus_freq =
  621. dev_read_u32_default(dev, "bus_freq",
  622. AM65_CPSW_MDIO_BUS_FREQ_DEF);
  623. am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
  624. ret = am65_cpsw_mdio_init(dev);
  625. if (ret)
  626. goto out;
  627. ret = am65_cpsw_phy_init(dev);
  628. if (ret)
  629. goto out;
  630. dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n",
  631. readl(cpsw_common->ss_base),
  632. readl(cpsw_common->cpsw_base),
  633. readl(cpsw_common->ale_base),
  634. cpsw_common->port_num,
  635. cpsw_common->bus_freq);
  636. out:
  637. clk_free(&cpsw_common->fclk);
  638. power_domain_free(&cpsw_common->pwrdmn);
  639. return ret;
  640. }
  641. static const struct udevice_id am65_cpsw_nuss_ids[] = {
  642. { .compatible = "ti,am654-cpsw-nuss" },
  643. { .compatible = "ti,j721e-cpsw-nuss" },
  644. { }
  645. };
  646. U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
  647. .name = "am65_cpsw_nuss_slave",
  648. .id = UCLASS_ETH,
  649. .of_match = am65_cpsw_nuss_ids,
  650. .probe = am65_cpsw_probe_cpsw,
  651. .ops = &am65_cpsw_ops,
  652. .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
  653. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  654. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  655. };