pcnet.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
  4. *
  5. * This driver for AMD PCnet network controllers is derived from the
  6. * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <memalign.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <asm/cache.h>
  18. #include <asm/io.h>
  19. #include <pci.h>
  20. #include <linux/delay.h>
  21. #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
  22. #define PCNET_DEBUG1(fmt,args...) \
  23. debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  24. #define PCNET_DEBUG2(fmt,args...) \
  25. debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  26. /*
  27. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  28. * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  29. * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  30. */
  31. #define PCNET_LOG_TX_BUFFERS 0
  32. #define PCNET_LOG_RX_BUFFERS 2
  33. #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
  34. #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
  35. #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
  36. #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
  37. #define PKT_BUF_SZ 1544
  38. /* The PCNET Rx and Tx ring descriptors. */
  39. struct pcnet_rx_head {
  40. u32 base;
  41. s16 buf_length;
  42. s16 status;
  43. u32 msg_length;
  44. u32 reserved;
  45. };
  46. struct pcnet_tx_head {
  47. u32 base;
  48. s16 length;
  49. s16 status;
  50. u32 misc;
  51. u32 reserved;
  52. };
  53. /* The PCNET 32-Bit initialization block, described in databook. */
  54. struct pcnet_init_block {
  55. u16 mode;
  56. u16 tlen_rlen;
  57. u8 phys_addr[6];
  58. u16 reserved;
  59. u32 filter[2];
  60. /* Receive and transmit ring base, along with extra bits. */
  61. u32 rx_ring;
  62. u32 tx_ring;
  63. u32 reserved2;
  64. };
  65. struct pcnet_uncached_priv {
  66. struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  67. struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  68. struct pcnet_init_block init_block;
  69. } __aligned(ARCH_DMA_MINALIGN);
  70. struct pcnet_priv {
  71. struct pcnet_uncached_priv ucp;
  72. /* Receive Buffer space */
  73. unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
  74. struct pcnet_uncached_priv *uc;
  75. #ifdef CONFIG_DM_ETH
  76. struct udevice *dev;
  77. const char *name;
  78. #else
  79. pci_dev_t dev;
  80. char *name;
  81. #endif
  82. void __iomem *iobase;
  83. u8 *enetaddr;
  84. u16 status;
  85. int cur_rx;
  86. int cur_tx;
  87. };
  88. /* Offsets from base I/O address for WIO mode */
  89. #define PCNET_RDP 0x10
  90. #define PCNET_RAP 0x12
  91. #define PCNET_RESET 0x14
  92. #define PCNET_BDP 0x16
  93. static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
  94. {
  95. writew(index, lp->iobase + PCNET_RAP);
  96. return readw(lp->iobase + PCNET_RDP);
  97. }
  98. static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
  99. {
  100. writew(index, lp->iobase + PCNET_RAP);
  101. writew(val, lp->iobase + PCNET_RDP);
  102. }
  103. static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
  104. {
  105. writew(index, lp->iobase + PCNET_RAP);
  106. return readw(lp->iobase + PCNET_BDP);
  107. }
  108. static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
  109. {
  110. writew(index, lp->iobase + PCNET_RAP);
  111. writew(val, lp->iobase + PCNET_BDP);
  112. }
  113. static void pcnet_reset(struct pcnet_priv *lp)
  114. {
  115. readw(lp->iobase + PCNET_RESET);
  116. }
  117. static int pcnet_check(struct pcnet_priv *lp)
  118. {
  119. writew(88, lp->iobase + PCNET_RAP);
  120. return readw(lp->iobase + PCNET_RAP) == 88;
  121. }
  122. static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
  123. {
  124. void *virt_addr = addr;
  125. #ifdef CONFIG_DM_ETH
  126. return dm_pci_virt_to_mem(lp->dev, virt_addr);
  127. #else
  128. return pci_virt_to_mem(lp->dev, virt_addr);
  129. #endif
  130. }
  131. static struct pci_device_id supported[] = {
  132. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
  133. {}
  134. };
  135. static int pcnet_probe_common(struct pcnet_priv *lp)
  136. {
  137. int chip_version;
  138. char *chipname;
  139. int i;
  140. /* Reset the PCnet controller */
  141. pcnet_reset(lp);
  142. /* Check if register access is working */
  143. if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
  144. printf("%s: CSR register access check failed\n", lp->name);
  145. return -1;
  146. }
  147. /* Identify the chip */
  148. chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
  149. if ((chip_version & 0xfff) != 0x003)
  150. return -1;
  151. chip_version = (chip_version >> 12) & 0xffff;
  152. switch (chip_version) {
  153. case 0x2621:
  154. chipname = "PCnet/PCI II 79C970A"; /* PCI */
  155. break;
  156. case 0x2625:
  157. chipname = "PCnet/FAST III 79C973"; /* PCI */
  158. break;
  159. case 0x2627:
  160. chipname = "PCnet/FAST III 79C975"; /* PCI */
  161. break;
  162. default:
  163. printf("%s: PCnet version %#x not supported\n",
  164. lp->name, chip_version);
  165. return -1;
  166. }
  167. PCNET_DEBUG1("AMD %s\n", chipname);
  168. /*
  169. * In most chips, after a chip reset, the ethernet address is read from
  170. * the station address PROM at the base address and programmed into the
  171. * "Physical Address Registers" CSR12-14.
  172. */
  173. for (i = 0; i < 3; i++) {
  174. unsigned int val;
  175. val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
  176. /* There may be endianness issues here. */
  177. lp->enetaddr[2 * i] = val & 0x0ff;
  178. lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
  179. }
  180. return 0;
  181. }
  182. static int pcnet_init_common(struct pcnet_priv *lp)
  183. {
  184. struct pcnet_uncached_priv *uc;
  185. int i, val;
  186. unsigned long addr;
  187. PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
  188. /* Switch pcnet to 32bit mode */
  189. pcnet_write_bcr(lp, 20, 2);
  190. /* Set/reset autoselect bit */
  191. val = pcnet_read_bcr(lp, 2) & ~2;
  192. val |= 2;
  193. pcnet_write_bcr(lp, 2, val);
  194. /* Enable auto negotiate, setup, disable fd */
  195. val = pcnet_read_bcr(lp, 32) & ~0x98;
  196. val |= 0x20;
  197. pcnet_write_bcr(lp, 32, val);
  198. /*
  199. * Enable NOUFLO on supported controllers, with the transmit
  200. * start point set to the full packet. This will cause entire
  201. * packets to be buffered by the ethernet controller before
  202. * transmission, eliminating underflows which are common on
  203. * slower devices. Controllers which do not support NOUFLO will
  204. * simply be left with a larger transmit FIFO threshold.
  205. */
  206. val = pcnet_read_bcr(lp, 18);
  207. val |= 1 << 11;
  208. pcnet_write_bcr(lp, 18, val);
  209. val = pcnet_read_csr(lp, 80);
  210. val |= 0x3 << 10;
  211. pcnet_write_csr(lp, 80, val);
  212. uc = lp->uc;
  213. uc->init_block.mode = cpu_to_le16(0x0000);
  214. uc->init_block.filter[0] = 0x00000000;
  215. uc->init_block.filter[1] = 0x00000000;
  216. /*
  217. * Initialize the Rx ring.
  218. */
  219. lp->cur_rx = 0;
  220. for (i = 0; i < RX_RING_SIZE; i++) {
  221. addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
  222. uc->rx_ring[i].base = cpu_to_le32(addr);
  223. uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
  224. uc->rx_ring[i].status = cpu_to_le16(0x8000);
  225. PCNET_DEBUG1
  226. ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
  227. uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
  228. uc->rx_ring[i].status);
  229. }
  230. /*
  231. * Initialize the Tx ring. The Tx buffer address is filled in as
  232. * needed, but we do need to clear the upper ownership bit.
  233. */
  234. lp->cur_tx = 0;
  235. for (i = 0; i < TX_RING_SIZE; i++) {
  236. uc->tx_ring[i].base = 0;
  237. uc->tx_ring[i].status = 0;
  238. }
  239. /*
  240. * Setup Init Block.
  241. */
  242. PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
  243. for (i = 0; i < 6; i++) {
  244. lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
  245. PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
  246. }
  247. uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
  248. RX_RING_LEN_BITS);
  249. addr = pcnet_virt_to_mem(lp, uc->rx_ring);
  250. uc->init_block.rx_ring = cpu_to_le32(addr);
  251. addr = pcnet_virt_to_mem(lp, uc->tx_ring);
  252. uc->init_block.tx_ring = cpu_to_le32(addr);
  253. PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
  254. uc->init_block.tlen_rlen,
  255. uc->init_block.rx_ring, uc->init_block.tx_ring);
  256. /*
  257. * Tell the controller where the Init Block is located.
  258. */
  259. barrier();
  260. addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
  261. pcnet_write_csr(lp, 1, addr & 0xffff);
  262. pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
  263. pcnet_write_csr(lp, 4, 0x0915);
  264. pcnet_write_csr(lp, 0, 0x0001); /* start */
  265. /* Wait for Init Done bit */
  266. for (i = 10000; i > 0; i--) {
  267. if (pcnet_read_csr(lp, 0) & 0x0100)
  268. break;
  269. udelay(10);
  270. }
  271. if (i <= 0) {
  272. printf("%s: TIMEOUT: controller init failed\n", lp->name);
  273. pcnet_reset(lp);
  274. return -1;
  275. }
  276. /*
  277. * Finally start network controller operation.
  278. */
  279. pcnet_write_csr(lp, 0, 0x0002);
  280. return 0;
  281. }
  282. static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
  283. {
  284. int i, status;
  285. u32 addr;
  286. struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
  287. PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
  288. packet);
  289. flush_dcache_range((unsigned long)packet,
  290. (unsigned long)packet + pkt_len);
  291. /* Wait for completion by testing the OWN bit */
  292. for (i = 1000; i > 0; i--) {
  293. status = readw(&entry->status);
  294. if ((status & 0x8000) == 0)
  295. break;
  296. udelay(100);
  297. PCNET_DEBUG2(".");
  298. }
  299. if (i <= 0) {
  300. printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
  301. lp->name, lp->cur_tx, status);
  302. pkt_len = 0;
  303. goto failure;
  304. }
  305. /*
  306. * Setup Tx ring. Caution: the write order is important here,
  307. * set the status with the "ownership" bits last.
  308. */
  309. addr = pcnet_virt_to_mem(lp, packet);
  310. writew(-pkt_len, &entry->length);
  311. writel(0, &entry->misc);
  312. writel(addr, &entry->base);
  313. writew(0x8300, &entry->status);
  314. /* Trigger an immediate send poll. */
  315. pcnet_write_csr(lp, 0, 0x0008);
  316. failure:
  317. if (++lp->cur_tx >= TX_RING_SIZE)
  318. lp->cur_tx = 0;
  319. PCNET_DEBUG2("done\n");
  320. return pkt_len;
  321. }
  322. static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
  323. {
  324. struct pcnet_rx_head *entry;
  325. unsigned char *buf;
  326. int pkt_len = 0;
  327. u16 err_status;
  328. entry = &lp->uc->rx_ring[lp->cur_rx];
  329. /*
  330. * If we own the next entry, it's a new packet. Send it up.
  331. */
  332. lp->status = readw(&entry->status);
  333. if ((lp->status & 0x8000) != 0)
  334. return 0;
  335. err_status = lp->status >> 8;
  336. if (err_status != 0x03) { /* There was an error. */
  337. printf("%s: Rx%d", lp->name, lp->cur_rx);
  338. PCNET_DEBUG1(" (status=0x%x)", err_status);
  339. if (err_status & 0x20)
  340. printf(" Frame");
  341. if (err_status & 0x10)
  342. printf(" Overflow");
  343. if (err_status & 0x08)
  344. printf(" CRC");
  345. if (err_status & 0x04)
  346. printf(" Fifo");
  347. printf(" Error\n");
  348. lp->status &= 0x03ff;
  349. return 0;
  350. }
  351. pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
  352. if (pkt_len < 60) {
  353. printf("%s: Rx%d: invalid packet length %d\n",
  354. lp->name, lp->cur_rx, pkt_len);
  355. return 0;
  356. }
  357. *bufp = lp->rx_buf[lp->cur_rx];
  358. invalidate_dcache_range((unsigned long)*bufp,
  359. (unsigned long)*bufp + pkt_len);
  360. PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
  361. lp->cur_rx, pkt_len, buf);
  362. return pkt_len;
  363. }
  364. static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
  365. {
  366. struct pcnet_rx_head *entry;
  367. entry = &lp->uc->rx_ring[lp->cur_rx];
  368. lp->status |= 0x8000;
  369. writew(lp->status, &entry->status);
  370. if (++lp->cur_rx >= RX_RING_SIZE)
  371. lp->cur_rx = 0;
  372. }
  373. static void pcnet_halt_common(struct pcnet_priv *lp)
  374. {
  375. int i;
  376. PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
  377. /* Reset the PCnet controller */
  378. pcnet_reset(lp);
  379. /* Wait for Stop bit */
  380. for (i = 1000; i > 0; i--) {
  381. if (pcnet_read_csr(lp, 0) & 0x4)
  382. break;
  383. udelay(10);
  384. }
  385. if (i <= 0)
  386. printf("%s: TIMEOUT: controller reset failed\n", lp->name);
  387. }
  388. #ifndef CONFIG_DM_ETH
  389. static int pcnet_init(struct eth_device *dev, bd_t *bis)
  390. {
  391. struct pcnet_priv *lp = dev->priv;
  392. return pcnet_init_common(lp);
  393. }
  394. static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
  395. {
  396. struct pcnet_priv *lp = dev->priv;
  397. return pcnet_send_common(lp, packet, pkt_len);
  398. }
  399. static int pcnet_recv(struct eth_device *dev)
  400. {
  401. struct pcnet_priv *lp = dev->priv;
  402. uchar *packet;
  403. int ret;
  404. ret = pcnet_recv_common(lp, &packet);
  405. if (ret > 0)
  406. net_process_received_packet(packet, ret);
  407. if (ret)
  408. pcnet_free_pkt_common(lp, ret);
  409. return ret;
  410. }
  411. static void pcnet_halt(struct eth_device *dev)
  412. {
  413. struct pcnet_priv *lp = dev->priv;
  414. pcnet_halt_common(lp);
  415. }
  416. int pcnet_initialize(bd_t *bis)
  417. {
  418. pci_dev_t devbusfn;
  419. struct eth_device *dev;
  420. struct pcnet_priv *lp;
  421. u16 command, status;
  422. int dev_nr = 0;
  423. u32 bar;
  424. PCNET_DEBUG1("\n%s...\n", __func__);
  425. for (dev_nr = 0; ; dev_nr++) {
  426. /*
  427. * Find the PCnet PCI device(s).
  428. */
  429. devbusfn = pci_find_devices(supported, dev_nr);
  430. if (devbusfn < 0)
  431. break;
  432. /*
  433. * Allocate and pre-fill the device structure.
  434. */
  435. dev = calloc(1, sizeof(*dev));
  436. if (!dev) {
  437. printf("pcnet: Can not allocate memory\n");
  438. break;
  439. }
  440. /*
  441. * We only maintain one structure because the drivers will
  442. * never be used concurrently. In 32bit mode the RX and TX
  443. * ring entries must be aligned on 16-byte boundaries.
  444. */
  445. lp = malloc_cache_aligned(sizeof(*lp));
  446. lp->uc = map_physmem((phys_addr_t)&lp->ucp,
  447. sizeof(lp->ucp), MAP_NOCACHE);
  448. lp->dev = devbusfn;
  449. flush_dcache_range((unsigned long)lp,
  450. (unsigned long)lp + sizeof(*lp));
  451. dev->priv = lp;
  452. sprintf(dev->name, "pcnet#%d", dev_nr);
  453. lp->name = dev->name;
  454. lp->enetaddr = dev->enetaddr;
  455. /*
  456. * Setup the PCI device.
  457. */
  458. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
  459. lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
  460. PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
  461. lp->name, devbusfn, lp->iobase);
  462. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  463. pci_write_config_word(devbusfn, PCI_COMMAND, command);
  464. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  465. if ((status & command) != command) {
  466. printf("%s: Couldn't enable IO access or Bus Mastering\n",
  467. lp->name);
  468. free(dev);
  469. continue;
  470. }
  471. pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
  472. /*
  473. * Probe the PCnet chip.
  474. */
  475. if (pcnet_probe_common(lp) < 0) {
  476. free(dev);
  477. continue;
  478. }
  479. /*
  480. * Setup device structure and register the driver.
  481. */
  482. dev->init = pcnet_init;
  483. dev->halt = pcnet_halt;
  484. dev->send = pcnet_send;
  485. dev->recv = pcnet_recv;
  486. eth_register(dev);
  487. }
  488. udelay(10 * 1000);
  489. return dev_nr;
  490. }
  491. #else /* DM_ETH */
  492. static int pcnet_start(struct udevice *dev)
  493. {
  494. struct eth_pdata *plat = dev_get_platdata(dev);
  495. struct pcnet_priv *priv = dev_get_priv(dev);
  496. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  497. return pcnet_init_common(priv);
  498. }
  499. static void pcnet_stop(struct udevice *dev)
  500. {
  501. struct pcnet_priv *priv = dev_get_priv(dev);
  502. pcnet_halt_common(priv);
  503. }
  504. static int pcnet_send(struct udevice *dev, void *packet, int length)
  505. {
  506. struct pcnet_priv *priv = dev_get_priv(dev);
  507. int ret;
  508. ret = pcnet_send_common(priv, packet, length);
  509. return ret ? 0 : -ETIMEDOUT;
  510. }
  511. static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
  512. {
  513. struct pcnet_priv *priv = dev_get_priv(dev);
  514. return pcnet_recv_common(priv, packetp);
  515. }
  516. static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
  517. {
  518. struct pcnet_priv *priv = dev_get_priv(dev);
  519. pcnet_free_pkt_common(priv, length);
  520. return 0;
  521. }
  522. static int pcnet_bind(struct udevice *dev)
  523. {
  524. static int card_number;
  525. char name[16];
  526. sprintf(name, "pcnet#%u", card_number++);
  527. return device_set_name(dev, name);
  528. }
  529. static int pcnet_probe(struct udevice *dev)
  530. {
  531. struct eth_pdata *plat = dev_get_platdata(dev);
  532. struct pcnet_priv *lp = dev_get_priv(dev);
  533. u16 command, status;
  534. u32 iobase;
  535. int ret;
  536. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
  537. iobase &= ~0xf;
  538. lp->uc = map_physmem((phys_addr_t)&lp->ucp,
  539. sizeof(lp->ucp), MAP_NOCACHE);
  540. lp->dev = dev;
  541. lp->name = dev->name;
  542. lp->enetaddr = plat->enetaddr;
  543. lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
  544. flush_dcache_range((unsigned long)lp,
  545. (unsigned long)lp + sizeof(*lp));
  546. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  547. dm_pci_write_config16(dev, PCI_COMMAND, command);
  548. dm_pci_read_config16(dev, PCI_COMMAND, &status);
  549. if ((status & command) != command) {
  550. printf("%s: Couldn't enable IO access or Bus Mastering\n",
  551. lp->name);
  552. return -EINVAL;
  553. }
  554. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
  555. ret = pcnet_probe_common(lp);
  556. if (ret)
  557. return ret;
  558. return 0;
  559. }
  560. static const struct eth_ops pcnet_ops = {
  561. .start = pcnet_start,
  562. .send = pcnet_send,
  563. .recv = pcnet_recv,
  564. .stop = pcnet_stop,
  565. .free_pkt = pcnet_free_pkt,
  566. };
  567. U_BOOT_DRIVER(eth_pcnet) = {
  568. .name = "eth_pcnet",
  569. .id = UCLASS_ETH,
  570. .bind = pcnet_bind,
  571. .probe = pcnet_probe,
  572. .ops = &pcnet_ops,
  573. .priv_auto_alloc_size = sizeof(struct pcnet_priv),
  574. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  575. .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
  576. };
  577. U_BOOT_PCI_DEVICE(eth_pcnet, supported);
  578. #endif