mpc8xx_fec.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <hang.h>
  9. #include <malloc.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/cpm_8xx.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. #include <phy.h>
  16. #include <linux/mii.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* define WANT_MII when MII support is required */
  19. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  20. #define WANT_MII
  21. #else
  22. #undef WANT_MII
  23. #endif
  24. #if defined(WANT_MII)
  25. #include <miiphy.h>
  26. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  27. #error "CONFIG_MII has to be defined!"
  28. #endif
  29. #endif
  30. #if defined(CONFIG_RMII) && !defined(WANT_MII)
  31. #error RMII support is unusable without a working PHY.
  32. #endif
  33. #ifdef CONFIG_SYS_DISCOVER_PHY
  34. static int mii_discover_phy(struct eth_device *dev);
  35. #endif
  36. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  37. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  38. u16 value);
  39. static struct ether_fcc_info_s
  40. {
  41. int ether_index;
  42. int fecp_offset;
  43. int phy_addr;
  44. int actual_phy_addr;
  45. int initialized;
  46. }
  47. ether_fcc_info[] = {
  48. #if defined(CONFIG_ETHER_ON_FEC1)
  49. {
  50. 0,
  51. offsetof(immap_t, im_cpm.cp_fec1),
  52. CONFIG_FEC1_PHY,
  53. -1,
  54. 0,
  55. },
  56. #endif
  57. #if defined(CONFIG_ETHER_ON_FEC2)
  58. {
  59. 1,
  60. offsetof(immap_t, im_cpm.cp_fec2),
  61. CONFIG_FEC2_PHY,
  62. -1,
  63. 0,
  64. },
  65. #endif
  66. };
  67. /* Ethernet Transmit and Receive Buffers */
  68. #define DBUF_LENGTH 1520
  69. #define TX_BUF_CNT 2
  70. #define TOUT_LOOP 100
  71. #define PKT_MAXBUF_SIZE 1518
  72. #define PKT_MINBUF_SIZE 64
  73. #define PKT_MAXBLR_SIZE 1520
  74. #ifdef __GNUC__
  75. static char txbuf[DBUF_LENGTH] __aligned(8);
  76. #else
  77. #error txbuf must be aligned.
  78. #endif
  79. static uint rxIdx; /* index of the current RX buffer */
  80. static uint txIdx; /* index of the current TX buffer */
  81. /*
  82. * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  83. * immr->udata_bd address on Dual-Port RAM
  84. * Provide for Double Buffering
  85. */
  86. struct common_buf_desc {
  87. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  88. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  89. };
  90. static struct common_buf_desc __iomem *rtx;
  91. static int fec_send(struct eth_device *dev, void *packet, int length);
  92. static int fec_recv(struct eth_device *dev);
  93. static int fec_init(struct eth_device *dev, bd_t *bd);
  94. static void fec_halt(struct eth_device *dev);
  95. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  96. static void __mii_init(void);
  97. #endif
  98. int fec_initialize(bd_t *bis)
  99. {
  100. struct eth_device *dev;
  101. struct ether_fcc_info_s *efis;
  102. int i;
  103. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
  104. dev = malloc(sizeof(*dev));
  105. if (dev == NULL)
  106. hang();
  107. memset(dev, 0, sizeof(*dev));
  108. /* for FEC1 make sure that the name of the interface is the same
  109. as the old one for compatibility reasons */
  110. if (i == 0)
  111. strcpy(dev->name, "FEC");
  112. else
  113. sprintf(dev->name, "FEC%d",
  114. ether_fcc_info[i].ether_index + 1);
  115. efis = &ether_fcc_info[i];
  116. /*
  117. * reset actual phy addr
  118. */
  119. efis->actual_phy_addr = -1;
  120. dev->priv = efis;
  121. dev->init = fec_init;
  122. dev->halt = fec_halt;
  123. dev->send = fec_send;
  124. dev->recv = fec_recv;
  125. eth_register(dev);
  126. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  127. int retval;
  128. struct mii_dev *mdiodev = mdio_alloc();
  129. if (!mdiodev)
  130. return -ENOMEM;
  131. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  132. mdiodev->read = fec8xx_miiphy_read;
  133. mdiodev->write = fec8xx_miiphy_write;
  134. retval = mdio_register(mdiodev);
  135. if (retval < 0)
  136. return retval;
  137. #endif
  138. }
  139. return 1;
  140. }
  141. static int fec_send(struct eth_device *dev, void *packet, int length)
  142. {
  143. int j, rc;
  144. struct ether_fcc_info_s *efis = dev->priv;
  145. fec_t __iomem *fecp =
  146. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  147. /* section 16.9.23.3
  148. * Wait for ready
  149. */
  150. j = 0;
  151. while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
  152. (j < TOUT_LOOP)) {
  153. udelay(1);
  154. j++;
  155. }
  156. if (j >= TOUT_LOOP)
  157. printf("TX not ready\n");
  158. out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
  159. out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
  160. setbits_be16(&rtx->txbd[txIdx].cbd_sc,
  161. BD_ENET_TX_READY | BD_ENET_TX_LAST);
  162. /* Activate transmit Buffer Descriptor polling */
  163. /* Descriptor polling active */
  164. out_be32(&fecp->fec_x_des_active, 0x01000000);
  165. j = 0;
  166. while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
  167. (j < TOUT_LOOP)) {
  168. udelay(1);
  169. j++;
  170. }
  171. if (j >= TOUT_LOOP)
  172. printf("TX timeout\n");
  173. /* return only status bits */;
  174. rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
  175. txIdx = (txIdx + 1) % TX_BUF_CNT;
  176. return rc;
  177. }
  178. static int fec_recv(struct eth_device *dev)
  179. {
  180. struct ether_fcc_info_s *efis = dev->priv;
  181. fec_t __iomem *fecp =
  182. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  183. int length;
  184. for (;;) {
  185. /* section 16.9.23.2 */
  186. if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
  187. length = -1;
  188. break; /* nothing received - leave for() loop */
  189. }
  190. length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
  191. if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
  192. uchar *rx = net_rx_packets[rxIdx];
  193. length -= 4;
  194. #if defined(CONFIG_CMD_CDP)
  195. if ((rx[0] & 1) != 0 &&
  196. memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
  197. !is_cdp_packet((uchar *)rx))
  198. rx = NULL;
  199. #endif
  200. /*
  201. * Pass the packet up to the protocol layers.
  202. */
  203. if (rx != NULL)
  204. net_process_received_packet(rx, length);
  205. }
  206. /* Give the buffer back to the FEC. */
  207. out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
  208. /* wrap around buffer index when necessary */
  209. if ((rxIdx + 1) >= PKTBUFSRX) {
  210. out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
  211. BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  212. rxIdx = 0;
  213. } else {
  214. out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
  215. rxIdx++;
  216. }
  217. /* Try to fill Buffer Descriptors */
  218. /* Descriptor polling active */
  219. out_be32(&fecp->fec_r_des_active, 0x01000000);
  220. }
  221. return length;
  222. }
  223. /**************************************************************
  224. *
  225. * FEC Ethernet Initialization Routine
  226. *
  227. *************************************************************/
  228. #define FEC_ECNTRL_PINMUX 0x00000004
  229. #define FEC_ECNTRL_ETHER_EN 0x00000002
  230. #define FEC_ECNTRL_RESET 0x00000001
  231. #define FEC_RCNTRL_BC_REJ 0x00000010
  232. #define FEC_RCNTRL_PROM 0x00000008
  233. #define FEC_RCNTRL_MII_MODE 0x00000004
  234. #define FEC_RCNTRL_DRT 0x00000002
  235. #define FEC_RCNTRL_LOOP 0x00000001
  236. #define FEC_TCNTRL_FDEN 0x00000004
  237. #define FEC_TCNTRL_HBC 0x00000002
  238. #define FEC_TCNTRL_GTS 0x00000001
  239. #define FEC_RESET_DELAY 50
  240. #if defined(CONFIG_RMII)
  241. static inline void fec_10Mbps(struct eth_device *dev)
  242. {
  243. struct ether_fcc_info_s *efis = dev->priv;
  244. int fecidx = efis->ether_index;
  245. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  246. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  247. if ((unsigned int)fecidx >= 2)
  248. hang();
  249. setbits_be32(&immr->im_cpm.cp_cptr, mask);
  250. }
  251. static inline void fec_100Mbps(struct eth_device *dev)
  252. {
  253. struct ether_fcc_info_s *efis = dev->priv;
  254. int fecidx = efis->ether_index;
  255. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  256. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  257. if ((unsigned int)fecidx >= 2)
  258. hang();
  259. clrbits_be32(&immr->im_cpm.cp_cptr, mask);
  260. }
  261. #endif
  262. static inline void fec_full_duplex(struct eth_device *dev)
  263. {
  264. struct ether_fcc_info_s *efis = dev->priv;
  265. fec_t __iomem *fecp =
  266. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  267. clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
  268. setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
  269. }
  270. static inline void fec_half_duplex(struct eth_device *dev)
  271. {
  272. struct ether_fcc_info_s *efis = dev->priv;
  273. fec_t __iomem *fecp =
  274. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  275. setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
  276. clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
  277. }
  278. static void fec_pin_init(int fecidx)
  279. {
  280. bd_t *bd = gd->bd;
  281. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  282. /*
  283. * Set MII speed to 2.5 MHz or slightly below.
  284. *
  285. * According to the MPC860T (Rev. D) Fast ethernet controller user
  286. * manual (6.2.14),
  287. * the MII management interface clock must be less than or equal
  288. * to 2.5 MHz.
  289. * This MDC frequency is equal to system clock / (2 * MII_SPEED).
  290. * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
  291. *
  292. * All MII configuration is done via FEC1 registers:
  293. */
  294. out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
  295. ((bd->bi_intfreq + 4999999) / 5000000) << 1);
  296. #if defined(CONFIG_MPC885) && defined(WANT_MII)
  297. /* use MDC for MII */
  298. setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
  299. clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
  300. #endif
  301. if (fecidx == 0) {
  302. #if defined(CONFIG_ETHER_ON_FEC1)
  303. #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
  304. #if !defined(CONFIG_RMII)
  305. setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
  306. setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
  307. clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
  308. setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
  309. clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
  310. setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
  311. clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
  312. setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
  313. setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
  314. clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
  315. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
  316. #else
  317. #if !defined(CONFIG_FEC1_PHY_NORXERR)
  318. setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
  319. clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
  320. #endif
  321. setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
  322. setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
  323. clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
  324. setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
  325. clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
  326. setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
  327. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
  328. #endif /* !CONFIG_RMII */
  329. #else
  330. /*
  331. * Configure all of port D for MII.
  332. */
  333. out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
  334. out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
  335. #if defined(CONFIG_TARGET_MCR3000)
  336. out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
  337. out_be16(&immr->im_ioport.iop_padir, 0x04F0);
  338. out_be16(&immr->im_ioport.iop_paodr, 0x0000);
  339. out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
  340. out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
  341. out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
  342. out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
  343. out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
  344. out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
  345. out_be16(&immr->im_ioport.iop_pcint, 0x0000);
  346. out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
  347. out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
  348. setbits_be32(&immr->im_ioport.utmode, 0x80);
  349. #endif
  350. #endif
  351. #endif /* CONFIG_ETHER_ON_FEC1 */
  352. } else if (fecidx == 1) {
  353. #if defined(CONFIG_ETHER_ON_FEC2)
  354. #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
  355. #if !defined(CONFIG_RMII)
  356. setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
  357. setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
  358. clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
  359. setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
  360. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
  361. #else
  362. #if !defined(CONFIG_FEC2_PHY_NORXERR)
  363. setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
  364. setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
  365. clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
  366. #endif
  367. setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
  368. setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
  369. setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
  370. clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
  371. setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
  372. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
  373. #endif /* CONFIG_RMII */
  374. #endif /* CONFIG_MPC885 */
  375. #endif /* CONFIG_ETHER_ON_FEC2 */
  376. }
  377. }
  378. static int fec_reset(fec_t __iomem *fecp)
  379. {
  380. int i;
  381. /* Whack a reset.
  382. * A delay is required between a reset of the FEC block and
  383. * initialization of other FEC registers because the reset takes
  384. * some time to complete. If you don't delay, subsequent writes
  385. * to FEC registers might get killed by the reset routine which is
  386. * still in progress.
  387. */
  388. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  389. for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
  390. (i < FEC_RESET_DELAY); ++i)
  391. udelay(1);
  392. if (i == FEC_RESET_DELAY)
  393. return -1;
  394. return 0;
  395. }
  396. static int fec_init(struct eth_device *dev, bd_t *bd)
  397. {
  398. struct ether_fcc_info_s *efis = dev->priv;
  399. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  400. fec_t __iomem *fecp =
  401. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  402. int i;
  403. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  404. /* the MII interface is connected to FEC1
  405. * so for the miiphy_xxx function to work we must
  406. * call mii_init since fec_halt messes the thing up
  407. */
  408. if (efis->ether_index != 0)
  409. __mii_init();
  410. #endif
  411. if (fec_reset(fecp) < 0)
  412. printf("FEC_RESET_DELAY timeout\n");
  413. /* We use strictly polling mode only
  414. */
  415. out_be32(&fecp->fec_imask, 0);
  416. /* Clear any pending interrupt
  417. */
  418. out_be32(&fecp->fec_ievent, 0xffc0);
  419. /* No need to set the IVEC register */
  420. /* Set station address
  421. */
  422. #define ea dev->enetaddr
  423. out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
  424. (ea[2] << 8) | ea[3]);
  425. out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
  426. #undef ea
  427. #if defined(CONFIG_CMD_CDP)
  428. /*
  429. * Turn on multicast address hash table
  430. */
  431. out_be32(&fecp->fec_hash_table_high, 0xffffffff);
  432. out_be32(&fecp->fec_hash_table_low, 0xffffffff);
  433. #else
  434. /* Clear multicast address hash table
  435. */
  436. out_be32(&fecp->fec_hash_table_high, 0);
  437. out_be32(&fecp->fec_hash_table_low, 0);
  438. #endif
  439. /* Set maximum receive buffer size.
  440. */
  441. out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
  442. /* Set maximum frame length
  443. */
  444. out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
  445. /*
  446. * Setup Buffers and Buffer Descriptors
  447. */
  448. rxIdx = 0;
  449. txIdx = 0;
  450. if (!rtx)
  451. rtx = (struct common_buf_desc __iomem *)
  452. (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
  453. /*
  454. * Setup Receiver Buffer Descriptors (13.14.24.18)
  455. * Settings:
  456. * Empty, Wrap
  457. */
  458. for (i = 0; i < PKTBUFSRX; i++) {
  459. out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
  460. out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
  461. out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
  462. }
  463. setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
  464. /*
  465. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  466. * Settings:
  467. * Last, Tx CRC
  468. */
  469. for (i = 0; i < TX_BUF_CNT; i++) {
  470. out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
  471. out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
  472. out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
  473. }
  474. setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
  475. /* Set receive and transmit descriptor base
  476. */
  477. out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
  478. out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
  479. /* Enable MII mode
  480. */
  481. /* Half duplex mode */
  482. out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
  483. out_be32(&fecp->fec_x_cntrl, 0);
  484. /* Enable big endian and don't care about SDMA FC.
  485. */
  486. out_be32(&fecp->fec_fun_code, 0x78000000);
  487. /*
  488. * Setup the pin configuration of the FEC
  489. */
  490. fec_pin_init(efis->ether_index);
  491. rxIdx = 0;
  492. txIdx = 0;
  493. /*
  494. * Now enable the transmit and receive processing
  495. */
  496. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  497. if (efis->phy_addr == -1) {
  498. #ifdef CONFIG_SYS_DISCOVER_PHY
  499. /*
  500. * wait for the PHY to wake up after reset
  501. */
  502. efis->actual_phy_addr = mii_discover_phy(dev);
  503. if (efis->actual_phy_addr == -1) {
  504. printf("Unable to discover phy!\n");
  505. return -1;
  506. }
  507. #else
  508. efis->actual_phy_addr = -1;
  509. #endif
  510. } else {
  511. efis->actual_phy_addr = efis->phy_addr;
  512. }
  513. #if defined(CONFIG_MII) && defined(CONFIG_RMII)
  514. /*
  515. * adapt the RMII speed to the speed of the phy
  516. */
  517. if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
  518. fec_100Mbps(dev);
  519. else
  520. fec_10Mbps(dev);
  521. #endif
  522. #if defined(CONFIG_MII)
  523. /*
  524. * adapt to the half/full speed settings
  525. */
  526. if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
  527. fec_full_duplex(dev);
  528. else
  529. fec_half_duplex(dev);
  530. #endif
  531. /* And last, try to fill Rx Buffer Descriptors */
  532. /* Descriptor polling active */
  533. out_be32(&fecp->fec_r_des_active, 0x01000000);
  534. efis->initialized = 1;
  535. return 0;
  536. }
  537. static void fec_halt(struct eth_device *dev)
  538. {
  539. struct ether_fcc_info_s *efis = dev->priv;
  540. fec_t __iomem *fecp =
  541. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  542. int i;
  543. /* avoid halt if initialized; mii gets stuck otherwise */
  544. if (!efis->initialized)
  545. return;
  546. /* Whack a reset.
  547. * A delay is required between a reset of the FEC block and
  548. * initialization of other FEC registers because the reset takes
  549. * some time to complete. If you don't delay, subsequent writes
  550. * to FEC registers might get killed by the reset routine which is
  551. * still in progress.
  552. */
  553. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  554. for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
  555. (i < FEC_RESET_DELAY); ++i)
  556. udelay(1);
  557. if (i == FEC_RESET_DELAY) {
  558. printf("FEC_RESET_DELAY timeout\n");
  559. return;
  560. }
  561. efis->initialized = 0;
  562. }
  563. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  564. /* Make MII read/write commands for the FEC.
  565. */
  566. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  567. (REG & 0x1f) << 18))
  568. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  569. (REG & 0x1f) << 18) | \
  570. (VAL & 0xffff))
  571. /* Interrupt events/masks.
  572. */
  573. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  574. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  575. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  576. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  577. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  578. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  579. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  580. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  581. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  582. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  583. /* send command to phy using mii, wait for result */
  584. static uint
  585. mii_send(uint mii_cmd)
  586. {
  587. uint mii_reply;
  588. fec_t __iomem *ep;
  589. int cnt;
  590. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  591. ep = &immr->im_cpm.cp_fec;
  592. out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
  593. /* wait for mii complete */
  594. cnt = 0;
  595. while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
  596. if (++cnt > 1000) {
  597. printf("mii_send STUCK!\n");
  598. break;
  599. }
  600. }
  601. mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
  602. out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
  603. return mii_reply & 0xffff; /* data read from phy */
  604. }
  605. #endif
  606. #if defined(CONFIG_SYS_DISCOVER_PHY)
  607. static int mii_discover_phy(struct eth_device *dev)
  608. {
  609. #define MAX_PHY_PASSES 11
  610. uint phyno;
  611. int pass;
  612. uint phytype;
  613. int phyaddr;
  614. phyaddr = -1; /* didn't find a PHY yet */
  615. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  616. if (pass > 1) {
  617. /* PHY may need more time to recover from reset.
  618. * The LXT970 needs 50ms typical, no maximum is
  619. * specified, so wait 10ms before try again.
  620. * With 11 passes this gives it 100ms to wake up.
  621. */
  622. udelay(10000); /* wait 10ms */
  623. }
  624. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  625. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
  626. if (phytype != 0xffff) {
  627. phyaddr = phyno;
  628. phytype |= mii_send(mk_mii_read(phyno,
  629. MII_PHYSID1)) << 16;
  630. }
  631. }
  632. }
  633. if (phyaddr < 0)
  634. printf("No PHY device found.\n");
  635. return phyaddr;
  636. }
  637. #endif /* CONFIG_SYS_DISCOVER_PHY */
  638. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
  639. /****************************************************************************
  640. * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
  641. * This function is a subset of eth_init
  642. ****************************************************************************
  643. */
  644. static void __mii_init(void)
  645. {
  646. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  647. fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
  648. if (fec_reset(fecp) < 0)
  649. printf("FEC_RESET_DELAY timeout\n");
  650. /* We use strictly polling mode only
  651. */
  652. out_be32(&fecp->fec_imask, 0);
  653. /* Clear any pending interrupt
  654. */
  655. out_be32(&fecp->fec_ievent, 0xffc0);
  656. /* Now enable the transmit and receive processing
  657. */
  658. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  659. }
  660. void mii_init(void)
  661. {
  662. int i;
  663. __mii_init();
  664. /* Setup the pin configuration of the FEC(s)
  665. */
  666. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
  667. fec_pin_init(ether_fcc_info[i].ether_index);
  668. }
  669. /*****************************************************************************
  670. * Read and write a MII PHY register, routines used by MII Utilities
  671. *
  672. * FIXME: These routines are expected to return 0 on success, but mii_send
  673. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  674. * no PHY connected...
  675. * For now always return 0.
  676. * FIXME: These routines only work after calling eth_init() at least once!
  677. * Otherwise they hang in mii_send() !!! Sorry!
  678. *****************************************************************************/
  679. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  680. {
  681. unsigned short value = 0;
  682. short rdreg; /* register working value */
  683. rdreg = mii_send(mk_mii_read(addr, reg));
  684. value = rdreg;
  685. return value;
  686. }
  687. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  688. u16 value)
  689. {
  690. (void)mii_send(mk_mii_write(addr, reg, value));
  691. return 0;
  692. }
  693. #endif