gmac_rockchip.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  4. *
  5. * Rockchip GMAC ethernet IP driver for U-Boot
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <clk.h>
  10. #include <log.h>
  11. #include <net.h>
  12. #include <phy.h>
  13. #include <syscon.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-rockchip/periph.h>
  16. #include <asm/arch-rockchip/clock.h>
  17. #include <asm/arch-rockchip/hardware.h>
  18. #include <asm/arch-rockchip/grf_px30.h>
  19. #include <asm/arch-rockchip/grf_rk322x.h>
  20. #include <asm/arch-rockchip/grf_rk3288.h>
  21. #include <asm/arch-rk3308/grf_rk3308.h>
  22. #include <asm/arch-rockchip/grf_rk3328.h>
  23. #include <asm/arch-rockchip/grf_rk3368.h>
  24. #include <asm/arch-rockchip/grf_rk3399.h>
  25. #include <asm/arch-rockchip/grf_rv1108.h>
  26. #include <dm/pinctrl.h>
  27. #include <dt-bindings/clock/rk3288-cru.h>
  28. #include <linux/bitops.h>
  29. #include "designware.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define DELAY_ENABLE(soc, tx, rx) \
  32. (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
  33. ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
  34. /*
  35. * Platform data for the gmac
  36. *
  37. * dw_eth_pdata: Required platform data for designware driver (must be first)
  38. */
  39. struct gmac_rockchip_platdata {
  40. struct dw_eth_pdata dw_eth_pdata;
  41. bool clock_input;
  42. int tx_delay;
  43. int rx_delay;
  44. };
  45. struct rk_gmac_ops {
  46. int (*fix_mac_speed)(struct dw_eth_dev *priv);
  47. void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
  48. void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
  49. };
  50. static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
  51. {
  52. struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
  53. const char *string;
  54. string = dev_read_string(dev, "clock_in_out");
  55. if (!strcmp(string, "input"))
  56. pdata->clock_input = true;
  57. else
  58. pdata->clock_input = false;
  59. /* Check the new naming-style first... */
  60. pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
  61. pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
  62. /* ... and fall back to the old naming style or default, if necessary */
  63. if (pdata->tx_delay == -ENOENT)
  64. pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
  65. if (pdata->rx_delay == -ENOENT)
  66. pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
  67. return designware_eth_ofdata_to_platdata(dev);
  68. }
  69. static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  70. {
  71. struct px30_grf *grf;
  72. struct clk clk_speed;
  73. int speed, ret;
  74. enum {
  75. PX30_GMAC_SPEED_SHIFT = 0x2,
  76. PX30_GMAC_SPEED_MASK = BIT(2),
  77. PX30_GMAC_SPEED_10M = 0,
  78. PX30_GMAC_SPEED_100M = BIT(2),
  79. };
  80. ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  81. &clk_speed);
  82. if (ret)
  83. return ret;
  84. switch (priv->phydev->speed) {
  85. case 10:
  86. speed = PX30_GMAC_SPEED_10M;
  87. ret = clk_set_rate(&clk_speed, 2500000);
  88. if (ret)
  89. return ret;
  90. break;
  91. case 100:
  92. speed = PX30_GMAC_SPEED_100M;
  93. ret = clk_set_rate(&clk_speed, 25000000);
  94. if (ret)
  95. return ret;
  96. break;
  97. default:
  98. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  99. return -EINVAL;
  100. }
  101. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  102. rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
  103. return 0;
  104. }
  105. static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  106. {
  107. struct rk322x_grf *grf;
  108. int clk;
  109. enum {
  110. RK3228_GMAC_CLK_SEL_SHIFT = 8,
  111. RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
  112. RK3228_GMAC_CLK_SEL_125M = 0 << 8,
  113. RK3228_GMAC_CLK_SEL_25M = 3 << 8,
  114. RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
  115. };
  116. switch (priv->phydev->speed) {
  117. case 10:
  118. clk = RK3228_GMAC_CLK_SEL_2_5M;
  119. break;
  120. case 100:
  121. clk = RK3228_GMAC_CLK_SEL_25M;
  122. break;
  123. case 1000:
  124. clk = RK3228_GMAC_CLK_SEL_125M;
  125. break;
  126. default:
  127. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  128. return -EINVAL;
  129. }
  130. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  131. rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
  132. return 0;
  133. }
  134. static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  135. {
  136. struct rk3288_grf *grf;
  137. int clk;
  138. switch (priv->phydev->speed) {
  139. case 10:
  140. clk = RK3288_GMAC_CLK_SEL_2_5M;
  141. break;
  142. case 100:
  143. clk = RK3288_GMAC_CLK_SEL_25M;
  144. break;
  145. case 1000:
  146. clk = RK3288_GMAC_CLK_SEL_125M;
  147. break;
  148. default:
  149. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  150. return -EINVAL;
  151. }
  152. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  153. rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
  154. return 0;
  155. }
  156. static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  157. {
  158. struct rk3308_grf *grf;
  159. struct clk clk_speed;
  160. int speed, ret;
  161. enum {
  162. RK3308_GMAC_SPEED_SHIFT = 0x0,
  163. RK3308_GMAC_SPEED_MASK = BIT(0),
  164. RK3308_GMAC_SPEED_10M = 0,
  165. RK3308_GMAC_SPEED_100M = BIT(0),
  166. };
  167. ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  168. &clk_speed);
  169. if (ret)
  170. return ret;
  171. switch (priv->phydev->speed) {
  172. case 10:
  173. speed = RK3308_GMAC_SPEED_10M;
  174. ret = clk_set_rate(&clk_speed, 2500000);
  175. if (ret)
  176. return ret;
  177. break;
  178. case 100:
  179. speed = RK3308_GMAC_SPEED_100M;
  180. ret = clk_set_rate(&clk_speed, 25000000);
  181. if (ret)
  182. return ret;
  183. break;
  184. default:
  185. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  186. return -EINVAL;
  187. }
  188. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  189. rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
  190. return 0;
  191. }
  192. static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  193. {
  194. struct rk3328_grf_regs *grf;
  195. int clk;
  196. enum {
  197. RK3328_GMAC_CLK_SEL_SHIFT = 11,
  198. RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
  199. RK3328_GMAC_CLK_SEL_125M = 0 << 11,
  200. RK3328_GMAC_CLK_SEL_25M = 3 << 11,
  201. RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
  202. };
  203. switch (priv->phydev->speed) {
  204. case 10:
  205. clk = RK3328_GMAC_CLK_SEL_2_5M;
  206. break;
  207. case 100:
  208. clk = RK3328_GMAC_CLK_SEL_25M;
  209. break;
  210. case 1000:
  211. clk = RK3328_GMAC_CLK_SEL_125M;
  212. break;
  213. default:
  214. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  215. return -EINVAL;
  216. }
  217. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  218. rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
  219. return 0;
  220. }
  221. static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  222. {
  223. struct rk3368_grf *grf;
  224. int clk;
  225. enum {
  226. RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
  227. RK3368_GMAC_CLK_SEL_25M = 3 << 4,
  228. RK3368_GMAC_CLK_SEL_125M = 0 << 4,
  229. RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
  230. };
  231. switch (priv->phydev->speed) {
  232. case 10:
  233. clk = RK3368_GMAC_CLK_SEL_2_5M;
  234. break;
  235. case 100:
  236. clk = RK3368_GMAC_CLK_SEL_25M;
  237. break;
  238. case 1000:
  239. clk = RK3368_GMAC_CLK_SEL_125M;
  240. break;
  241. default:
  242. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  243. return -EINVAL;
  244. }
  245. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  246. rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
  247. return 0;
  248. }
  249. static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  250. {
  251. struct rk3399_grf_regs *grf;
  252. int clk;
  253. switch (priv->phydev->speed) {
  254. case 10:
  255. clk = RK3399_GMAC_CLK_SEL_2_5M;
  256. break;
  257. case 100:
  258. clk = RK3399_GMAC_CLK_SEL_25M;
  259. break;
  260. case 1000:
  261. clk = RK3399_GMAC_CLK_SEL_125M;
  262. break;
  263. default:
  264. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  265. return -EINVAL;
  266. }
  267. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  268. rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
  269. return 0;
  270. }
  271. static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
  272. {
  273. struct rv1108_grf *grf;
  274. int clk, speed;
  275. enum {
  276. RV1108_GMAC_SPEED_MASK = BIT(2),
  277. RV1108_GMAC_SPEED_10M = 0 << 2,
  278. RV1108_GMAC_SPEED_100M = 1 << 2,
  279. RV1108_GMAC_CLK_SEL_MASK = BIT(7),
  280. RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
  281. RV1108_GMAC_CLK_SEL_25M = 1 << 7,
  282. };
  283. switch (priv->phydev->speed) {
  284. case 10:
  285. clk = RV1108_GMAC_CLK_SEL_2_5M;
  286. speed = RV1108_GMAC_SPEED_10M;
  287. break;
  288. case 100:
  289. clk = RV1108_GMAC_CLK_SEL_25M;
  290. speed = RV1108_GMAC_SPEED_100M;
  291. break;
  292. default:
  293. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  294. return -EINVAL;
  295. }
  296. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  297. rk_clrsetreg(&grf->gmac_con0,
  298. RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
  299. clk | speed);
  300. return 0;
  301. }
  302. static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
  303. {
  304. struct px30_grf *grf;
  305. enum {
  306. PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
  307. PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
  308. PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
  309. };
  310. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  311. rk_clrsetreg(&grf->mac_con1,
  312. PX30_GMAC_PHY_INTF_SEL_MASK,
  313. PX30_GMAC_PHY_INTF_SEL_RMII);
  314. }
  315. static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
  316. {
  317. struct rk322x_grf *grf;
  318. enum {
  319. RK3228_RMII_MODE_SHIFT = 10,
  320. RK3228_RMII_MODE_MASK = BIT(10),
  321. RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
  322. RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  323. RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
  324. RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
  325. RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  326. RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
  327. RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
  328. RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  329. RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
  330. };
  331. enum {
  332. RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
  333. RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
  334. RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
  335. RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  336. };
  337. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  338. rk_clrsetreg(&grf->mac_con[1],
  339. RK3228_RMII_MODE_MASK |
  340. RK3228_GMAC_PHY_INTF_SEL_MASK |
  341. RK3228_RXCLK_DLY_ENA_GMAC_MASK |
  342. RK3228_TXCLK_DLY_ENA_GMAC_MASK,
  343. RK3228_GMAC_PHY_INTF_SEL_RGMII |
  344. DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
  345. rk_clrsetreg(&grf->mac_con[0],
  346. RK3228_CLK_RX_DL_CFG_GMAC_MASK |
  347. RK3228_CLK_TX_DL_CFG_GMAC_MASK,
  348. pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
  349. pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
  350. }
  351. static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
  352. {
  353. struct rk3288_grf *grf;
  354. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  355. rk_clrsetreg(&grf->soc_con1,
  356. RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
  357. RK3288_GMAC_PHY_INTF_SEL_RGMII);
  358. rk_clrsetreg(&grf->soc_con3,
  359. RK3288_RXCLK_DLY_ENA_GMAC_MASK |
  360. RK3288_TXCLK_DLY_ENA_GMAC_MASK |
  361. RK3288_CLK_RX_DL_CFG_GMAC_MASK |
  362. RK3288_CLK_TX_DL_CFG_GMAC_MASK,
  363. DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
  364. pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
  365. pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
  366. }
  367. static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
  368. {
  369. struct rk3308_grf *grf;
  370. enum {
  371. RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
  372. RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
  373. RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
  374. };
  375. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  376. rk_clrsetreg(&grf->mac_con0,
  377. RK3308_GMAC_PHY_INTF_SEL_MASK,
  378. RK3308_GMAC_PHY_INTF_SEL_RMII);
  379. }
  380. static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
  381. {
  382. struct rk3328_grf_regs *grf;
  383. enum {
  384. RK3328_RMII_MODE_SHIFT = 9,
  385. RK3328_RMII_MODE_MASK = BIT(9),
  386. RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
  387. RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  388. RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
  389. RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
  390. RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  391. RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
  392. RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
  393. RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  394. RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
  395. };
  396. enum {
  397. RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
  398. RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
  399. RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
  400. RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  401. };
  402. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  403. rk_clrsetreg(&grf->mac_con[1],
  404. RK3328_RMII_MODE_MASK |
  405. RK3328_GMAC_PHY_INTF_SEL_MASK |
  406. RK3328_RXCLK_DLY_ENA_GMAC_MASK |
  407. RK3328_TXCLK_DLY_ENA_GMAC_MASK,
  408. RK3328_GMAC_PHY_INTF_SEL_RGMII |
  409. DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
  410. rk_clrsetreg(&grf->mac_con[0],
  411. RK3328_CLK_RX_DL_CFG_GMAC_MASK |
  412. RK3328_CLK_TX_DL_CFG_GMAC_MASK,
  413. pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
  414. pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
  415. }
  416. static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
  417. {
  418. struct rk3368_grf *grf;
  419. enum {
  420. RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
  421. RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
  422. RK3368_RMII_MODE_MASK = BIT(6),
  423. RK3368_RMII_MODE = BIT(6),
  424. };
  425. enum {
  426. RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
  427. RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  428. RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
  429. RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
  430. RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  431. RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
  432. RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
  433. RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
  434. RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
  435. RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  436. };
  437. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  438. rk_clrsetreg(&grf->soc_con15,
  439. RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
  440. RK3368_GMAC_PHY_INTF_SEL_RGMII);
  441. rk_clrsetreg(&grf->soc_con16,
  442. RK3368_RXCLK_DLY_ENA_GMAC_MASK |
  443. RK3368_TXCLK_DLY_ENA_GMAC_MASK |
  444. RK3368_CLK_RX_DL_CFG_GMAC_MASK |
  445. RK3368_CLK_TX_DL_CFG_GMAC_MASK,
  446. DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
  447. pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
  448. pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
  449. }
  450. static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
  451. {
  452. struct rk3399_grf_regs *grf;
  453. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  454. rk_clrsetreg(&grf->soc_con5,
  455. RK3399_GMAC_PHY_INTF_SEL_MASK,
  456. RK3399_GMAC_PHY_INTF_SEL_RGMII);
  457. rk_clrsetreg(&grf->soc_con6,
  458. RK3399_RXCLK_DLY_ENA_GMAC_MASK |
  459. RK3399_TXCLK_DLY_ENA_GMAC_MASK |
  460. RK3399_CLK_RX_DL_CFG_GMAC_MASK |
  461. RK3399_CLK_TX_DL_CFG_GMAC_MASK,
  462. DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
  463. pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
  464. pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
  465. }
  466. static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
  467. {
  468. struct rv1108_grf *grf;
  469. enum {
  470. RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  471. RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
  472. };
  473. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  474. rk_clrsetreg(&grf->gmac_con0,
  475. RV1108_GMAC_PHY_INTF_SEL_MASK,
  476. RV1108_GMAC_PHY_INTF_SEL_RMII);
  477. }
  478. static int gmac_rockchip_probe(struct udevice *dev)
  479. {
  480. struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
  481. struct rk_gmac_ops *ops =
  482. (struct rk_gmac_ops *)dev_get_driver_data(dev);
  483. struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
  484. struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
  485. struct clk clk;
  486. ulong rate;
  487. int ret;
  488. ret = clk_set_defaults(dev, 0);
  489. if (ret)
  490. debug("%s clk_set_defaults failed %d\n", __func__, ret);
  491. ret = clk_get_by_index(dev, 0, &clk);
  492. if (ret)
  493. return ret;
  494. switch (eth_pdata->phy_interface) {
  495. case PHY_INTERFACE_MODE_RGMII:
  496. /* Set to RGMII mode */
  497. if (ops->set_to_rgmii)
  498. ops->set_to_rgmii(pdata);
  499. else
  500. return -EPERM;
  501. /*
  502. * If the gmac clock is from internal pll, need to set and
  503. * check the return value for gmac clock at RGMII mode. If
  504. * the gmac clock is from external source, the clock rate
  505. * is not set, because of it is bypassed.
  506. */
  507. if (!pdata->clock_input) {
  508. rate = clk_set_rate(&clk, 125000000);
  509. if (rate != 125000000)
  510. return -EINVAL;
  511. }
  512. break;
  513. case PHY_INTERFACE_MODE_RGMII_ID:
  514. /* Set to RGMII mode */
  515. if (ops->set_to_rgmii) {
  516. pdata->tx_delay = 0;
  517. pdata->rx_delay = 0;
  518. ops->set_to_rgmii(pdata);
  519. } else
  520. return -EPERM;
  521. if (!pdata->clock_input) {
  522. rate = clk_set_rate(&clk, 125000000);
  523. if (rate != 125000000)
  524. return -EINVAL;
  525. }
  526. break;
  527. case PHY_INTERFACE_MODE_RMII:
  528. /* Set to RMII mode */
  529. if (ops->set_to_rmii)
  530. ops->set_to_rmii(pdata);
  531. else
  532. return -EPERM;
  533. if (!pdata->clock_input) {
  534. rate = clk_set_rate(&clk, 50000000);
  535. if (rate != 50000000)
  536. return -EINVAL;
  537. }
  538. break;
  539. case PHY_INTERFACE_MODE_RGMII_RXID:
  540. /* Set to RGMII_RXID mode */
  541. if (ops->set_to_rgmii) {
  542. pdata->tx_delay = 0;
  543. ops->set_to_rgmii(pdata);
  544. } else
  545. return -EPERM;
  546. if (!pdata->clock_input) {
  547. rate = clk_set_rate(&clk, 125000000);
  548. if (rate != 125000000)
  549. return -EINVAL;
  550. }
  551. break;
  552. case PHY_INTERFACE_MODE_RGMII_TXID:
  553. /* Set to RGMII_TXID mode */
  554. if (ops->set_to_rgmii) {
  555. pdata->rx_delay = 0;
  556. ops->set_to_rgmii(pdata);
  557. } else
  558. return -EPERM;
  559. if (!pdata->clock_input) {
  560. rate = clk_set_rate(&clk, 125000000);
  561. if (rate != 125000000)
  562. return -EINVAL;
  563. }
  564. break;
  565. default:
  566. debug("NO interface defined!\n");
  567. return -ENXIO;
  568. }
  569. return designware_eth_probe(dev);
  570. }
  571. static int gmac_rockchip_eth_start(struct udevice *dev)
  572. {
  573. struct eth_pdata *pdata = dev_get_platdata(dev);
  574. struct dw_eth_dev *priv = dev_get_priv(dev);
  575. struct rk_gmac_ops *ops =
  576. (struct rk_gmac_ops *)dev_get_driver_data(dev);
  577. int ret;
  578. ret = designware_eth_init(priv, pdata->enetaddr);
  579. if (ret)
  580. return ret;
  581. ret = ops->fix_mac_speed(priv);
  582. if (ret)
  583. return ret;
  584. ret = designware_eth_enable(priv);
  585. if (ret)
  586. return ret;
  587. return 0;
  588. }
  589. const struct eth_ops gmac_rockchip_eth_ops = {
  590. .start = gmac_rockchip_eth_start,
  591. .send = designware_eth_send,
  592. .recv = designware_eth_recv,
  593. .free_pkt = designware_eth_free_pkt,
  594. .stop = designware_eth_stop,
  595. .write_hwaddr = designware_eth_write_hwaddr,
  596. };
  597. const struct rk_gmac_ops px30_gmac_ops = {
  598. .fix_mac_speed = px30_gmac_fix_mac_speed,
  599. .set_to_rmii = px30_gmac_set_to_rmii,
  600. };
  601. const struct rk_gmac_ops rk3228_gmac_ops = {
  602. .fix_mac_speed = rk3228_gmac_fix_mac_speed,
  603. .set_to_rgmii = rk3228_gmac_set_to_rgmii,
  604. };
  605. const struct rk_gmac_ops rk3288_gmac_ops = {
  606. .fix_mac_speed = rk3288_gmac_fix_mac_speed,
  607. .set_to_rgmii = rk3288_gmac_set_to_rgmii,
  608. };
  609. const struct rk_gmac_ops rk3308_gmac_ops = {
  610. .fix_mac_speed = rk3308_gmac_fix_mac_speed,
  611. .set_to_rmii = rk3308_gmac_set_to_rmii,
  612. };
  613. const struct rk_gmac_ops rk3328_gmac_ops = {
  614. .fix_mac_speed = rk3328_gmac_fix_mac_speed,
  615. .set_to_rgmii = rk3328_gmac_set_to_rgmii,
  616. };
  617. const struct rk_gmac_ops rk3368_gmac_ops = {
  618. .fix_mac_speed = rk3368_gmac_fix_mac_speed,
  619. .set_to_rgmii = rk3368_gmac_set_to_rgmii,
  620. };
  621. const struct rk_gmac_ops rk3399_gmac_ops = {
  622. .fix_mac_speed = rk3399_gmac_fix_mac_speed,
  623. .set_to_rgmii = rk3399_gmac_set_to_rgmii,
  624. };
  625. const struct rk_gmac_ops rv1108_gmac_ops = {
  626. .fix_mac_speed = rv1108_set_rmii_speed,
  627. .set_to_rmii = rv1108_gmac_set_to_rmii,
  628. };
  629. static const struct udevice_id rockchip_gmac_ids[] = {
  630. { .compatible = "rockchip,px30-gmac",
  631. .data = (ulong)&px30_gmac_ops },
  632. { .compatible = "rockchip,rk3228-gmac",
  633. .data = (ulong)&rk3228_gmac_ops },
  634. { .compatible = "rockchip,rk3288-gmac",
  635. .data = (ulong)&rk3288_gmac_ops },
  636. { .compatible = "rockchip,rk3308-mac",
  637. .data = (ulong)&rk3308_gmac_ops },
  638. { .compatible = "rockchip,rk3328-gmac",
  639. .data = (ulong)&rk3328_gmac_ops },
  640. { .compatible = "rockchip,rk3368-gmac",
  641. .data = (ulong)&rk3368_gmac_ops },
  642. { .compatible = "rockchip,rk3399-gmac",
  643. .data = (ulong)&rk3399_gmac_ops },
  644. { .compatible = "rockchip,rv1108-gmac",
  645. .data = (ulong)&rv1108_gmac_ops },
  646. { }
  647. };
  648. U_BOOT_DRIVER(eth_gmac_rockchip) = {
  649. .name = "gmac_rockchip",
  650. .id = UCLASS_ETH,
  651. .of_match = rockchip_gmac_ids,
  652. .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
  653. .probe = gmac_rockchip_probe,
  654. .ops = &gmac_rockchip_eth_ops,
  655. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  656. .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
  657. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  658. };