dc2114x.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <env.h>
  4. #include <malloc.h>
  5. #include <net.h>
  6. #include <netdev.h>
  7. #include <pci.h>
  8. #include <linux/bitops.h>
  9. #include <linux/delay.h>
  10. #define SROM_DLEVEL 0
  11. #undef UPDATE_SROM
  12. /* PCI Registers. */
  13. #define PCI_CFDA_PSM 0x43
  14. #define CFRV_RN 0x000000f0 /* Revision Number */
  15. #define WAKEUP 0x00 /* Power Saving Wakeup */
  16. #define SLEEP 0x80 /* Power Saving Sleep Mode */
  17. #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
  18. /* Ethernet chip registers. */
  19. #define DE4X5_BMR 0x000 /* Bus Mode Register */
  20. #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
  21. #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
  22. #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
  23. #define DE4X5_STS 0x028 /* Status Register */
  24. #define DE4X5_OMR 0x030 /* Operation Mode Register */
  25. #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
  26. #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
  27. /* Register bits. */
  28. #define BMR_SWR 0x00000001 /* Software Reset */
  29. #define STS_TS 0x00700000 /* Transmit Process State */
  30. #define STS_RS 0x000e0000 /* Receive Process State */
  31. #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
  32. #define OMR_SR 0x00000002 /* Start/Stop Receive */
  33. #define OMR_PS 0x00040000 /* Port Select */
  34. #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
  35. #define OMR_PM 0x00000080 /* Pass All Multicast */
  36. /* Descriptor bits. */
  37. #define R_OWN 0x80000000 /* Own Bit */
  38. #define RD_RER 0x02000000 /* Receive End Of Ring */
  39. #define RD_LS 0x00000100 /* Last Descriptor */
  40. #define RD_ES 0x00008000 /* Error Summary */
  41. #define TD_TER 0x02000000 /* Transmit End Of Ring */
  42. #define T_OWN 0x80000000 /* Own Bit */
  43. #define TD_LS 0x40000000 /* Last Segment */
  44. #define TD_FS 0x20000000 /* First Segment */
  45. #define TD_ES 0x00008000 /* Error Summary */
  46. #define TD_SET 0x08000000 /* Setup Packet */
  47. /* The EEPROM commands include the alway-set leading bit. */
  48. #define SROM_WRITE_CMD 5
  49. #define SROM_READ_CMD 6
  50. #define SROM_ERASE_CMD 7
  51. #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
  52. #define SROM_RD 0x00004000 /* Read from Boot ROM */
  53. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  54. #define EE_WRITE_0 0x4801
  55. #define EE_WRITE_1 0x4805
  56. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  57. #define SROM_SR 0x00000800 /* Select Serial ROM when set */
  58. #define DT_IN 0x00000004 /* Serial Data In */
  59. #define DT_CLK 0x00000002 /* Serial ROM Clock */
  60. #define DT_CS 0x00000001 /* Serial ROM Chip Select */
  61. #define POLL_DEMAND 1
  62. #if defined(CONFIG_E500)
  63. #define phys_to_bus(a) (a)
  64. #else
  65. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  66. #endif
  67. #define NUM_RX_DESC PKTBUFSRX
  68. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  69. #define RX_BUFF_SZ PKTSIZE_ALIGN
  70. #define TOUT_LOOP 1000000
  71. #define SETUP_FRAME_LEN 192
  72. struct de4x5_desc {
  73. volatile s32 status;
  74. u32 des1;
  75. u32 buf;
  76. u32 next;
  77. };
  78. /* RX and TX descriptor ring */
  79. static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
  80. static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
  81. static int rx_new; /* RX descriptor ring pointer */
  82. static int tx_new; /* TX descriptor ring pointer */
  83. static char rx_ring_size;
  84. static char tx_ring_size;
  85. static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
  86. {
  87. return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
  88. }
  89. static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
  90. {
  91. *(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
  92. }
  93. static void reset_de4x5(struct eth_device *dev)
  94. {
  95. u32 i;
  96. i = dc2114x_inl(dev, DE4X5_BMR);
  97. mdelay(1);
  98. dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
  99. mdelay(1);
  100. dc2114x_outl(dev, i, DE4X5_BMR);
  101. mdelay(1);
  102. for (i = 0; i < 5; i++) {
  103. dc2114x_inl(dev, DE4X5_BMR);
  104. mdelay(10);
  105. }
  106. mdelay(1);
  107. }
  108. static void start_de4x5(struct eth_device *dev)
  109. {
  110. u32 omr;
  111. omr = dc2114x_inl(dev, DE4X5_OMR);
  112. omr |= OMR_ST | OMR_SR;
  113. dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */
  114. }
  115. static void stop_de4x5(struct eth_device *dev)
  116. {
  117. u32 omr;
  118. omr = dc2114x_inl(dev, DE4X5_OMR);
  119. omr &= ~(OMR_ST | OMR_SR);
  120. dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
  121. }
  122. /* SROM Read and write routines. */
  123. static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
  124. {
  125. dc2114x_outl(dev, command, addr);
  126. udelay(1);
  127. }
  128. static int getfrom_srom(struct eth_device *dev, u_long addr)
  129. {
  130. u32 tmp = dc2114x_inl(dev, addr);
  131. udelay(1);
  132. return tmp;
  133. }
  134. /* Note: this routine returns extra data bits for size detection. */
  135. static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
  136. int addr_len)
  137. {
  138. int read_cmd = location | (SROM_READ_CMD << addr_len);
  139. unsigned int retval = 0;
  140. int i;
  141. sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
  142. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  143. debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
  144. /* Shift the read command bits out. */
  145. for (i = 4 + addr_len; i >= 0; i--) {
  146. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  147. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
  148. ioaddr);
  149. udelay(10);
  150. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
  151. ioaddr);
  152. udelay(10);
  153. debug_cond(SROM_DLEVEL >= 2, "%X",
  154. getfrom_srom(dev, ioaddr) & 15);
  155. retval = (retval << 1) |
  156. !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
  157. }
  158. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  159. debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15);
  160. for (i = 16; i > 0; i--) {
  161. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  162. udelay(10);
  163. debug_cond(SROM_DLEVEL >= 2, "%X",
  164. getfrom_srom(dev, ioaddr) & 15);
  165. retval = (retval << 1) |
  166. !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
  167. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  168. udelay(10);
  169. }
  170. /* Terminate the EEPROM access. */
  171. sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
  172. debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
  173. location, retval);
  174. return retval;
  175. }
  176. /*
  177. * This executes a generic EEPROM command, typically a write or write
  178. * enable. It returns the data output from the EEPROM, and thus may
  179. * also be used for reads.
  180. */
  181. static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
  182. int cmd_len)
  183. {
  184. unsigned int retval = 0;
  185. debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
  186. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  187. /* Shift the command bits out. */
  188. do {
  189. short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
  190. sendto_srom(dev, dataval, ioaddr);
  191. udelay(10);
  192. debug_cond(SROM_DLEVEL >= 2, "%X",
  193. getfrom_srom(dev, ioaddr) & 15);
  194. sendto_srom(dev, dataval | DT_CLK, ioaddr);
  195. udelay(10);
  196. retval = (retval << 1) |
  197. !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
  198. } while (--cmd_len >= 0);
  199. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  200. /* Terminate the EEPROM access. */
  201. sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
  202. debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
  203. return retval;
  204. }
  205. static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
  206. {
  207. int ee_addr_size;
  208. ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
  209. return do_eeprom_cmd(dev, ioaddr, 0xffff |
  210. (((SROM_READ_CMD << ee_addr_size) | index) << 16),
  211. 3 + ee_addr_size + 16);
  212. }
  213. #ifdef UPDATE_SROM
  214. static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
  215. int new_value)
  216. {
  217. unsigned short newval;
  218. int ee_addr_size;
  219. int i;
  220. ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
  221. udelay(10 * 1000); /* test-only */
  222. debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size);
  223. debug_cond(SROM_DLEVEL >= 1,
  224. "Writing new entry 0x%4.4x to offset %d.\n",
  225. new_value, index);
  226. /* Enable programming modes. */
  227. do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
  228. 3 + ee_addr_size);
  229. /* Do the actual write. */
  230. do_eeprom_cmd(dev, ioaddr, new_value |
  231. (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
  232. 3 + ee_addr_size + 16);
  233. /* Poll for write finished. */
  234. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  235. for (i = 0; i < 10000; i++) { /* Typical 2000 ticks */
  236. if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
  237. break;
  238. }
  239. debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i);
  240. /* Disable programming. */
  241. do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
  242. 3 + ee_addr_size);
  243. /* And read the result. */
  244. newval = do_eeprom_cmd(dev, ioaddr,
  245. (((SROM_READ_CMD << ee_addr_size) | index) << 16)
  246. | 0xffff, 3 + ee_addr_size + 16);
  247. debug_cond(SROM_DLEVEL >= 1, " New value at offset %d is %4.4x.\n",
  248. index, newval);
  249. return 1;
  250. }
  251. static void update_srom(struct eth_device *dev, bd_t *bis)
  252. {
  253. static unsigned short eeprom[0x40] = {
  254. 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
  255. 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
  256. 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
  257. 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
  258. 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
  259. 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
  260. 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
  261. 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
  262. 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
  263. 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
  264. 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
  265. 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
  266. 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
  267. 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
  268. 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
  269. 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
  270. };
  271. uchar enetaddr[6];
  272. int i;
  273. /* Ethernet Addr... */
  274. if (!eth_env_get_enetaddr("ethaddr", enetaddr))
  275. return;
  276. eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
  277. eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
  278. eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
  279. for (i = 0; i < 0x40; i++)
  280. write_srom(dev, DE4X5_APROM, i, eeprom[i]);
  281. }
  282. #endif /* UPDATE_SROM */
  283. static void send_setup_frame(struct eth_device *dev, bd_t *bis)
  284. {
  285. char setup_frame[SETUP_FRAME_LEN];
  286. char *pa = &setup_frame[0];
  287. int i;
  288. memset(pa, 0xff, SETUP_FRAME_LEN);
  289. for (i = 0; i < ETH_ALEN; i++) {
  290. *(pa + (i & 1)) = dev->enetaddr[i];
  291. if (i & 0x01)
  292. pa += 4;
  293. }
  294. for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  295. if (i < TOUT_LOOP)
  296. continue;
  297. printf("%s: tx error buffer not ready\n", dev->name);
  298. return;
  299. }
  300. tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
  301. tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
  302. tx_ring[tx_new].status = cpu_to_le32(T_OWN);
  303. dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
  304. for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  305. if (i < TOUT_LOOP)
  306. continue;
  307. printf("%s: tx buffer not ready\n", dev->name);
  308. return;
  309. }
  310. if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
  311. printf("TX error status2 = 0x%08X\n",
  312. le32_to_cpu(tx_ring[tx_new].status));
  313. }
  314. tx_new = (tx_new + 1) % NUM_TX_DESC;
  315. }
  316. static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
  317. {
  318. int status = -1;
  319. int i;
  320. if (length <= 0) {
  321. printf("%s: bad packet size: %d\n", dev->name, length);
  322. goto done;
  323. }
  324. for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  325. if (i < TOUT_LOOP)
  326. continue;
  327. printf("%s: tx error buffer not ready\n", dev->name);
  328. goto done;
  329. }
  330. tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
  331. tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
  332. tx_ring[tx_new].status = cpu_to_le32(T_OWN);
  333. dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
  334. for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  335. if (i < TOUT_LOOP)
  336. continue;
  337. printf(".%s: tx buffer not ready\n", dev->name);
  338. goto done;
  339. }
  340. if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
  341. tx_ring[tx_new].status = 0x0;
  342. goto done;
  343. }
  344. status = length;
  345. done:
  346. tx_new = (tx_new + 1) % NUM_TX_DESC;
  347. return status;
  348. }
  349. static int dc21x4x_recv(struct eth_device *dev)
  350. {
  351. int length = 0;
  352. u32 status;
  353. while (true) {
  354. status = le32_to_cpu(rx_ring[rx_new].status);
  355. if (status & R_OWN)
  356. break;
  357. if (status & RD_LS) {
  358. /* Valid frame status. */
  359. if (status & RD_ES) {
  360. /* There was an error. */
  361. printf("RX error status = 0x%08X\n", status);
  362. } else {
  363. /* A valid frame received. */
  364. length = (le32_to_cpu(rx_ring[rx_new].status)
  365. >> 16);
  366. /* Pass the packet up to the protocol layers */
  367. net_process_received_packet
  368. (net_rx_packets[rx_new], length - 4);
  369. }
  370. /*
  371. * Change buffer ownership for this frame,
  372. * back to the adapter.
  373. */
  374. rx_ring[rx_new].status = cpu_to_le32(R_OWN);
  375. }
  376. /* Update entry information. */
  377. rx_new = (rx_new + 1) % rx_ring_size;
  378. }
  379. return length;
  380. }
  381. static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
  382. {
  383. int i;
  384. int devbusfn = (int)dev->priv;
  385. /* Ensure we're not sleeping. */
  386. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
  387. reset_de4x5(dev);
  388. if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
  389. printf("Error: Cannot reset ethernet controller.\n");
  390. return -1;
  391. }
  392. dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
  393. for (i = 0; i < NUM_RX_DESC; i++) {
  394. rx_ring[i].status = cpu_to_le32(R_OWN);
  395. rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
  396. rx_ring[i].buf =
  397. cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
  398. rx_ring[i].next = 0;
  399. }
  400. for (i = 0; i < NUM_TX_DESC; i++) {
  401. tx_ring[i].status = 0;
  402. tx_ring[i].des1 = 0;
  403. tx_ring[i].buf = 0;
  404. tx_ring[i].next = 0;
  405. }
  406. rx_ring_size = NUM_RX_DESC;
  407. tx_ring_size = NUM_TX_DESC;
  408. /* Write the end of list marker to the descriptor lists. */
  409. rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
  410. tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
  411. /* Tell the adapter where the TX/RX rings are located. */
  412. dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
  413. dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
  414. start_de4x5(dev);
  415. tx_new = 0;
  416. rx_new = 0;
  417. send_setup_frame(dev, bis);
  418. return 0;
  419. }
  420. static void dc21x4x_halt(struct eth_device *dev)
  421. {
  422. int devbusfn = (int)dev->priv;
  423. stop_de4x5(dev);
  424. dc2114x_outl(dev, 0, DE4X5_SICR);
  425. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
  426. }
  427. static void read_hw_addr(struct eth_device *dev, bd_t *bis)
  428. {
  429. u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
  430. int i, j = 0;
  431. for (i = 0; i < (ETH_ALEN >> 1); i++) {
  432. tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
  433. *p = le16_to_cpu(tmp);
  434. j += *p++;
  435. }
  436. if (!j || j == 0x2fffd) {
  437. memset(dev->enetaddr, 0, ETH_ALEN);
  438. debug("Warning: can't read HW address from SROM.\n");
  439. #ifdef UPDATE_SROM
  440. update_srom(dev, bis);
  441. #endif
  442. }
  443. }
  444. static struct pci_device_id supported[] = {
  445. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
  446. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
  447. { }
  448. };
  449. int dc21x4x_initialize(bd_t *bis)
  450. {
  451. struct eth_device *dev;
  452. unsigned short status;
  453. unsigned char timer;
  454. unsigned int iobase;
  455. int card_number = 0;
  456. pci_dev_t devbusfn;
  457. unsigned int cfrv;
  458. int idx = 0;
  459. while (1) {
  460. devbusfn = pci_find_devices(supported, idx++);
  461. if (devbusfn == -1)
  462. break;
  463. /* Get the chip configuration revision register. */
  464. pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
  465. if ((cfrv & CFRV_RN) < DC2114x_BRK) {
  466. printf("Error: The chip is not DC21143.\n");
  467. continue;
  468. }
  469. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  470. status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  471. pci_write_config_word(devbusfn, PCI_COMMAND, status);
  472. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  473. if (!(status & PCI_COMMAND_MEMORY)) {
  474. printf("Error: Can not enable MEMORY access.\n");
  475. continue;
  476. }
  477. if (!(status & PCI_COMMAND_MASTER)) {
  478. printf("Error: Can not enable Bus Mastering.\n");
  479. continue;
  480. }
  481. /* Check the latency timer for values >= 0x60. */
  482. pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
  483. if (timer < 0x60) {
  484. pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
  485. 0x60);
  486. }
  487. /* read BAR for memory space access */
  488. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
  489. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  490. debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
  491. dev = (struct eth_device *)malloc(sizeof(*dev));
  492. if (!dev) {
  493. printf("Can not allocalte memory of dc21x4x\n");
  494. break;
  495. }
  496. memset(dev, 0, sizeof(*dev));
  497. sprintf(dev->name, "dc21x4x#%d", card_number);
  498. dev->iobase = pci_mem_to_phys(devbusfn, iobase);
  499. dev->priv = (void *)devbusfn;
  500. dev->init = dc21x4x_init;
  501. dev->halt = dc21x4x_halt;
  502. dev->send = dc21x4x_send;
  503. dev->recv = dc21x4x_recv;
  504. /* Ensure we're not sleeping. */
  505. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
  506. udelay(10 * 1000);
  507. read_hw_addr(dev, bis);
  508. eth_register(dev);
  509. card_number++;
  510. }
  511. return card_number;
  512. }