altera_tse.c 18 KB

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  1. /*
  2. * Altera 10/100/1000 triple speed ethernet mac driver
  3. *
  4. * Copyright (C) 2008 Altera Corporation.
  5. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <fdt_support.h>
  16. #include <log.h>
  17. #include <memalign.h>
  18. #include <miiphy.h>
  19. #include <net.h>
  20. #include <asm/cache.h>
  21. #include <linux/dma-mapping.h>
  22. #include <asm/io.h>
  23. #include "altera_tse.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static inline void alt_sgdma_construct_descriptor(
  26. struct alt_sgdma_descriptor *desc,
  27. struct alt_sgdma_descriptor *next,
  28. void *read_addr,
  29. void *write_addr,
  30. u16 length_or_eop,
  31. int generate_eop,
  32. int read_fixed,
  33. int write_fixed_or_sop)
  34. {
  35. u8 val;
  36. /*
  37. * Mark the "next" descriptor as "not" owned by hardware. This prevents
  38. * The SGDMA controller from continuing to process the chain.
  39. */
  40. next->descriptor_control = next->descriptor_control &
  41. ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  42. memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
  43. desc->source = virt_to_phys(read_addr);
  44. desc->destination = virt_to_phys(write_addr);
  45. desc->next = virt_to_phys(next);
  46. desc->bytes_to_transfer = length_or_eop;
  47. /*
  48. * Set the descriptor control block as follows:
  49. * - Set "owned by hardware" bit
  50. * - Optionally set "generate EOP" bit
  51. * - Optionally set the "read from fixed address" bit
  52. * - Optionally set the "write to fixed address bit (which serves
  53. * serves as a "generate SOP" control bit in memory-to-stream mode).
  54. * - Set the 4-bit atlantic channel, if specified
  55. *
  56. * Note this step is performed after all other descriptor information
  57. * has been filled out so that, if the controller already happens to be
  58. * pointing at this descriptor, it will not run (via the "owned by
  59. * hardware" bit) until all other descriptor has been set up.
  60. */
  61. val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  62. if (generate_eop)
  63. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
  64. if (read_fixed)
  65. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
  66. if (write_fixed_or_sop)
  67. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
  68. desc->descriptor_control = val;
  69. }
  70. static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
  71. {
  72. int status;
  73. ulong ctime;
  74. /* Wait for the descriptor (chain) to complete */
  75. ctime = get_timer(0);
  76. while (1) {
  77. status = readl(&regs->status);
  78. if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
  79. break;
  80. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  81. status = -ETIMEDOUT;
  82. debug("sgdma timeout\n");
  83. break;
  84. }
  85. }
  86. /* Clear Run */
  87. writel(0, &regs->control);
  88. /* Clear status */
  89. writel(0xff, &regs->status);
  90. return status;
  91. }
  92. static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
  93. struct alt_sgdma_descriptor *desc)
  94. {
  95. u32 val;
  96. /* Point the controller at the descriptor */
  97. writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
  98. /*
  99. * Set up SGDMA controller to:
  100. * - Disable interrupt generation
  101. * - Run once a valid descriptor is written to controller
  102. * - Stop on an error with any particular descriptor
  103. */
  104. val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
  105. writel(val, &regs->control);
  106. return 0;
  107. }
  108. static void tse_adjust_link(struct altera_tse_priv *priv,
  109. struct phy_device *phydev)
  110. {
  111. struct alt_tse_mac *mac_dev = priv->mac_dev;
  112. u32 refvar;
  113. if (!phydev->link) {
  114. debug("%s: No link.\n", phydev->dev->name);
  115. return;
  116. }
  117. refvar = readl(&mac_dev->command_config);
  118. if (phydev->duplex)
  119. refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
  120. else
  121. refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
  122. switch (phydev->speed) {
  123. case 1000:
  124. refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
  125. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  126. break;
  127. case 100:
  128. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  129. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  130. break;
  131. case 10:
  132. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  133. refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
  134. break;
  135. }
  136. writel(refvar, &mac_dev->command_config);
  137. }
  138. static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
  139. {
  140. struct altera_tse_priv *priv = dev_get_priv(dev);
  141. struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
  142. alt_sgdma_construct_descriptor(
  143. tx_desc,
  144. tx_desc + 1,
  145. packet, /* read addr */
  146. NULL, /* write addr */
  147. length, /* length or EOP ,will change for each tx */
  148. 1, /* gen eop */
  149. 0, /* read fixed */
  150. 1 /* write fixed or sop */
  151. );
  152. /* send the packet */
  153. alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
  154. alt_sgdma_wait_transfer(priv->sgdma_tx);
  155. debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
  156. return tx_desc->actual_bytes_transferred;
  157. }
  158. static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
  159. uchar **packetp)
  160. {
  161. struct altera_tse_priv *priv = dev_get_priv(dev);
  162. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  163. int packet_length;
  164. if (rx_desc->descriptor_status &
  165. ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
  166. alt_sgdma_wait_transfer(priv->sgdma_rx);
  167. packet_length = rx_desc->actual_bytes_transferred;
  168. debug("recv %d bytes\n", packet_length);
  169. *packetp = priv->rx_buf;
  170. return packet_length;
  171. }
  172. return -EAGAIN;
  173. }
  174. static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
  175. int length)
  176. {
  177. struct altera_tse_priv *priv = dev_get_priv(dev);
  178. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  179. alt_sgdma_construct_descriptor(
  180. rx_desc,
  181. rx_desc + 1,
  182. NULL, /* read addr */
  183. priv->rx_buf, /* write addr */
  184. 0, /* length or EOP */
  185. 0, /* gen eop */
  186. 0, /* read fixed */
  187. 0 /* write fixed or sop */
  188. );
  189. /* setup the sgdma */
  190. alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
  191. debug("recv setup\n");
  192. return 0;
  193. }
  194. static void altera_tse_stop_mac(struct altera_tse_priv *priv)
  195. {
  196. struct alt_tse_mac *mac_dev = priv->mac_dev;
  197. u32 status;
  198. ulong ctime;
  199. /* reset the mac */
  200. writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
  201. ctime = get_timer(0);
  202. while (1) {
  203. status = readl(&mac_dev->command_config);
  204. if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
  205. break;
  206. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  207. debug("Reset mac timeout\n");
  208. break;
  209. }
  210. }
  211. }
  212. static void altera_tse_stop_sgdma(struct udevice *dev)
  213. {
  214. struct altera_tse_priv *priv = dev_get_priv(dev);
  215. struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
  216. struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
  217. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  218. int ret;
  219. /* clear rx desc & wait for sgdma to complete */
  220. rx_desc->descriptor_control = 0;
  221. writel(0, &rx_sgdma->control);
  222. ret = alt_sgdma_wait_transfer(rx_sgdma);
  223. if (ret == -ETIMEDOUT)
  224. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  225. &rx_sgdma->control);
  226. writel(0, &tx_sgdma->control);
  227. ret = alt_sgdma_wait_transfer(tx_sgdma);
  228. if (ret == -ETIMEDOUT)
  229. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  230. &tx_sgdma->control);
  231. }
  232. static void msgdma_reset(struct msgdma_csr *csr)
  233. {
  234. u32 status;
  235. ulong ctime;
  236. /* Reset mSGDMA */
  237. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  238. writel(MSGDMA_CSR_CTL_RESET, &csr->control);
  239. ctime = get_timer(0);
  240. while (1) {
  241. status = readl(&csr->status);
  242. if (!(status & MSGDMA_CSR_STAT_RESETTING))
  243. break;
  244. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  245. debug("Reset msgdma timeout\n");
  246. break;
  247. }
  248. }
  249. /* Clear status */
  250. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  251. }
  252. static u32 msgdma_wait(struct msgdma_csr *csr)
  253. {
  254. u32 status;
  255. ulong ctime;
  256. /* Wait for the descriptor to complete */
  257. ctime = get_timer(0);
  258. while (1) {
  259. status = readl(&csr->status);
  260. if (!(status & MSGDMA_CSR_STAT_BUSY))
  261. break;
  262. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  263. debug("sgdma timeout\n");
  264. break;
  265. }
  266. }
  267. /* Clear status */
  268. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  269. return status;
  270. }
  271. static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
  272. int length)
  273. {
  274. struct altera_tse_priv *priv = dev_get_priv(dev);
  275. struct msgdma_extended_desc *desc = priv->tx_desc;
  276. u32 tx_buf = virt_to_phys(packet);
  277. u32 status;
  278. writel(tx_buf, &desc->read_addr_lo);
  279. writel(0, &desc->read_addr_hi);
  280. writel(0, &desc->write_addr_lo);
  281. writel(0, &desc->write_addr_hi);
  282. writel(length, &desc->len);
  283. writel(0, &desc->burst_seq_num);
  284. writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
  285. writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
  286. status = msgdma_wait(priv->sgdma_tx);
  287. debug("sent %d bytes, status %08x\n", length, status);
  288. return 0;
  289. }
  290. static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
  291. uchar **packetp)
  292. {
  293. struct altera_tse_priv *priv = dev_get_priv(dev);
  294. struct msgdma_csr *csr = priv->sgdma_rx;
  295. struct msgdma_response *resp = priv->rx_resp;
  296. u32 level, length, status;
  297. level = readl(&csr->resp_fill_level);
  298. if (level & 0xffff) {
  299. length = readl(&resp->bytes_transferred);
  300. status = readl(&resp->status);
  301. debug("recv %d bytes, status %08x\n", length, status);
  302. *packetp = priv->rx_buf;
  303. return length;
  304. }
  305. return -EAGAIN;
  306. }
  307. static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
  308. int length)
  309. {
  310. struct altera_tse_priv *priv = dev_get_priv(dev);
  311. struct msgdma_extended_desc *desc = priv->rx_desc;
  312. u32 rx_buf = virt_to_phys(priv->rx_buf);
  313. writel(0, &desc->read_addr_lo);
  314. writel(0, &desc->read_addr_hi);
  315. writel(rx_buf, &desc->write_addr_lo);
  316. writel(0, &desc->write_addr_hi);
  317. writel(PKTSIZE_ALIGN, &desc->len);
  318. writel(0, &desc->burst_seq_num);
  319. writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
  320. writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
  321. debug("recv setup\n");
  322. return 0;
  323. }
  324. static void altera_tse_stop_msgdma(struct udevice *dev)
  325. {
  326. struct altera_tse_priv *priv = dev_get_priv(dev);
  327. msgdma_reset(priv->sgdma_rx);
  328. msgdma_reset(priv->sgdma_tx);
  329. }
  330. static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  331. {
  332. struct altera_tse_priv *priv = bus->priv;
  333. struct alt_tse_mac *mac_dev = priv->mac_dev;
  334. u32 value;
  335. /* set mdio address */
  336. writel(addr, &mac_dev->mdio_phy1_addr);
  337. /* get the data */
  338. value = readl(&mac_dev->mdio_phy1[reg]);
  339. return value & 0xffff;
  340. }
  341. static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  342. u16 val)
  343. {
  344. struct altera_tse_priv *priv = bus->priv;
  345. struct alt_tse_mac *mac_dev = priv->mac_dev;
  346. /* set mdio address */
  347. writel(addr, &mac_dev->mdio_phy1_addr);
  348. /* set the data */
  349. writel(val, &mac_dev->mdio_phy1[reg]);
  350. return 0;
  351. }
  352. static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
  353. {
  354. struct mii_dev *bus = mdio_alloc();
  355. if (!bus) {
  356. printf("Failed to allocate MDIO bus\n");
  357. return -ENOMEM;
  358. }
  359. bus->read = tse_mdio_read;
  360. bus->write = tse_mdio_write;
  361. snprintf(bus->name, sizeof(bus->name), "%s", name);
  362. bus->priv = (void *)priv;
  363. return mdio_register(bus);
  364. }
  365. static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
  366. {
  367. struct phy_device *phydev;
  368. unsigned int mask = 0xffffffff;
  369. if (priv->phyaddr)
  370. mask = 1 << priv->phyaddr;
  371. phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
  372. if (!phydev)
  373. return -ENODEV;
  374. phy_connect_dev(phydev, dev);
  375. phydev->supported &= PHY_GBIT_FEATURES;
  376. phydev->advertising = phydev->supported;
  377. priv->phydev = phydev;
  378. phy_config(phydev);
  379. return 0;
  380. }
  381. static int altera_tse_write_hwaddr(struct udevice *dev)
  382. {
  383. struct altera_tse_priv *priv = dev_get_priv(dev);
  384. struct alt_tse_mac *mac_dev = priv->mac_dev;
  385. struct eth_pdata *pdata = dev_get_platdata(dev);
  386. u8 *hwaddr = pdata->enetaddr;
  387. u32 mac_lo, mac_hi;
  388. mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
  389. (hwaddr[1] << 8) | hwaddr[0];
  390. mac_hi = (hwaddr[5] << 8) | hwaddr[4];
  391. debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
  392. writel(mac_lo, &mac_dev->mac_addr_0);
  393. writel(mac_hi, &mac_dev->mac_addr_1);
  394. writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
  395. writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
  396. writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
  397. writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
  398. writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
  399. writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
  400. writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
  401. writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
  402. return 0;
  403. }
  404. static int altera_tse_send(struct udevice *dev, void *packet, int length)
  405. {
  406. struct altera_tse_priv *priv = dev_get_priv(dev);
  407. unsigned long tx_buf = (unsigned long)packet;
  408. flush_dcache_range(tx_buf, tx_buf + length);
  409. return priv->ops->send(dev, packet, length);
  410. }
  411. static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
  412. {
  413. struct altera_tse_priv *priv = dev_get_priv(dev);
  414. return priv->ops->recv(dev, flags, packetp);
  415. }
  416. static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
  417. int length)
  418. {
  419. struct altera_tse_priv *priv = dev_get_priv(dev);
  420. unsigned long rx_buf = (unsigned long)priv->rx_buf;
  421. invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
  422. return priv->ops->free_pkt(dev, packet, length);
  423. }
  424. static void altera_tse_stop(struct udevice *dev)
  425. {
  426. struct altera_tse_priv *priv = dev_get_priv(dev);
  427. priv->ops->stop(dev);
  428. altera_tse_stop_mac(priv);
  429. }
  430. static int altera_tse_start(struct udevice *dev)
  431. {
  432. struct altera_tse_priv *priv = dev_get_priv(dev);
  433. struct alt_tse_mac *mac_dev = priv->mac_dev;
  434. u32 val;
  435. int ret;
  436. /* need to create sgdma */
  437. debug("Configuring rx desc\n");
  438. altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
  439. /* start TSE */
  440. debug("Configuring TSE Mac\n");
  441. /* Initialize MAC registers */
  442. writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
  443. writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
  444. writel(0, &mac_dev->rx_sel_full_threshold);
  445. writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
  446. writel(0, &mac_dev->tx_sel_full_threshold);
  447. writel(8, &mac_dev->rx_almost_empty_threshold);
  448. writel(8, &mac_dev->rx_almost_full_threshold);
  449. writel(8, &mac_dev->tx_almost_empty_threshold);
  450. writel(3, &mac_dev->tx_almost_full_threshold);
  451. /* NO Shift */
  452. writel(0, &mac_dev->rx_cmd_stat);
  453. writel(0, &mac_dev->tx_cmd_stat);
  454. /* enable MAC */
  455. val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
  456. writel(val, &mac_dev->command_config);
  457. /* Start up the PHY */
  458. ret = phy_startup(priv->phydev);
  459. if (ret) {
  460. debug("Could not initialize PHY %s\n",
  461. priv->phydev->dev->name);
  462. return ret;
  463. }
  464. tse_adjust_link(priv, priv->phydev);
  465. if (!priv->phydev->link)
  466. return -EIO;
  467. return 0;
  468. }
  469. static const struct tse_ops tse_sgdma_ops = {
  470. .send = altera_tse_send_sgdma,
  471. .recv = altera_tse_recv_sgdma,
  472. .free_pkt = altera_tse_free_pkt_sgdma,
  473. .stop = altera_tse_stop_sgdma,
  474. };
  475. static const struct tse_ops tse_msgdma_ops = {
  476. .send = altera_tse_send_msgdma,
  477. .recv = altera_tse_recv_msgdma,
  478. .free_pkt = altera_tse_free_pkt_msgdma,
  479. .stop = altera_tse_stop_msgdma,
  480. };
  481. static int altera_tse_probe(struct udevice *dev)
  482. {
  483. struct eth_pdata *pdata = dev_get_platdata(dev);
  484. struct altera_tse_priv *priv = dev_get_priv(dev);
  485. void *blob = (void *)gd->fdt_blob;
  486. int node = dev_of_offset(dev);
  487. const char *list, *end;
  488. const fdt32_t *cell;
  489. void *base, *desc_mem = NULL;
  490. unsigned long addr, size;
  491. int parent, addrc, sizec;
  492. int len, idx;
  493. int ret;
  494. priv->dma_type = dev_get_driver_data(dev);
  495. if (priv->dma_type == ALT_SGDMA)
  496. priv->ops = &tse_sgdma_ops;
  497. else
  498. priv->ops = &tse_msgdma_ops;
  499. /*
  500. * decode regs. there are multiple reg tuples, and they need to
  501. * match with reg-names.
  502. */
  503. parent = fdt_parent_offset(blob, node);
  504. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  505. list = fdt_getprop(blob, node, "reg-names", &len);
  506. if (!list)
  507. return -ENOENT;
  508. end = list + len;
  509. cell = fdt_getprop(blob, node, "reg", &len);
  510. if (!cell)
  511. return -ENOENT;
  512. idx = 0;
  513. while (list < end) {
  514. addr = fdt_translate_address((void *)blob,
  515. node, cell + idx);
  516. size = fdt_addr_to_cpu(cell[idx + addrc]);
  517. base = map_physmem(addr, size, MAP_NOCACHE);
  518. len = strlen(list);
  519. if (strcmp(list, "control_port") == 0)
  520. priv->mac_dev = base;
  521. else if (strcmp(list, "rx_csr") == 0)
  522. priv->sgdma_rx = base;
  523. else if (strcmp(list, "rx_desc") == 0)
  524. priv->rx_desc = base;
  525. else if (strcmp(list, "rx_resp") == 0)
  526. priv->rx_resp = base;
  527. else if (strcmp(list, "tx_csr") == 0)
  528. priv->sgdma_tx = base;
  529. else if (strcmp(list, "tx_desc") == 0)
  530. priv->tx_desc = base;
  531. else if (strcmp(list, "s1") == 0)
  532. desc_mem = base;
  533. idx += addrc + sizec;
  534. list += (len + 1);
  535. }
  536. /* decode fifo depth */
  537. priv->rx_fifo_depth = fdtdec_get_int(blob, node,
  538. "rx-fifo-depth", 0);
  539. priv->tx_fifo_depth = fdtdec_get_int(blob, node,
  540. "tx-fifo-depth", 0);
  541. /* decode phy */
  542. addr = fdtdec_get_int(blob, node,
  543. "phy-handle", 0);
  544. addr = fdt_node_offset_by_phandle(blob, addr);
  545. priv->phyaddr = fdtdec_get_int(blob, addr,
  546. "reg", 0);
  547. /* init desc */
  548. if (priv->dma_type == ALT_SGDMA) {
  549. len = sizeof(struct alt_sgdma_descriptor) * 4;
  550. if (!desc_mem) {
  551. desc_mem = dma_alloc_coherent(len, &addr);
  552. if (!desc_mem)
  553. return -ENOMEM;
  554. }
  555. memset(desc_mem, 0, len);
  556. priv->tx_desc = desc_mem;
  557. priv->rx_desc = priv->tx_desc +
  558. 2 * sizeof(struct alt_sgdma_descriptor);
  559. }
  560. /* allocate recv packet buffer */
  561. priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
  562. if (!priv->rx_buf)
  563. return -ENOMEM;
  564. /* stop controller */
  565. debug("Reset TSE & SGDMAs\n");
  566. altera_tse_stop(dev);
  567. /* start the phy */
  568. priv->interface = pdata->phy_interface;
  569. tse_mdio_init(dev->name, priv);
  570. priv->bus = miiphy_get_dev_by_name(dev->name);
  571. ret = tse_phy_init(priv, dev);
  572. return ret;
  573. }
  574. static int altera_tse_ofdata_to_platdata(struct udevice *dev)
  575. {
  576. struct eth_pdata *pdata = dev_get_platdata(dev);
  577. const char *phy_mode;
  578. pdata->phy_interface = -1;
  579. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  580. NULL);
  581. if (phy_mode)
  582. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  583. if (pdata->phy_interface == -1) {
  584. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  585. return -EINVAL;
  586. }
  587. return 0;
  588. }
  589. static const struct eth_ops altera_tse_ops = {
  590. .start = altera_tse_start,
  591. .send = altera_tse_send,
  592. .recv = altera_tse_recv,
  593. .free_pkt = altera_tse_free_pkt,
  594. .stop = altera_tse_stop,
  595. .write_hwaddr = altera_tse_write_hwaddr,
  596. };
  597. static const struct udevice_id altera_tse_ids[] = {
  598. { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
  599. { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
  600. {}
  601. };
  602. U_BOOT_DRIVER(altera_tse) = {
  603. .name = "altera_tse",
  604. .id = UCLASS_ETH,
  605. .of_match = altera_tse_ids,
  606. .ops = &altera_tse_ops,
  607. .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
  608. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  609. .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
  610. .probe = altera_tse_probe,
  611. };