zynq_sdhci.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <linux/delay.h>
  12. #include "mmc_private.h"
  13. #include <log.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/err.h>
  16. #include <linux/libfdt.h>
  17. #include <malloc.h>
  18. #include <sdhci.h>
  19. #include <zynqmp_tap_delay.h>
  20. struct arasan_sdhci_plat {
  21. struct mmc_config cfg;
  22. struct mmc mmc;
  23. };
  24. struct arasan_sdhci_priv {
  25. struct sdhci_host *host;
  26. u8 deviceid;
  27. u8 bank;
  28. };
  29. #if defined(CONFIG_ARCH_ZYNQMP)
  30. #define MMC_HS200_BUS_SPEED 5
  31. static const u8 mode2timing[] = {
  32. [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
  33. [MMC_HS] = HIGH_SPEED_BUS_SPEED,
  34. [SD_HS] = HIGH_SPEED_BUS_SPEED,
  35. [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
  36. [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
  37. [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  38. [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  39. [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  40. [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  41. [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  42. [MMC_HS_200] = MMC_HS200_BUS_SPEED,
  43. };
  44. #define SDHCI_TUNING_LOOP_COUNT 40
  45. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  46. {
  47. u16 clk;
  48. unsigned long timeout;
  49. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  50. clk &= ~(SDHCI_CLOCK_CARD_EN);
  51. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  52. /* Issue DLL Reset */
  53. zynqmp_dll_reset(deviceid);
  54. /* Wait max 20 ms */
  55. timeout = 100;
  56. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  57. & SDHCI_CLOCK_INT_STABLE)) {
  58. if (timeout == 0) {
  59. dev_err(mmc_dev(host->mmc),
  60. ": Internal clock never stabilised.\n");
  61. return;
  62. }
  63. timeout--;
  64. udelay(1000);
  65. }
  66. clk |= SDHCI_CLOCK_CARD_EN;
  67. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  68. }
  69. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  70. {
  71. struct mmc_cmd cmd;
  72. struct mmc_data data;
  73. u32 ctrl;
  74. struct sdhci_host *host;
  75. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  76. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  77. u8 deviceid;
  78. debug("%s\n", __func__);
  79. host = priv->host;
  80. deviceid = priv->deviceid;
  81. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  82. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  83. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  84. mdelay(1);
  85. arasan_zynqmp_dll_reset(host, deviceid);
  86. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  87. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  88. do {
  89. cmd.cmdidx = opcode;
  90. cmd.resp_type = MMC_RSP_R1;
  91. cmd.cmdarg = 0;
  92. data.blocksize = 64;
  93. data.blocks = 1;
  94. data.flags = MMC_DATA_READ;
  95. if (tuning_loop_counter-- == 0)
  96. break;
  97. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  98. mmc->bus_width == 8)
  99. data.blocksize = 128;
  100. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  101. data.blocksize),
  102. SDHCI_BLOCK_SIZE);
  103. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  104. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  105. mmc_send_cmd(mmc, &cmd, NULL);
  106. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  107. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  108. udelay(1);
  109. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  110. if (tuning_loop_counter < 0) {
  111. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  112. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  113. }
  114. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  115. printf("%s:Tuning failed\n", __func__);
  116. return -1;
  117. }
  118. udelay(1);
  119. arasan_zynqmp_dll_reset(host, deviceid);
  120. /* Enable only interrupts served by the SD controller */
  121. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  122. SDHCI_INT_ENABLE);
  123. /* Mask all sdhci interrupt sources */
  124. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  125. return 0;
  126. }
  127. static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  128. {
  129. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  130. struct mmc *mmc = (struct mmc *)host->mmc;
  131. u8 uhsmode;
  132. uhsmode = mode2timing[mmc->selected_mode];
  133. if (uhsmode >= UHS_SDR25_BUS_SPEED)
  134. arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
  135. priv->bank);
  136. }
  137. static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  138. {
  139. struct mmc *mmc = (struct mmc *)host->mmc;
  140. u32 reg;
  141. if (!IS_SD(mmc))
  142. return;
  143. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  144. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  145. reg |= SDHCI_CTRL_VDD_180;
  146. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  147. }
  148. if (mmc->selected_mode > SD_HS &&
  149. mmc->selected_mode <= UHS_DDR50)
  150. sdhci_set_uhs_timing(host);
  151. }
  152. #endif
  153. #if defined(CONFIG_ARCH_ZYNQMP)
  154. const struct sdhci_ops arasan_ops = {
  155. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  156. .set_delay = &arasan_sdhci_set_tapdelay,
  157. .set_control_reg = &arasan_sdhci_set_control_reg,
  158. };
  159. #endif
  160. static int arasan_sdhci_probe(struct udevice *dev)
  161. {
  162. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  163. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  164. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  165. struct sdhci_host *host;
  166. struct clk clk;
  167. unsigned long clock;
  168. int ret;
  169. host = priv->host;
  170. ret = clk_get_by_index(dev, 0, &clk);
  171. if (ret < 0) {
  172. dev_err(dev, "failed to get clock\n");
  173. return ret;
  174. }
  175. clock = clk_get_rate(&clk);
  176. if (IS_ERR_VALUE(clock)) {
  177. dev_err(dev, "failed to get rate\n");
  178. return clock;
  179. }
  180. debug("%s: CLK %ld\n", __func__, clock);
  181. ret = clk_enable(&clk);
  182. if (ret && ret != -ENOSYS) {
  183. dev_err(dev, "failed to enable clock\n");
  184. return ret;
  185. }
  186. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  187. SDHCI_QUIRK_BROKEN_R1B;
  188. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  189. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  190. #endif
  191. plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
  192. ret = mmc_of_parse(dev, &plat->cfg);
  193. if (ret)
  194. return ret;
  195. host->max_clk = clock;
  196. host->mmc = &plat->mmc;
  197. host->mmc->dev = dev;
  198. host->mmc->priv = host;
  199. ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
  200. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  201. if (ret)
  202. return ret;
  203. upriv->mmc = host->mmc;
  204. return sdhci_probe(dev);
  205. }
  206. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  207. {
  208. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  209. priv->host = calloc(1, sizeof(struct sdhci_host));
  210. if (!priv->host)
  211. return -1;
  212. priv->host->name = dev->name;
  213. #if defined(CONFIG_ARCH_ZYNQMP)
  214. priv->host->ops = &arasan_ops;
  215. #endif
  216. priv->host->ioaddr = (void *)dev_read_addr(dev);
  217. if (IS_ERR(priv->host->ioaddr))
  218. return PTR_ERR(priv->host->ioaddr);
  219. priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
  220. priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
  221. return 0;
  222. }
  223. static int arasan_sdhci_bind(struct udevice *dev)
  224. {
  225. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  226. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  227. }
  228. static const struct udevice_id arasan_sdhci_ids[] = {
  229. { .compatible = "arasan,sdhci-8.9a" },
  230. { }
  231. };
  232. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  233. .name = "arasan_sdhci",
  234. .id = UCLASS_MMC,
  235. .of_match = arasan_sdhci_ids,
  236. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  237. .ops = &sdhci_ops,
  238. .bind = arasan_sdhci_bind,
  239. .probe = arasan_sdhci_probe,
  240. .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
  241. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  242. };