tmio-common.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <fdtdec.h>
  10. #include <mmc.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/pinctrl.h>
  14. #include <linux/compat.h>
  15. #include <linux/delay.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/io.h>
  18. #include <linux/sizes.h>
  19. #include <power/regulator.h>
  20. #include <asm/unaligned.h>
  21. #include "tmio-common.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
  24. {
  25. return readq(priv->regbase + (reg << 1));
  26. }
  27. static void tmio_sd_writeq(struct tmio_sd_priv *priv,
  28. u64 val, unsigned int reg)
  29. {
  30. writeq(val, priv->regbase + (reg << 1));
  31. }
  32. static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
  33. {
  34. return readw(priv->regbase + (reg >> 1));
  35. }
  36. static void tmio_sd_writew(struct tmio_sd_priv *priv,
  37. u16 val, unsigned int reg)
  38. {
  39. writew(val, priv->regbase + (reg >> 1));
  40. }
  41. u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
  42. {
  43. u32 val;
  44. if (priv->caps & TMIO_SD_CAP_64BIT)
  45. return readl(priv->regbase + (reg << 1));
  46. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  47. val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  48. if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
  49. (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
  50. val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  51. }
  52. return val;
  53. } else
  54. return readl(priv->regbase + reg);
  55. }
  56. void tmio_sd_writel(struct tmio_sd_priv *priv,
  57. u32 val, unsigned int reg)
  58. {
  59. if (priv->caps & TMIO_SD_CAP_64BIT)
  60. writel(val, priv->regbase + (reg << 1));
  61. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  62. writew(val & 0xffff, priv->regbase + (reg >> 1));
  63. if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
  64. reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
  65. reg == TMIO_SD_ARG)
  66. writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  67. } else
  68. writel(val, priv->regbase + reg);
  69. }
  70. static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
  71. {
  72. struct tmio_sd_priv *priv = dev_get_priv(dev);
  73. u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
  74. if (info2 & TMIO_SD_INFO2_ERR_RTO) {
  75. /*
  76. * TIMEOUT must be returned for unsupported command. Do not
  77. * display error log since this might be a part of sequence to
  78. * distinguish between SD and MMC.
  79. */
  80. return -ETIMEDOUT;
  81. }
  82. if (info2 & TMIO_SD_INFO2_ERR_TO) {
  83. dev_err(dev, "timeout error\n");
  84. return -ETIMEDOUT;
  85. }
  86. if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
  87. TMIO_SD_INFO2_ERR_IDX)) {
  88. if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
  89. (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  90. dev_err(dev, "communication out of sync\n");
  91. return -EILSEQ;
  92. }
  93. if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
  94. TMIO_SD_INFO2_ERR_ILW)) {
  95. dev_err(dev, "illegal access\n");
  96. return -EIO;
  97. }
  98. return 0;
  99. }
  100. static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
  101. unsigned int reg, u32 flag)
  102. {
  103. struct tmio_sd_priv *priv = dev_get_priv(dev);
  104. long wait = 1000000;
  105. int ret;
  106. while (!(tmio_sd_readl(priv, reg) & flag)) {
  107. if (wait-- < 0) {
  108. dev_err(dev, "timeout\n");
  109. return -ETIMEDOUT;
  110. }
  111. ret = tmio_sd_check_error(dev, cmd);
  112. if (ret)
  113. return ret;
  114. udelay(1);
  115. }
  116. return 0;
  117. }
  118. #define tmio_pio_read_fifo(__width, __suffix) \
  119. static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
  120. char *pbuf, uint blksz) \
  121. { \
  122. u##__width *buf = (u##__width *)pbuf; \
  123. int i; \
  124. \
  125. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  126. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  127. *buf++ = tmio_sd_read##__suffix(priv, \
  128. TMIO_SD_BUF); \
  129. } \
  130. } else { \
  131. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  132. u##__width data; \
  133. data = tmio_sd_read##__suffix(priv, \
  134. TMIO_SD_BUF); \
  135. put_unaligned(data, buf++); \
  136. } \
  137. } \
  138. }
  139. tmio_pio_read_fifo(64, q)
  140. tmio_pio_read_fifo(32, l)
  141. tmio_pio_read_fifo(16, w)
  142. static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  143. char *pbuf, uint blocksize)
  144. {
  145. struct tmio_sd_priv *priv = dev_get_priv(dev);
  146. int ret;
  147. /* wait until the buffer is filled with data */
  148. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  149. TMIO_SD_INFO2_BRE);
  150. if (ret)
  151. return ret;
  152. /*
  153. * Clear the status flag _before_ read the buffer out because
  154. * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
  155. */
  156. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  157. if (priv->caps & TMIO_SD_CAP_64BIT)
  158. tmio_pio_read_fifo_64(priv, pbuf, blocksize);
  159. else if (priv->caps & TMIO_SD_CAP_16BIT)
  160. tmio_pio_read_fifo_16(priv, pbuf, blocksize);
  161. else
  162. tmio_pio_read_fifo_32(priv, pbuf, blocksize);
  163. return 0;
  164. }
  165. #define tmio_pio_write_fifo(__width, __suffix) \
  166. static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
  167. const char *pbuf, uint blksz)\
  168. { \
  169. const u##__width *buf = (const u##__width *)pbuf; \
  170. int i; \
  171. \
  172. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  173. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  174. tmio_sd_write##__suffix(priv, *buf++, \
  175. TMIO_SD_BUF); \
  176. } \
  177. } else { \
  178. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  179. u##__width data = get_unaligned(buf++); \
  180. tmio_sd_write##__suffix(priv, data, \
  181. TMIO_SD_BUF); \
  182. } \
  183. } \
  184. }
  185. tmio_pio_write_fifo(64, q)
  186. tmio_pio_write_fifo(32, l)
  187. tmio_pio_write_fifo(16, w)
  188. static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  189. const char *pbuf, uint blocksize)
  190. {
  191. struct tmio_sd_priv *priv = dev_get_priv(dev);
  192. int ret;
  193. /* wait until the buffer becomes empty */
  194. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  195. TMIO_SD_INFO2_BWE);
  196. if (ret)
  197. return ret;
  198. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  199. if (priv->caps & TMIO_SD_CAP_64BIT)
  200. tmio_pio_write_fifo_64(priv, pbuf, blocksize);
  201. else if (priv->caps & TMIO_SD_CAP_16BIT)
  202. tmio_pio_write_fifo_16(priv, pbuf, blocksize);
  203. else
  204. tmio_pio_write_fifo_32(priv, pbuf, blocksize);
  205. return 0;
  206. }
  207. static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
  208. struct mmc_data *data)
  209. {
  210. const char *src = data->src;
  211. char *dest = data->dest;
  212. int i, ret;
  213. for (i = 0; i < data->blocks; i++) {
  214. if (data->flags & MMC_DATA_READ)
  215. ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
  216. data->blocksize);
  217. else
  218. ret = tmio_sd_pio_write_one_block(dev, cmd, src,
  219. data->blocksize);
  220. if (ret)
  221. return ret;
  222. if (data->flags & MMC_DATA_READ)
  223. dest += data->blocksize;
  224. else
  225. src += data->blocksize;
  226. }
  227. return 0;
  228. }
  229. static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
  230. dma_addr_t dma_addr)
  231. {
  232. u32 tmp;
  233. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
  234. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
  235. /* enable DMA */
  236. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  237. tmp |= TMIO_SD_EXTMODE_DMA_EN;
  238. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  239. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
  240. /* suppress the warning "right shift count >= width of type" */
  241. dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
  242. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
  243. tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
  244. }
  245. static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
  246. unsigned int blocks)
  247. {
  248. struct tmio_sd_priv *priv = dev_get_priv(dev);
  249. long wait = 1000000 + 10 * blocks;
  250. while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
  251. if (wait-- < 0) {
  252. dev_err(dev, "timeout during DMA\n");
  253. return -ETIMEDOUT;
  254. }
  255. udelay(10);
  256. }
  257. if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
  258. dev_err(dev, "error during DMA\n");
  259. return -EIO;
  260. }
  261. return 0;
  262. }
  263. static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
  264. {
  265. struct tmio_sd_priv *priv = dev_get_priv(dev);
  266. size_t len = data->blocks * data->blocksize;
  267. void *buf;
  268. enum dma_data_direction dir;
  269. dma_addr_t dma_addr;
  270. u32 poll_flag, tmp;
  271. int ret;
  272. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  273. if (data->flags & MMC_DATA_READ) {
  274. buf = data->dest;
  275. dir = DMA_FROM_DEVICE;
  276. /*
  277. * The DMA READ completion flag position differs on Socionext
  278. * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
  279. * bit 17 is a hardware bug and forbidden. It is either bit 17
  280. * or bit 20 on Renesas SoCs, depending on SoC.
  281. */
  282. poll_flag = priv->read_poll_flag;
  283. tmp |= TMIO_SD_DMA_MODE_DIR_RD;
  284. } else {
  285. buf = (void *)data->src;
  286. dir = DMA_TO_DEVICE;
  287. poll_flag = TMIO_SD_DMA_INFO1_END_WR;
  288. tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
  289. }
  290. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  291. dma_addr = dma_map_single(buf, len, dir);
  292. tmio_sd_dma_start(priv, dma_addr);
  293. ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
  294. if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
  295. udelay(1);
  296. dma_unmap_single(dma_addr, len, dir);
  297. return ret;
  298. }
  299. /* check if the address is DMA'able */
  300. static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
  301. {
  302. uintptr_t addr = (uintptr_t)data->src;
  303. if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
  304. return false;
  305. #if defined(CONFIG_RCAR_GEN3)
  306. if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
  307. return false;
  308. /* Gen3 DMA has 32bit limit */
  309. if (addr >> 32)
  310. return false;
  311. #endif
  312. #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
  313. defined(CONFIG_SPL_BUILD)
  314. /*
  315. * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
  316. * of L2, which is unreachable from the DMA engine.
  317. */
  318. if (addr < CONFIG_SPL_STACK)
  319. return false;
  320. #endif
  321. return true;
  322. }
  323. int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  324. struct mmc_data *data)
  325. {
  326. struct tmio_sd_priv *priv = dev_get_priv(dev);
  327. int ret;
  328. u32 tmp;
  329. if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
  330. dev_err(dev, "command busy\n");
  331. return -EBUSY;
  332. }
  333. /* clear all status flags */
  334. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  335. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  336. /* disable DMA once */
  337. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  338. tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
  339. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  340. tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
  341. tmp = cmd->cmdidx;
  342. if (data) {
  343. tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
  344. tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
  345. /* Do not send CMD12 automatically */
  346. tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
  347. if (data->blocks > 1)
  348. tmp |= TMIO_SD_CMD_MULTI;
  349. if (data->flags & MMC_DATA_READ)
  350. tmp |= TMIO_SD_CMD_RD;
  351. }
  352. /*
  353. * Do not use the response type auto-detection on this hardware.
  354. * CMD8, for example, has different response types on SD and eMMC,
  355. * while this controller always assumes the response type for SD.
  356. * Set the response type manually.
  357. */
  358. switch (cmd->resp_type) {
  359. case MMC_RSP_NONE:
  360. tmp |= TMIO_SD_CMD_RSP_NONE;
  361. break;
  362. case MMC_RSP_R1:
  363. tmp |= TMIO_SD_CMD_RSP_R1;
  364. break;
  365. case MMC_RSP_R1b:
  366. tmp |= TMIO_SD_CMD_RSP_R1B;
  367. break;
  368. case MMC_RSP_R2:
  369. tmp |= TMIO_SD_CMD_RSP_R2;
  370. break;
  371. case MMC_RSP_R3:
  372. tmp |= TMIO_SD_CMD_RSP_R3;
  373. break;
  374. default:
  375. dev_err(dev, "unknown response type\n");
  376. return -EINVAL;
  377. }
  378. dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
  379. cmd->cmdidx, tmp, cmd->cmdarg);
  380. tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
  381. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  382. TMIO_SD_INFO1_RSP);
  383. if (ret)
  384. return ret;
  385. if (cmd->resp_type & MMC_RSP_136) {
  386. u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
  387. u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
  388. u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
  389. u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
  390. cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
  391. ((rsp_103_72 & 0xff000000) >> 24);
  392. cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
  393. ((rsp_71_40 & 0xff000000) >> 24);
  394. cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
  395. ((rsp_39_8 & 0xff000000) >> 24);
  396. cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
  397. } else {
  398. /* bit 39-8 */
  399. cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
  400. }
  401. if (data) {
  402. /* use DMA if the HW supports it and the buffer is aligned */
  403. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
  404. tmio_sd_addr_is_dmaable(data))
  405. ret = tmio_sd_dma_xfer(dev, data);
  406. else
  407. ret = tmio_sd_pio_xfer(dev, cmd, data);
  408. if (ret)
  409. return ret;
  410. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  411. TMIO_SD_INFO1_CMP);
  412. if (ret)
  413. return ret;
  414. }
  415. return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  416. TMIO_SD_INFO2_SCLKDIVEN);
  417. }
  418. static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
  419. struct mmc *mmc)
  420. {
  421. u32 val, tmp;
  422. switch (mmc->bus_width) {
  423. case 0:
  424. case 1:
  425. val = TMIO_SD_OPTION_WIDTH_1;
  426. break;
  427. case 4:
  428. val = TMIO_SD_OPTION_WIDTH_4;
  429. break;
  430. case 8:
  431. val = TMIO_SD_OPTION_WIDTH_8;
  432. break;
  433. default:
  434. return -EINVAL;
  435. }
  436. tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
  437. tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
  438. tmp |= val;
  439. tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
  440. return 0;
  441. }
  442. static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
  443. struct mmc *mmc)
  444. {
  445. u32 tmp;
  446. tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
  447. if (mmc->ddr_mode)
  448. tmp |= TMIO_SD_IF_MODE_DDR;
  449. else
  450. tmp &= ~TMIO_SD_IF_MODE_DDR;
  451. tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
  452. }
  453. static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
  454. {
  455. return priv->clk_get_rate(priv);
  456. }
  457. static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
  458. {
  459. unsigned int divisor;
  460. u32 tmp, val = 0;
  461. ulong mclk;
  462. if (mmc->clock) {
  463. mclk = tmio_sd_clk_get_rate(priv);
  464. divisor = DIV_ROUND_UP(mclk, mmc->clock);
  465. /* Do not set divider to 0xff in DDR mode */
  466. if (mmc->ddr_mode && (divisor == 1))
  467. divisor = 2;
  468. if (divisor <= 1)
  469. val = (priv->caps & TMIO_SD_CAP_RCAR) ?
  470. TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
  471. else if (divisor <= 2)
  472. val = TMIO_SD_CLKCTL_DIV2;
  473. else if (divisor <= 4)
  474. val = TMIO_SD_CLKCTL_DIV4;
  475. else if (divisor <= 8)
  476. val = TMIO_SD_CLKCTL_DIV8;
  477. else if (divisor <= 16)
  478. val = TMIO_SD_CLKCTL_DIV16;
  479. else if (divisor <= 32)
  480. val = TMIO_SD_CLKCTL_DIV32;
  481. else if (divisor <= 64)
  482. val = TMIO_SD_CLKCTL_DIV64;
  483. else if (divisor <= 128)
  484. val = TMIO_SD_CLKCTL_DIV128;
  485. else if (divisor <= 256)
  486. val = TMIO_SD_CLKCTL_DIV256;
  487. else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
  488. val = TMIO_SD_CLKCTL_DIV512;
  489. else
  490. val = TMIO_SD_CLKCTL_DIV1024;
  491. }
  492. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  493. if (mmc->clock &&
  494. !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
  495. ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
  496. /*
  497. * Stop the clock before changing its rate
  498. * to avoid a glitch signal
  499. */
  500. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  501. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  502. /* Change the clock rate. */
  503. tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
  504. tmp |= val;
  505. }
  506. /* Enable or Disable the clock */
  507. if (mmc->clk_disable) {
  508. tmp |= TMIO_SD_CLKCTL_OFFEN;
  509. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  510. } else {
  511. tmp &= ~TMIO_SD_CLKCTL_OFFEN;
  512. tmp |= TMIO_SD_CLKCTL_SCLKEN;
  513. }
  514. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  515. udelay(1000);
  516. }
  517. static void tmio_sd_set_pins(struct udevice *dev)
  518. {
  519. __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
  520. #ifdef CONFIG_DM_REGULATOR
  521. struct tmio_sd_priv *priv = dev_get_priv(dev);
  522. if (priv->vqmmc_dev) {
  523. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  524. regulator_set_value(priv->vqmmc_dev, 1800000);
  525. else
  526. regulator_set_value(priv->vqmmc_dev, 3300000);
  527. regulator_set_enable(priv->vqmmc_dev, true);
  528. }
  529. #endif
  530. #ifdef CONFIG_PINCTRL
  531. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  532. pinctrl_select_state(dev, "state_uhs");
  533. else
  534. pinctrl_select_state(dev, "default");
  535. #endif
  536. }
  537. int tmio_sd_set_ios(struct udevice *dev)
  538. {
  539. struct tmio_sd_priv *priv = dev_get_priv(dev);
  540. struct mmc *mmc = mmc_get_mmc_dev(dev);
  541. int ret;
  542. dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
  543. mmc->clock, mmc->ddr_mode, mmc->bus_width);
  544. tmio_sd_set_clk_rate(priv, mmc);
  545. ret = tmio_sd_set_bus_width(priv, mmc);
  546. if (ret)
  547. return ret;
  548. tmio_sd_set_ddr_mode(priv, mmc);
  549. tmio_sd_set_pins(dev);
  550. return 0;
  551. }
  552. int tmio_sd_get_cd(struct udevice *dev)
  553. {
  554. struct tmio_sd_priv *priv = dev_get_priv(dev);
  555. if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
  556. return 1;
  557. return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
  558. TMIO_SD_INFO1_CD);
  559. }
  560. static void tmio_sd_host_init(struct tmio_sd_priv *priv)
  561. {
  562. u32 tmp;
  563. /* soft reset of the host */
  564. tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
  565. tmp &= ~TMIO_SD_SOFT_RST_RSTX;
  566. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  567. tmp |= TMIO_SD_SOFT_RST_RSTX;
  568. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  569. /* FIXME: implement eMMC hw_reset */
  570. tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
  571. /*
  572. * Connected to 32bit AXI.
  573. * This register dropped backward compatibility at version 0x10.
  574. * Write an appropriate value depending on the IP version.
  575. */
  576. if (priv->version >= 0x10) {
  577. if (priv->caps & TMIO_SD_CAP_64BIT)
  578. tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
  579. else
  580. tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
  581. } else {
  582. tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
  583. }
  584. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
  585. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  586. tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
  587. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  588. }
  589. }
  590. int tmio_sd_bind(struct udevice *dev)
  591. {
  592. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  593. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  594. }
  595. int tmio_sd_probe(struct udevice *dev, u32 quirks)
  596. {
  597. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  598. struct tmio_sd_priv *priv = dev_get_priv(dev);
  599. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  600. fdt_addr_t base;
  601. ulong mclk;
  602. int ret;
  603. base = devfdt_get_addr(dev);
  604. if (base == FDT_ADDR_T_NONE)
  605. return -EINVAL;
  606. priv->regbase = devm_ioremap(dev, base, SZ_2K);
  607. if (!priv->regbase)
  608. return -ENOMEM;
  609. #ifdef CONFIG_DM_REGULATOR
  610. device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
  611. if (priv->vqmmc_dev)
  612. regulator_set_value(priv->vqmmc_dev, 3300000);
  613. #endif
  614. ret = mmc_of_parse(dev, &plat->cfg);
  615. if (ret < 0) {
  616. dev_err(dev, "failed to parse host caps\n");
  617. return ret;
  618. }
  619. plat->cfg.name = dev->name;
  620. plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  621. if (quirks)
  622. priv->caps = quirks;
  623. priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
  624. TMIO_SD_VERSION_IP;
  625. dev_dbg(dev, "version %x\n", priv->version);
  626. if (priv->version >= 0x10) {
  627. priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
  628. priv->caps |= TMIO_SD_CAP_DIV1024;
  629. }
  630. if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
  631. NULL))
  632. priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
  633. tmio_sd_host_init(priv);
  634. mclk = tmio_sd_clk_get_rate(priv);
  635. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  636. plat->cfg.f_min = mclk /
  637. (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
  638. plat->cfg.f_max = mclk;
  639. if (quirks & TMIO_SD_CAP_16BIT)
  640. plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
  641. else
  642. plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
  643. upriv->mmc = &plat->mmc;
  644. return 0;
  645. }