sh_mmcif.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MMCIF driver.
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <log.h>
  10. #include <watchdog.h>
  11. #include <command.h>
  12. #include <mmc.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <malloc.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/compat.h>
  21. #include <linux/io.h>
  22. #include <linux/sizes.h>
  23. #include "sh_mmcif.h"
  24. #define DRIVER_NAME "sh_mmcif"
  25. static int sh_mmcif_intr(void *dev_id)
  26. {
  27. struct sh_mmcif_host *host = dev_id;
  28. u32 state = 0;
  29. state = sh_mmcif_read(&host->regs->ce_int);
  30. state &= sh_mmcif_read(&host->regs->ce_int_mask);
  31. if (state & INT_RBSYE) {
  32. sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
  33. sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
  34. goto end;
  35. } else if (state & INT_CRSPE) {
  36. sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
  37. sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
  38. /* one more interrupt (INT_RBSYE) */
  39. if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
  40. return -EAGAIN;
  41. goto end;
  42. } else if (state & INT_BUFREN) {
  43. sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
  44. sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
  45. goto end;
  46. } else if (state & INT_BUFWEN) {
  47. sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
  48. sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
  49. goto end;
  50. } else if (state & INT_CMD12DRE) {
  51. sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
  52. INT_BUFRE), &host->regs->ce_int);
  53. sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
  54. goto end;
  55. } else if (state & INT_BUFRE) {
  56. sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
  57. sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
  58. goto end;
  59. } else if (state & INT_DTRANE) {
  60. sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
  61. sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
  62. goto end;
  63. } else if (state & INT_CMD12RBE) {
  64. sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
  65. &host->regs->ce_int);
  66. sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
  67. goto end;
  68. } else if (state & INT_ERR_STS) {
  69. /* err interrupts */
  70. sh_mmcif_write(~state, &host->regs->ce_int);
  71. sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
  72. goto err;
  73. } else
  74. return -EAGAIN;
  75. err:
  76. host->sd_error = 1;
  77. debug("%s: int err state = %08x\n", DRIVER_NAME, state);
  78. end:
  79. host->wait_int = 1;
  80. return 0;
  81. }
  82. static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
  83. {
  84. int timeout = 10000000;
  85. while (1) {
  86. timeout--;
  87. if (timeout < 0) {
  88. printf("timeout\n");
  89. return 0;
  90. }
  91. if (!sh_mmcif_intr(host))
  92. break;
  93. udelay(1); /* 1 usec */
  94. }
  95. return 1; /* Return value: NOT 0 = complete waiting */
  96. }
  97. static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
  98. {
  99. sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  100. sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
  101. if (!clk)
  102. return;
  103. if (clk == CLKDEV_EMMC_DATA)
  104. sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
  105. else
  106. sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
  107. clk) - 1) - 1) << 16,
  108. &host->regs->ce_clk_ctrl);
  109. sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  110. }
  111. static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
  112. {
  113. u32 tmp;
  114. tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
  115. CLK_CLEAR);
  116. sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
  117. sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
  118. sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
  119. &host->regs->ce_clk_ctrl);
  120. /* byte swap on */
  121. sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
  122. }
  123. static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
  124. {
  125. u32 state1, state2;
  126. int ret, timeout = 10000000;
  127. host->sd_error = 0;
  128. host->wait_int = 0;
  129. state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
  130. state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
  131. debug("%s: ERR HOST_STS1 = %08x\n", \
  132. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
  133. debug("%s: ERR HOST_STS2 = %08x\n", \
  134. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
  135. if (state1 & STS1_CMDSEQ) {
  136. debug("%s: Forced end of command sequence\n", DRIVER_NAME);
  137. sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  138. sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  139. while (1) {
  140. timeout--;
  141. if (timeout < 0) {
  142. printf(DRIVER_NAME": Forceed end of " \
  143. "command sequence timeout err\n");
  144. return -EILSEQ;
  145. }
  146. if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
  147. & STS1_CMDSEQ))
  148. break;
  149. }
  150. sh_mmcif_sync_reset(host);
  151. return -EILSEQ;
  152. }
  153. if (state2 & STS2_CRC_ERR)
  154. ret = -EILSEQ;
  155. else if (state2 & STS2_TIMEOUT_ERR)
  156. ret = -ETIMEDOUT;
  157. else
  158. ret = -EILSEQ;
  159. return ret;
  160. }
  161. static int sh_mmcif_single_read(struct sh_mmcif_host *host,
  162. struct mmc_data *data)
  163. {
  164. long time;
  165. u32 blocksize, i;
  166. unsigned long *p = (unsigned long *)data->dest;
  167. if ((unsigned long)p & 0x00000001) {
  168. printf("%s: The data pointer is unaligned.", __func__);
  169. return -EIO;
  170. }
  171. host->wait_int = 0;
  172. /* buf read enable */
  173. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  174. time = mmcif_wait_interrupt_flag(host);
  175. if (time == 0 || host->sd_error != 0)
  176. return sh_mmcif_error_manage(host);
  177. host->wait_int = 0;
  178. blocksize = (BLOCK_SIZE_MASK &
  179. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  180. for (i = 0; i < blocksize / 4; i++)
  181. *p++ = sh_mmcif_read(&host->regs->ce_data);
  182. /* buffer read end */
  183. sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
  184. time = mmcif_wait_interrupt_flag(host);
  185. if (time == 0 || host->sd_error != 0)
  186. return sh_mmcif_error_manage(host);
  187. host->wait_int = 0;
  188. return 0;
  189. }
  190. static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
  191. struct mmc_data *data)
  192. {
  193. long time;
  194. u32 blocksize, i, j;
  195. unsigned long *p = (unsigned long *)data->dest;
  196. if ((unsigned long)p & 0x00000001) {
  197. printf("%s: The data pointer is unaligned.", __func__);
  198. return -EIO;
  199. }
  200. host->wait_int = 0;
  201. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  202. for (j = 0; j < data->blocks; j++) {
  203. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  204. time = mmcif_wait_interrupt_flag(host);
  205. if (time == 0 || host->sd_error != 0)
  206. return sh_mmcif_error_manage(host);
  207. host->wait_int = 0;
  208. for (i = 0; i < blocksize / 4; i++)
  209. *p++ = sh_mmcif_read(&host->regs->ce_data);
  210. WATCHDOG_RESET();
  211. }
  212. return 0;
  213. }
  214. static int sh_mmcif_single_write(struct sh_mmcif_host *host,
  215. struct mmc_data *data)
  216. {
  217. long time;
  218. u32 blocksize, i;
  219. const unsigned long *p = (unsigned long *)data->dest;
  220. if ((unsigned long)p & 0x00000001) {
  221. printf("%s: The data pointer is unaligned.", __func__);
  222. return -EIO;
  223. }
  224. host->wait_int = 0;
  225. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  226. time = mmcif_wait_interrupt_flag(host);
  227. if (time == 0 || host->sd_error != 0)
  228. return sh_mmcif_error_manage(host);
  229. host->wait_int = 0;
  230. blocksize = (BLOCK_SIZE_MASK &
  231. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  232. for (i = 0; i < blocksize / 4; i++)
  233. sh_mmcif_write(*p++, &host->regs->ce_data);
  234. /* buffer write end */
  235. sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
  236. time = mmcif_wait_interrupt_flag(host);
  237. if (time == 0 || host->sd_error != 0)
  238. return sh_mmcif_error_manage(host);
  239. host->wait_int = 0;
  240. return 0;
  241. }
  242. static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
  243. struct mmc_data *data)
  244. {
  245. long time;
  246. u32 i, j, blocksize;
  247. const unsigned long *p = (unsigned long *)data->dest;
  248. if ((unsigned long)p & 0x00000001) {
  249. printf("%s: The data pointer is unaligned.", __func__);
  250. return -EIO;
  251. }
  252. host->wait_int = 0;
  253. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  254. for (j = 0; j < data->blocks; j++) {
  255. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  256. time = mmcif_wait_interrupt_flag(host);
  257. if (time == 0 || host->sd_error != 0)
  258. return sh_mmcif_error_manage(host);
  259. host->wait_int = 0;
  260. for (i = 0; i < blocksize / 4; i++)
  261. sh_mmcif_write(*p++, &host->regs->ce_data);
  262. WATCHDOG_RESET();
  263. }
  264. return 0;
  265. }
  266. static void sh_mmcif_get_response(struct sh_mmcif_host *host,
  267. struct mmc_cmd *cmd)
  268. {
  269. if (cmd->resp_type & MMC_RSP_136) {
  270. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
  271. cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
  272. cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
  273. cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
  274. debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
  275. cmd->response[1], cmd->response[2], cmd->response[3]);
  276. } else {
  277. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
  278. }
  279. }
  280. static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
  281. struct mmc_cmd *cmd)
  282. {
  283. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
  284. }
  285. static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
  286. struct mmc_data *data, struct mmc_cmd *cmd)
  287. {
  288. u32 tmp = 0;
  289. u32 opc = cmd->cmdidx;
  290. /* Response Type check */
  291. switch (cmd->resp_type) {
  292. case MMC_RSP_NONE:
  293. tmp |= CMD_SET_RTYP_NO;
  294. break;
  295. case MMC_RSP_R1:
  296. case MMC_RSP_R1b:
  297. case MMC_RSP_R3:
  298. tmp |= CMD_SET_RTYP_6B;
  299. break;
  300. case MMC_RSP_R2:
  301. tmp |= CMD_SET_RTYP_17B;
  302. break;
  303. default:
  304. printf(DRIVER_NAME": Not support type response.\n");
  305. break;
  306. }
  307. /* RBSY */
  308. if (opc == MMC_CMD_SWITCH)
  309. tmp |= CMD_SET_RBSY;
  310. /* WDAT / DATW */
  311. if (host->data) {
  312. tmp |= CMD_SET_WDAT;
  313. switch (host->bus_width) {
  314. case MMC_BUS_WIDTH_1:
  315. tmp |= CMD_SET_DATW_1;
  316. break;
  317. case MMC_BUS_WIDTH_4:
  318. tmp |= CMD_SET_DATW_4;
  319. break;
  320. case MMC_BUS_WIDTH_8:
  321. tmp |= CMD_SET_DATW_8;
  322. break;
  323. default:
  324. printf(DRIVER_NAME": Not support bus width.\n");
  325. break;
  326. }
  327. }
  328. /* DWEN */
  329. if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
  330. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
  331. tmp |= CMD_SET_DWEN;
  332. /* CMLTE/CMD12EN */
  333. if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
  334. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
  335. tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
  336. sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
  337. }
  338. /* RIDXC[1:0] check bits */
  339. if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
  340. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  341. tmp |= CMD_SET_RIDXC_BITS;
  342. /* RCRC7C[1:0] check bits */
  343. if (opc == MMC_CMD_SEND_OP_COND)
  344. tmp |= CMD_SET_CRC7C_BITS;
  345. /* RCRC7C[1:0] internal CRC7 */
  346. if (opc == MMC_CMD_ALL_SEND_CID ||
  347. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  348. tmp |= CMD_SET_CRC7C_INTERNAL;
  349. return opc = ((opc << 24) | tmp);
  350. }
  351. static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
  352. struct mmc_data *data, u16 opc)
  353. {
  354. u32 ret;
  355. switch (opc) {
  356. case MMC_CMD_READ_MULTIPLE_BLOCK:
  357. ret = sh_mmcif_multi_read(host, data);
  358. break;
  359. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  360. ret = sh_mmcif_multi_write(host, data);
  361. break;
  362. case MMC_CMD_WRITE_SINGLE_BLOCK:
  363. ret = sh_mmcif_single_write(host, data);
  364. break;
  365. case MMC_CMD_READ_SINGLE_BLOCK:
  366. case MMC_CMD_SEND_EXT_CSD:
  367. ret = sh_mmcif_single_read(host, data);
  368. break;
  369. default:
  370. printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
  371. ret = -EINVAL;
  372. break;
  373. }
  374. return ret;
  375. }
  376. static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
  377. struct mmc_data *data, struct mmc_cmd *cmd)
  378. {
  379. long time;
  380. int ret = 0, mask = 0;
  381. u32 opc = cmd->cmdidx;
  382. if (opc == MMC_CMD_STOP_TRANSMISSION) {
  383. /* MMCIF sends the STOP command automatically */
  384. if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
  385. sh_mmcif_bitset(MASK_MCMD12DRE,
  386. &host->regs->ce_int_mask);
  387. else
  388. sh_mmcif_bitset(MASK_MCMD12RBE,
  389. &host->regs->ce_int_mask);
  390. time = mmcif_wait_interrupt_flag(host);
  391. if (time == 0 || host->sd_error != 0)
  392. return sh_mmcif_error_manage(host);
  393. sh_mmcif_get_cmd12response(host, cmd);
  394. return 0;
  395. }
  396. if (opc == MMC_CMD_SWITCH)
  397. mask = MASK_MRBSYE;
  398. else
  399. mask = MASK_MCRSPE;
  400. mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
  401. MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
  402. MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
  403. MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
  404. if (host->data) {
  405. sh_mmcif_write(0, &host->regs->ce_block_set);
  406. sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
  407. }
  408. opc = sh_mmcif_set_cmd(host, data, cmd);
  409. sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
  410. sh_mmcif_write(mask, &host->regs->ce_int_mask);
  411. debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
  412. /* set arg */
  413. sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
  414. host->wait_int = 0;
  415. /* set cmd */
  416. sh_mmcif_write(opc, &host->regs->ce_cmd_set);
  417. time = mmcif_wait_interrupt_flag(host);
  418. if (time == 0)
  419. return sh_mmcif_error_manage(host);
  420. if (host->sd_error) {
  421. switch (cmd->cmdidx) {
  422. case MMC_CMD_ALL_SEND_CID:
  423. case MMC_CMD_SELECT_CARD:
  424. case MMC_CMD_APP_CMD:
  425. ret = -ETIMEDOUT;
  426. break;
  427. default:
  428. printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
  429. ret = sh_mmcif_error_manage(host);
  430. break;
  431. }
  432. host->sd_error = 0;
  433. host->wait_int = 0;
  434. return ret;
  435. }
  436. /* if no response */
  437. if (!(opc & 0x00C00000))
  438. return 0;
  439. if (host->wait_int == 1) {
  440. sh_mmcif_get_response(host, cmd);
  441. host->wait_int = 0;
  442. }
  443. if (host->data)
  444. ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
  445. host->last_cmd = cmd->cmdidx;
  446. return ret;
  447. }
  448. static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
  449. struct mmc_cmd *cmd, struct mmc_data *data)
  450. {
  451. int ret;
  452. WATCHDOG_RESET();
  453. switch (cmd->cmdidx) {
  454. case MMC_CMD_APP_CMD:
  455. return -ETIMEDOUT;
  456. case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
  457. if (data)
  458. /* ext_csd */
  459. break;
  460. else
  461. /* send_if_cond cmd (not support) */
  462. return -ETIMEDOUT;
  463. default:
  464. break;
  465. }
  466. host->sd_error = 0;
  467. host->data = data;
  468. ret = sh_mmcif_start_cmd(host, data, cmd);
  469. host->data = NULL;
  470. return ret;
  471. }
  472. static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
  473. {
  474. if (mmc->clock)
  475. sh_mmcif_clock_control(host, mmc->clock);
  476. if (mmc->bus_width == 8)
  477. host->bus_width = MMC_BUS_WIDTH_8;
  478. else if (mmc->bus_width == 4)
  479. host->bus_width = MMC_BUS_WIDTH_4;
  480. else
  481. host->bus_width = MMC_BUS_WIDTH_1;
  482. debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
  483. return 0;
  484. }
  485. static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
  486. {
  487. sh_mmcif_sync_reset(host);
  488. sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
  489. return 0;
  490. }
  491. #ifndef CONFIG_DM_MMC
  492. static void *mmc_priv(struct mmc *mmc)
  493. {
  494. return (void *)mmc->priv;
  495. }
  496. static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  497. struct mmc_data *data)
  498. {
  499. struct sh_mmcif_host *host = mmc_priv(mmc);
  500. return sh_mmcif_send_cmd_common(host, cmd, data);
  501. }
  502. static int sh_mmcif_set_ios(struct mmc *mmc)
  503. {
  504. struct sh_mmcif_host *host = mmc_priv(mmc);
  505. return sh_mmcif_set_ios_common(host, mmc);
  506. }
  507. static int sh_mmcif_initialize(struct mmc *mmc)
  508. {
  509. struct sh_mmcif_host *host = mmc_priv(mmc);
  510. return sh_mmcif_initialize_common(host);
  511. }
  512. static const struct mmc_ops sh_mmcif_ops = {
  513. .send_cmd = sh_mmcif_send_cmd,
  514. .set_ios = sh_mmcif_set_ios,
  515. .init = sh_mmcif_initialize,
  516. };
  517. static struct mmc_config sh_mmcif_cfg = {
  518. .name = DRIVER_NAME,
  519. .ops = &sh_mmcif_ops,
  520. .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
  521. MMC_MODE_8BIT,
  522. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  523. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  524. };
  525. int mmcif_mmc_init(void)
  526. {
  527. struct mmc *mmc;
  528. struct sh_mmcif_host *host = NULL;
  529. host = malloc(sizeof(struct sh_mmcif_host));
  530. if (!host)
  531. return -ENOMEM;
  532. memset(host, 0, sizeof(*host));
  533. host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
  534. host->clk = CONFIG_SH_MMCIF_CLK;
  535. sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  536. sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  537. mmc = mmc_create(&sh_mmcif_cfg, host);
  538. if (mmc == NULL) {
  539. free(host);
  540. return -ENOMEM;
  541. }
  542. return 0;
  543. }
  544. #else
  545. struct sh_mmcif_plat {
  546. struct mmc_config cfg;
  547. struct mmc mmc;
  548. };
  549. int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  550. struct mmc_data *data)
  551. {
  552. struct sh_mmcif_host *host = dev_get_priv(dev);
  553. return sh_mmcif_send_cmd_common(host, cmd, data);
  554. }
  555. int sh_mmcif_dm_set_ios(struct udevice *dev)
  556. {
  557. struct sh_mmcif_host *host = dev_get_priv(dev);
  558. struct mmc *mmc = mmc_get_mmc_dev(dev);
  559. return sh_mmcif_set_ios_common(host, mmc);
  560. }
  561. static const struct dm_mmc_ops sh_mmcif_dm_ops = {
  562. .send_cmd = sh_mmcif_dm_send_cmd,
  563. .set_ios = sh_mmcif_dm_set_ios,
  564. };
  565. static int sh_mmcif_dm_bind(struct udevice *dev)
  566. {
  567. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  568. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  569. }
  570. static int sh_mmcif_dm_probe(struct udevice *dev)
  571. {
  572. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  573. struct sh_mmcif_host *host = dev_get_priv(dev);
  574. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  575. struct clk sh_mmcif_clk;
  576. fdt_addr_t base;
  577. int ret;
  578. base = devfdt_get_addr(dev);
  579. if (base == FDT_ADDR_T_NONE)
  580. return -EINVAL;
  581. host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
  582. if (!host->regs)
  583. return -ENOMEM;
  584. ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
  585. if (ret) {
  586. debug("failed to get clock, ret=%d\n", ret);
  587. return ret;
  588. }
  589. ret = clk_enable(&sh_mmcif_clk);
  590. if (ret) {
  591. debug("failed to enable clock, ret=%d\n", ret);
  592. return ret;
  593. }
  594. host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
  595. plat->cfg.name = dev->name;
  596. plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  597. switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
  598. 1)) {
  599. case 8:
  600. plat->cfg.host_caps |= MMC_MODE_8BIT;
  601. break;
  602. case 4:
  603. plat->cfg.host_caps |= MMC_MODE_4BIT;
  604. break;
  605. case 1:
  606. break;
  607. default:
  608. dev_err(dev, "Invalid \"bus-width\" value\n");
  609. return -EINVAL;
  610. }
  611. sh_mmcif_initialize_common(host);
  612. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  613. plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  614. plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  615. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  616. upriv->mmc = &plat->mmc;
  617. return 0;
  618. }
  619. static const struct udevice_id sh_mmcif_sd_match[] = {
  620. { .compatible = "renesas,sh-mmcif" },
  621. { /* sentinel */ }
  622. };
  623. U_BOOT_DRIVER(sh_mmcif_mmc) = {
  624. .name = "sh-mmcif",
  625. .id = UCLASS_MMC,
  626. .of_match = sh_mmcif_sd_match,
  627. .bind = sh_mmcif_dm_bind,
  628. .probe = sh_mmcif_dm_probe,
  629. .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
  630. .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
  631. .ops = &sh_mmcif_dm_ops,
  632. };
  633. #endif