sdhci-cadence.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/device_compat.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bug.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/sizes.h>
  15. #include <linux/libfdt.h>
  16. #include <mmc.h>
  17. #include <sdhci.h>
  18. /* HRS - Host Register Set (specific to Cadence) */
  19. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  20. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  21. #define SDHCI_CDNS_HRS04_RD BIT(25)
  22. #define SDHCI_CDNS_HRS04_WR BIT(24)
  23. #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
  24. #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
  25. #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
  26. #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
  27. #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
  28. #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
  29. #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
  30. #define SDHCI_CDNS_HRS06_MODE_SD 0x0
  31. #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
  32. #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
  33. #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
  34. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
  35. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
  36. /* SRS - Slot Register Set (SDHCI-compatible) */
  37. #define SDHCI_CDNS_SRS_BASE 0x200
  38. /* PHY */
  39. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  40. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  41. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  42. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  43. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  44. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  45. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  46. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  47. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  48. #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
  49. #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
  50. #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
  51. /*
  52. * The tuned val register is 6 bit-wide, but not the whole of the range is
  53. * available. The range 0-42 seems to be available (then 43 wraps around to 0)
  54. * but I am not quite sure if it is official. Use only 0 to 39 for safety.
  55. */
  56. #define SDHCI_CDNS_MAX_TUNING_LOOP 40
  57. struct sdhci_cdns_plat {
  58. struct mmc_config cfg;
  59. struct mmc mmc;
  60. void __iomem *hrs_addr;
  61. };
  62. struct sdhci_cdns_phy_cfg {
  63. const char *property;
  64. u8 addr;
  65. };
  66. static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  67. { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  68. { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  69. { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  70. { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  71. { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  72. { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  73. { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  74. { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  75. { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  76. { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  77. { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  78. };
  79. static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  80. u8 addr, u8 data)
  81. {
  82. void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  83. u32 tmp;
  84. int ret;
  85. tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  86. FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  87. writel(tmp, reg);
  88. tmp |= SDHCI_CDNS_HRS04_WR;
  89. writel(tmp, reg);
  90. ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
  91. if (ret)
  92. return ret;
  93. tmp &= ~SDHCI_CDNS_HRS04_WR;
  94. writel(tmp, reg);
  95. return 0;
  96. }
  97. static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
  98. const void *fdt, int nodeoffset)
  99. {
  100. const fdt32_t *prop;
  101. int ret, i;
  102. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
  103. prop = fdt_getprop(fdt, nodeoffset,
  104. sdhci_cdns_phy_cfgs[i].property, NULL);
  105. if (!prop)
  106. continue;
  107. ret = sdhci_cdns_write_phy_reg(plat,
  108. sdhci_cdns_phy_cfgs[i].addr,
  109. fdt32_to_cpu(*prop));
  110. if (ret)
  111. return ret;
  112. }
  113. return 0;
  114. }
  115. static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
  116. {
  117. struct mmc *mmc = host->mmc;
  118. struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
  119. unsigned int clock = mmc->clock;
  120. u32 mode, tmp;
  121. /*
  122. * REVISIT:
  123. * The mode should be decided by MMC_TIMING_* like Linux, but
  124. * U-Boot does not support timing. Use the clock frequency instead.
  125. */
  126. if (clock <= 26000000) {
  127. mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
  128. } else if (clock <= 52000000) {
  129. if (mmc->ddr_mode)
  130. mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
  131. else
  132. mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
  133. } else {
  134. if (mmc->ddr_mode)
  135. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
  136. else
  137. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
  138. }
  139. tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
  140. tmp &= ~SDHCI_CDNS_HRS06_MODE;
  141. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
  142. writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
  143. }
  144. static const struct sdhci_ops sdhci_cdns_ops = {
  145. .set_control_reg = sdhci_cdns_set_control_reg,
  146. };
  147. static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
  148. unsigned int val)
  149. {
  150. void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
  151. u32 tmp;
  152. int i, ret;
  153. if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
  154. return -EINVAL;
  155. tmp = readl(reg);
  156. tmp &= ~SDHCI_CDNS_HRS06_TUNE;
  157. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
  158. /*
  159. * Workaround for IP errata:
  160. * The IP6116 SD/eMMC PHY design has a timing issue on receive data
  161. * path. Send tune request twice.
  162. */
  163. for (i = 0; i < 2; i++) {
  164. tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
  165. writel(tmp, reg);
  166. ret = readl_poll_timeout(reg, tmp,
  167. !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1);
  168. if (ret)
  169. return ret;
  170. }
  171. return 0;
  172. }
  173. static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
  174. unsigned int opcode)
  175. {
  176. struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
  177. struct mmc *mmc = &plat->mmc;
  178. int cur_streak = 0;
  179. int max_streak = 0;
  180. int end_of_streak = 0;
  181. int i;
  182. /*
  183. * This handler only implements the eMMC tuning that is specific to
  184. * this controller. The tuning for SD timing should be handled by the
  185. * SDHCI core.
  186. */
  187. if (!IS_MMC(mmc))
  188. return -ENOTSUPP;
  189. if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  190. return -EINVAL;
  191. for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
  192. if (sdhci_cdns_set_tune_val(plat, i) ||
  193. mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
  194. cur_streak = 0;
  195. } else { /* good */
  196. cur_streak++;
  197. if (cur_streak > max_streak) {
  198. max_streak = cur_streak;
  199. end_of_streak = i;
  200. }
  201. }
  202. }
  203. if (!max_streak) {
  204. dev_err(dev, "no tuning point found\n");
  205. return -EIO;
  206. }
  207. return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
  208. }
  209. static struct dm_mmc_ops sdhci_cdns_mmc_ops;
  210. static int sdhci_cdns_bind(struct udevice *dev)
  211. {
  212. struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
  213. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  214. }
  215. static int sdhci_cdns_probe(struct udevice *dev)
  216. {
  217. DECLARE_GLOBAL_DATA_PTR;
  218. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  219. struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
  220. struct sdhci_host *host = dev_get_priv(dev);
  221. fdt_addr_t base;
  222. int ret;
  223. base = devfdt_get_addr(dev);
  224. if (base == FDT_ADDR_T_NONE)
  225. return -EINVAL;
  226. plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
  227. if (!plat->hrs_addr)
  228. return -ENOMEM;
  229. host->name = dev->name;
  230. host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
  231. host->ops = &sdhci_cdns_ops;
  232. host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
  233. sdhci_cdns_mmc_ops = sdhci_ops;
  234. #ifdef MMC_SUPPORTS_TUNING
  235. sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
  236. #endif
  237. ret = mmc_of_parse(dev, &plat->cfg);
  238. if (ret)
  239. return ret;
  240. ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
  241. if (ret)
  242. return ret;
  243. host->mmc = &plat->mmc;
  244. host->mmc->dev = dev;
  245. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  246. if (ret)
  247. return ret;
  248. upriv->mmc = &plat->mmc;
  249. host->mmc->priv = host;
  250. return sdhci_probe(dev);
  251. }
  252. static const struct udevice_id sdhci_cdns_match[] = {
  253. { .compatible = "socionext,uniphier-sd4hc" },
  254. { .compatible = "cdns,sd4hc" },
  255. { /* sentinel */ }
  256. };
  257. U_BOOT_DRIVER(sdhci_cdns) = {
  258. .name = "sdhci-cdns",
  259. .id = UCLASS_MMC,
  260. .of_match = sdhci_cdns_match,
  261. .bind = sdhci_cdns_bind,
  262. .probe = sdhci_cdns_probe,
  263. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  264. .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
  265. .ops = &sdhci_cdns_mmc_ops,
  266. };