omap_hsmmc.c 51 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. * Sukumar Ghorai <s-ghorai@ti.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation's version 2 of
  12. * the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <config.h>
  25. #include <common.h>
  26. #include <cpu_func.h>
  27. #include <log.h>
  28. #include <malloc.h>
  29. #include <memalign.h>
  30. #include <mmc.h>
  31. #include <part.h>
  32. #include <i2c.h>
  33. #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  34. #include <palmas.h>
  35. #endif
  36. #include <asm/cache.h>
  37. #include <asm/io.h>
  38. #include <asm/arch/mmc_host_def.h>
  39. #ifdef CONFIG_OMAP54XX
  40. #include <asm/arch/mux_dra7xx.h>
  41. #include <asm/arch/dra7xx_iodelay.h>
  42. #endif
  43. #if !defined(CONFIG_SOC_KEYSTONE)
  44. #include <asm/gpio.h>
  45. #include <asm/arch/sys_proto.h>
  46. #endif
  47. #ifdef CONFIG_MMC_OMAP36XX_PINS
  48. #include <asm/arch/mux.h>
  49. #endif
  50. #include <dm.h>
  51. #include <dm/devres.h>
  52. #include <linux/bitops.h>
  53. #include <linux/delay.h>
  54. #include <linux/err.h>
  55. #include <power/regulator.h>
  56. #include <thermal.h>
  57. DECLARE_GLOBAL_DATA_PTR;
  58. /* simplify defines to OMAP_HSMMC_USE_GPIO */
  59. #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  60. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  61. #define OMAP_HSMMC_USE_GPIO
  62. #else
  63. #undef OMAP_HSMMC_USE_GPIO
  64. #endif
  65. /* common definitions for all OMAPs */
  66. #define SYSCTL_SRC (1 << 25)
  67. #define SYSCTL_SRD (1 << 26)
  68. #ifdef CONFIG_IODELAY_RECALIBRATION
  69. struct omap_hsmmc_pinctrl_state {
  70. struct pad_conf_entry *padconf;
  71. int npads;
  72. struct iodelay_cfg_entry *iodelay;
  73. int niodelays;
  74. };
  75. #endif
  76. struct omap_hsmmc_data {
  77. struct hsmmc *base_addr;
  78. #if !CONFIG_IS_ENABLED(DM_MMC)
  79. struct mmc_config cfg;
  80. #endif
  81. uint bus_width;
  82. uint clock;
  83. ushort last_cmd;
  84. #ifdef OMAP_HSMMC_USE_GPIO
  85. #if CONFIG_IS_ENABLED(DM_MMC)
  86. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  87. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  88. #else
  89. int cd_gpio;
  90. int wp_gpio;
  91. #endif
  92. #endif
  93. #if CONFIG_IS_ENABLED(DM_MMC)
  94. enum bus_mode mode;
  95. #endif
  96. u8 controller_flags;
  97. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  98. struct omap_hsmmc_adma_desc *adma_desc_table;
  99. uint desc_slot;
  100. #endif
  101. const char *hw_rev;
  102. struct udevice *pbias_supply;
  103. uint signal_voltage;
  104. #ifdef CONFIG_IODELAY_RECALIBRATION
  105. struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
  106. struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
  107. struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
  108. struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
  109. struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
  110. struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
  111. struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
  112. struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
  113. struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
  114. #endif
  115. };
  116. struct omap_mmc_of_data {
  117. u8 controller_flags;
  118. };
  119. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  120. struct omap_hsmmc_adma_desc {
  121. u8 attr;
  122. u8 reserved;
  123. u16 len;
  124. u32 addr;
  125. };
  126. #define ADMA_MAX_LEN 63488
  127. /* Decriptor table defines */
  128. #define ADMA_DESC_ATTR_VALID BIT(0)
  129. #define ADMA_DESC_ATTR_END BIT(1)
  130. #define ADMA_DESC_ATTR_INT BIT(2)
  131. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  132. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  133. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  134. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  135. #endif
  136. /* If we fail after 1 second wait, something is really bad */
  137. #define MAX_RETRY_MS 1000
  138. #define MMC_TIMEOUT_MS 20
  139. /* DMA transfers can take a long time if a lot a data is transferred.
  140. * The timeout must take in account the amount of data. Let's assume
  141. * that the time will never exceed 333 ms per MB (in other word we assume
  142. * that the bandwidth is always above 3MB/s).
  143. */
  144. #define DMA_TIMEOUT_PER_MB 333
  145. #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
  146. #define OMAP_HSMMC_NO_1_8_V BIT(1)
  147. #define OMAP_HSMMC_USE_ADMA BIT(2)
  148. #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
  149. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  150. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  151. unsigned int siz);
  152. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
  153. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
  154. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
  155. static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
  156. {
  157. #if CONFIG_IS_ENABLED(DM_MMC)
  158. return dev_get_priv(mmc->dev);
  159. #else
  160. return (struct omap_hsmmc_data *)mmc->priv;
  161. #endif
  162. }
  163. #if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
  164. static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
  165. {
  166. #if CONFIG_IS_ENABLED(DM_MMC)
  167. struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
  168. return &plat->cfg;
  169. #else
  170. return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
  171. #endif
  172. }
  173. #endif
  174. #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
  175. static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  176. {
  177. int ret;
  178. #if !CONFIG_IS_ENABLED(DM_GPIO)
  179. if (!gpio_is_valid(gpio))
  180. return -1;
  181. #endif
  182. ret = gpio_request(gpio, label);
  183. if (ret)
  184. return ret;
  185. ret = gpio_direction_input(gpio);
  186. if (ret)
  187. return ret;
  188. return gpio;
  189. }
  190. #endif
  191. static unsigned char mmc_board_init(struct mmc *mmc)
  192. {
  193. #if defined(CONFIG_OMAP34XX)
  194. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  195. t2_t *t2_base = (t2_t *)T2_BASE;
  196. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  197. u32 pbias_lite;
  198. #ifdef CONFIG_MMC_OMAP36XX_PINS
  199. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  200. #endif
  201. pbias_lite = readl(&t2_base->pbias_lite);
  202. pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
  203. #ifdef CONFIG_TARGET_OMAP3_CAIRO
  204. /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
  205. pbias_lite &= ~PBIASLITEVMODE0;
  206. #endif
  207. #ifdef CONFIG_TARGET_OMAP3_LOGIC
  208. /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
  209. pbias_lite &= ~PBIASLITEVMODE1;
  210. #endif
  211. #ifdef CONFIG_MMC_OMAP36XX_PINS
  212. if (get_cpu_family() == CPU_OMAP36XX) {
  213. /* Disable extended drain IO before changing PBIAS */
  214. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  215. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  216. }
  217. #endif
  218. writel(pbias_lite, &t2_base->pbias_lite);
  219. writel(pbias_lite | PBIASLITEPWRDNZ1 |
  220. PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  221. &t2_base->pbias_lite);
  222. #ifdef CONFIG_MMC_OMAP36XX_PINS
  223. if (get_cpu_family() == CPU_OMAP36XX)
  224. /* Enable extended drain IO after changing PBIAS */
  225. writel(wkup_ctrl |
  226. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  227. OMAP34XX_CTRL_WKUP_CTRL);
  228. #endif
  229. writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  230. &t2_base->devconf0);
  231. writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  232. &t2_base->devconf1);
  233. /* Change from default of 52MHz to 26MHz if necessary */
  234. if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
  235. writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
  236. &t2_base->ctl_prog_io1);
  237. writel(readl(&prcm_base->fclken1_core) |
  238. EN_MMC1 | EN_MMC2 | EN_MMC3,
  239. &prcm_base->fclken1_core);
  240. writel(readl(&prcm_base->iclken1_core) |
  241. EN_MMC1 | EN_MMC2 | EN_MMC3,
  242. &prcm_base->iclken1_core);
  243. #endif
  244. #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
  245. !CONFIG_IS_ENABLED(DM_REGULATOR)
  246. /* PBIAS config needed for MMC1 only */
  247. if (mmc_get_blk_desc(mmc)->devnum == 0)
  248. vmmc_pbias_config(LDO_VOLT_3V3);
  249. #endif
  250. return 0;
  251. }
  252. void mmc_init_stream(struct hsmmc *mmc_base)
  253. {
  254. ulong start;
  255. writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
  256. writel(MMC_CMD0, &mmc_base->cmd);
  257. start = get_timer(0);
  258. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  259. if (get_timer(0) - start > MAX_RETRY_MS) {
  260. printf("%s: timedout waiting for cc!\n", __func__);
  261. return;
  262. }
  263. }
  264. writel(CC_MASK, &mmc_base->stat)
  265. ;
  266. writel(MMC_CMD0, &mmc_base->cmd)
  267. ;
  268. start = get_timer(0);
  269. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  270. if (get_timer(0) - start > MAX_RETRY_MS) {
  271. printf("%s: timedout waiting for cc2!\n", __func__);
  272. return;
  273. }
  274. }
  275. writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
  276. }
  277. #if CONFIG_IS_ENABLED(DM_MMC)
  278. #ifdef CONFIG_IODELAY_RECALIBRATION
  279. static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
  280. {
  281. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  282. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  283. switch (priv->mode) {
  284. case MMC_HS_200:
  285. pinctrl_state = priv->hs200_1_8v_pinctrl_state;
  286. break;
  287. case UHS_SDR104:
  288. pinctrl_state = priv->sdr104_pinctrl_state;
  289. break;
  290. case UHS_SDR50:
  291. pinctrl_state = priv->sdr50_pinctrl_state;
  292. break;
  293. case UHS_DDR50:
  294. pinctrl_state = priv->ddr50_pinctrl_state;
  295. break;
  296. case UHS_SDR25:
  297. pinctrl_state = priv->sdr25_pinctrl_state;
  298. break;
  299. case UHS_SDR12:
  300. pinctrl_state = priv->sdr12_pinctrl_state;
  301. break;
  302. case SD_HS:
  303. case MMC_HS:
  304. case MMC_HS_52:
  305. pinctrl_state = priv->hs_pinctrl_state;
  306. break;
  307. case MMC_DDR_52:
  308. pinctrl_state = priv->ddr_1_8v_pinctrl_state;
  309. default:
  310. pinctrl_state = priv->default_pinctrl_state;
  311. break;
  312. }
  313. if (!pinctrl_state)
  314. pinctrl_state = priv->default_pinctrl_state;
  315. if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
  316. if (pinctrl_state->iodelay)
  317. late_recalibrate_iodelay(pinctrl_state->padconf,
  318. pinctrl_state->npads,
  319. pinctrl_state->iodelay,
  320. pinctrl_state->niodelays);
  321. else
  322. do_set_mux32((*ctrl)->control_padconf_core_base,
  323. pinctrl_state->padconf,
  324. pinctrl_state->npads);
  325. }
  326. }
  327. #endif
  328. static void omap_hsmmc_set_timing(struct mmc *mmc)
  329. {
  330. u32 val;
  331. struct hsmmc *mmc_base;
  332. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  333. mmc_base = priv->base_addr;
  334. omap_hsmmc_stop_clock(mmc_base);
  335. val = readl(&mmc_base->ac12);
  336. val &= ~AC12_UHSMC_MASK;
  337. priv->mode = mmc->selected_mode;
  338. if (mmc_is_mode_ddr(priv->mode))
  339. writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
  340. else
  341. writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
  342. switch (priv->mode) {
  343. case MMC_HS_200:
  344. case UHS_SDR104:
  345. val |= AC12_UHSMC_SDR104;
  346. break;
  347. case UHS_SDR50:
  348. val |= AC12_UHSMC_SDR50;
  349. break;
  350. case MMC_DDR_52:
  351. case UHS_DDR50:
  352. val |= AC12_UHSMC_DDR50;
  353. break;
  354. case SD_HS:
  355. case MMC_HS_52:
  356. case UHS_SDR25:
  357. val |= AC12_UHSMC_SDR25;
  358. break;
  359. case MMC_LEGACY:
  360. case MMC_HS:
  361. case UHS_SDR12:
  362. val |= AC12_UHSMC_SDR12;
  363. break;
  364. default:
  365. val |= AC12_UHSMC_RES;
  366. break;
  367. }
  368. writel(val, &mmc_base->ac12);
  369. #ifdef CONFIG_IODELAY_RECALIBRATION
  370. omap_hsmmc_io_recalibrate(mmc);
  371. #endif
  372. omap_hsmmc_start_clock(mmc_base);
  373. }
  374. static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
  375. {
  376. struct hsmmc *mmc_base;
  377. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  378. u32 hctl, ac12;
  379. mmc_base = priv->base_addr;
  380. hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
  381. ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
  382. switch (signal_voltage) {
  383. case MMC_SIGNAL_VOLTAGE_330:
  384. hctl |= SDVS_3V3;
  385. break;
  386. case MMC_SIGNAL_VOLTAGE_180:
  387. hctl |= SDVS_1V8;
  388. ac12 |= AC12_V1V8_SIGEN;
  389. break;
  390. }
  391. writel(hctl, &mmc_base->hctl);
  392. writel(ac12, &mmc_base->ac12);
  393. }
  394. static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
  395. {
  396. int ret = -ETIMEDOUT;
  397. u32 con;
  398. bool dat0_high;
  399. bool target_dat0_high = !!state;
  400. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  401. struct hsmmc *mmc_base = priv->base_addr;
  402. con = readl(&mmc_base->con);
  403. writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
  404. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  405. while (timeout_us--) {
  406. dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
  407. if (dat0_high == target_dat0_high) {
  408. ret = 0;
  409. break;
  410. }
  411. udelay(10);
  412. }
  413. writel(con, &mmc_base->con);
  414. return ret;
  415. }
  416. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  417. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  418. static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
  419. {
  420. int ret = 0;
  421. int uV = mV * 1000;
  422. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  423. if (!mmc->vqmmc_supply)
  424. return 0;
  425. /* Disable PBIAS */
  426. ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
  427. if (ret)
  428. return ret;
  429. /* Turn off IO voltage */
  430. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
  431. if (ret)
  432. return ret;
  433. /* Program a new IO voltage value */
  434. ret = regulator_set_value(mmc->vqmmc_supply, uV);
  435. if (ret)
  436. return ret;
  437. /* Turn on IO voltage */
  438. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
  439. if (ret)
  440. return ret;
  441. /* Program PBIAS voltage*/
  442. ret = regulator_set_value(priv->pbias_supply, uV);
  443. if (ret && ret != -ENOSYS)
  444. return ret;
  445. /* Enable PBIAS */
  446. ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
  447. if (ret)
  448. return ret;
  449. return 0;
  450. }
  451. #endif
  452. static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
  453. {
  454. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  455. struct hsmmc *mmc_base = priv->base_addr;
  456. int mv = mmc_voltage_to_mv(mmc->signal_voltage);
  457. u32 capa_mask;
  458. __maybe_unused u8 palmas_ldo_volt;
  459. u32 val;
  460. if (mv < 0)
  461. return -EINVAL;
  462. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  463. mv = 3300;
  464. capa_mask = VS33_3V3SUP;
  465. palmas_ldo_volt = LDO_VOLT_3V3;
  466. } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  467. capa_mask = VS18_1V8SUP;
  468. palmas_ldo_volt = LDO_VOLT_1V8;
  469. } else {
  470. return -EOPNOTSUPP;
  471. }
  472. val = readl(&mmc_base->capa);
  473. if (!(val & capa_mask))
  474. return -EOPNOTSUPP;
  475. priv->signal_voltage = mmc->signal_voltage;
  476. omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
  477. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  478. return omap_hsmmc_set_io_regulator(mmc, mv);
  479. #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
  480. defined(CONFIG_PALMAS_POWER)
  481. if (mmc_get_blk_desc(mmc)->devnum == 0)
  482. vmmc_pbias_config(palmas_ldo_volt);
  483. return 0;
  484. #else
  485. return 0;
  486. #endif
  487. }
  488. #endif
  489. static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
  490. {
  491. struct hsmmc *mmc_base;
  492. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  493. u32 val;
  494. mmc_base = priv->base_addr;
  495. val = readl(&mmc_base->capa);
  496. if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  497. val |= (VS33_3V3SUP | VS18_1V8SUP);
  498. } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
  499. val |= VS33_3V3SUP;
  500. val &= ~VS18_1V8SUP;
  501. } else {
  502. val |= VS18_1V8SUP;
  503. val &= ~VS33_3V3SUP;
  504. }
  505. writel(val, &mmc_base->capa);
  506. return val;
  507. }
  508. #ifdef MMC_SUPPORTS_TUNING
  509. static void omap_hsmmc_disable_tuning(struct mmc *mmc)
  510. {
  511. struct hsmmc *mmc_base;
  512. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  513. u32 val;
  514. mmc_base = priv->base_addr;
  515. val = readl(&mmc_base->ac12);
  516. val &= ~(AC12_SCLK_SEL);
  517. writel(val, &mmc_base->ac12);
  518. val = readl(&mmc_base->dll);
  519. val &= ~(DLL_FORCE_VALUE | DLL_SWT);
  520. writel(val, &mmc_base->dll);
  521. }
  522. static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
  523. {
  524. int i;
  525. struct hsmmc *mmc_base;
  526. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  527. u32 val;
  528. mmc_base = priv->base_addr;
  529. val = readl(&mmc_base->dll);
  530. val |= DLL_FORCE_VALUE;
  531. val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
  532. val |= (count << DLL_FORCE_SR_C_SHIFT);
  533. writel(val, &mmc_base->dll);
  534. val |= DLL_CALIB;
  535. writel(val, &mmc_base->dll);
  536. for (i = 0; i < 1000; i++) {
  537. if (readl(&mmc_base->dll) & DLL_CALIB)
  538. break;
  539. }
  540. val &= ~DLL_CALIB;
  541. writel(val, &mmc_base->dll);
  542. }
  543. static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
  544. {
  545. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  546. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  547. struct mmc *mmc = upriv->mmc;
  548. struct hsmmc *mmc_base;
  549. u32 val;
  550. u8 cur_match, prev_match = 0;
  551. int ret;
  552. u32 phase_delay = 0;
  553. u32 start_window = 0, max_window = 0;
  554. u32 length = 0, max_len = 0;
  555. bool single_point_failure = false;
  556. struct udevice *thermal_dev;
  557. int temperature;
  558. int i;
  559. mmc_base = priv->base_addr;
  560. val = readl(&mmc_base->capa2);
  561. /* clock tuning is not needed for upto 52MHz */
  562. if (!((mmc->selected_mode == MMC_HS_200) ||
  563. (mmc->selected_mode == UHS_SDR104) ||
  564. ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
  565. return 0;
  566. ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
  567. if (ret) {
  568. printf("Couldn't get thermal device for tuning\n");
  569. return ret;
  570. }
  571. ret = thermal_get_temp(thermal_dev, &temperature);
  572. if (ret) {
  573. printf("Couldn't get temperature for tuning\n");
  574. return ret;
  575. }
  576. val = readl(&mmc_base->dll);
  577. val |= DLL_SWT;
  578. writel(val, &mmc_base->dll);
  579. /*
  580. * Stage 1: Search for a maximum pass window ignoring any
  581. * any single point failures. If the tuning value ends up
  582. * near it, move away from it in stage 2 below
  583. */
  584. while (phase_delay <= MAX_PHASE_DELAY) {
  585. omap_hsmmc_set_dll(mmc, phase_delay);
  586. cur_match = !mmc_send_tuning(mmc, opcode, NULL);
  587. if (cur_match) {
  588. if (prev_match) {
  589. length++;
  590. } else if (single_point_failure) {
  591. /* ignore single point failure */
  592. length++;
  593. single_point_failure = false;
  594. } else {
  595. start_window = phase_delay;
  596. length = 1;
  597. }
  598. } else {
  599. single_point_failure = prev_match;
  600. }
  601. if (length > max_len) {
  602. max_window = start_window;
  603. max_len = length;
  604. }
  605. prev_match = cur_match;
  606. phase_delay += 4;
  607. }
  608. if (!max_len) {
  609. ret = -EIO;
  610. goto tuning_error;
  611. }
  612. val = readl(&mmc_base->ac12);
  613. if (!(val & AC12_SCLK_SEL)) {
  614. ret = -EIO;
  615. goto tuning_error;
  616. }
  617. /*
  618. * Assign tuning value as a ratio of maximum pass window based
  619. * on temperature
  620. */
  621. if (temperature < -20000)
  622. phase_delay = min(max_window + 4 * max_len - 24,
  623. max_window +
  624. DIV_ROUND_UP(13 * max_len, 16) * 4);
  625. else if (temperature < 20000)
  626. phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
  627. else if (temperature < 40000)
  628. phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
  629. else if (temperature < 70000)
  630. phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
  631. else if (temperature < 90000)
  632. phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
  633. else if (temperature < 120000)
  634. phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
  635. else
  636. phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
  637. /*
  638. * Stage 2: Search for a single point failure near the chosen tuning
  639. * value in two steps. First in the +3 to +10 range and then in the
  640. * +2 to -10 range. If found, move away from it in the appropriate
  641. * direction by the appropriate amount depending on the temperature.
  642. */
  643. for (i = 3; i <= 10; i++) {
  644. omap_hsmmc_set_dll(mmc, phase_delay + i);
  645. if (mmc_send_tuning(mmc, opcode, NULL)) {
  646. if (temperature < 10000)
  647. phase_delay += i + 6;
  648. else if (temperature < 20000)
  649. phase_delay += i - 12;
  650. else if (temperature < 70000)
  651. phase_delay += i - 8;
  652. else if (temperature < 90000)
  653. phase_delay += i - 6;
  654. else
  655. phase_delay += i - 6;
  656. goto single_failure_found;
  657. }
  658. }
  659. for (i = 2; i >= -10; i--) {
  660. omap_hsmmc_set_dll(mmc, phase_delay + i);
  661. if (mmc_send_tuning(mmc, opcode, NULL)) {
  662. if (temperature < 10000)
  663. phase_delay += i + 12;
  664. else if (temperature < 20000)
  665. phase_delay += i + 8;
  666. else if (temperature < 70000)
  667. phase_delay += i + 8;
  668. else if (temperature < 90000)
  669. phase_delay += i + 10;
  670. else
  671. phase_delay += i + 12;
  672. goto single_failure_found;
  673. }
  674. }
  675. single_failure_found:
  676. omap_hsmmc_set_dll(mmc, phase_delay);
  677. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  678. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  679. return 0;
  680. tuning_error:
  681. omap_hsmmc_disable_tuning(mmc);
  682. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  683. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  684. return ret;
  685. }
  686. #endif
  687. #endif
  688. static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
  689. {
  690. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  691. struct hsmmc *mmc_base = priv->base_addr;
  692. u32 irq_mask = INT_EN_MASK;
  693. /*
  694. * TODO: Errata i802 indicates only DCRC interrupts can occur during
  695. * tuning procedure and DCRC should be disabled. But see occurences
  696. * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
  697. * interrupts occur along with BRR, so the data is actually in the
  698. * buffer. It has to be debugged why these interrutps occur
  699. */
  700. if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
  701. irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
  702. writel(irq_mask, &mmc_base->ie);
  703. }
  704. static int omap_hsmmc_init_setup(struct mmc *mmc)
  705. {
  706. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  707. struct hsmmc *mmc_base;
  708. unsigned int reg_val;
  709. unsigned int dsor;
  710. ulong start;
  711. mmc_base = priv->base_addr;
  712. mmc_board_init(mmc);
  713. writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
  714. &mmc_base->sysconfig);
  715. start = get_timer(0);
  716. while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
  717. if (get_timer(0) - start > MAX_RETRY_MS) {
  718. printf("%s: timedout waiting for cc2!\n", __func__);
  719. return -ETIMEDOUT;
  720. }
  721. }
  722. writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
  723. start = get_timer(0);
  724. while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
  725. if (get_timer(0) - start > MAX_RETRY_MS) {
  726. printf("%s: timedout waiting for softresetall!\n",
  727. __func__);
  728. return -ETIMEDOUT;
  729. }
  730. }
  731. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  732. reg_val = readl(&mmc_base->hl_hwinfo);
  733. if (reg_val & MADMA_EN)
  734. priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
  735. #endif
  736. #if CONFIG_IS_ENABLED(DM_MMC)
  737. reg_val = omap_hsmmc_set_capabilities(mmc);
  738. omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
  739. MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
  740. #else
  741. writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, &mmc_base->hctl);
  742. writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
  743. &mmc_base->capa);
  744. #endif
  745. reg_val = readl(&mmc_base->con) & RESERVED_MASK;
  746. writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
  747. MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
  748. HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
  749. dsor = 240;
  750. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
  751. (ICE_STOP | DTO_15THDTO));
  752. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  753. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  754. start = get_timer(0);
  755. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  756. if (get_timer(0) - start > MAX_RETRY_MS) {
  757. printf("%s: timedout waiting for ics!\n", __func__);
  758. return -ETIMEDOUT;
  759. }
  760. }
  761. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  762. writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
  763. mmc_enable_irq(mmc, NULL);
  764. #if !CONFIG_IS_ENABLED(DM_MMC)
  765. mmc_init_stream(mmc_base);
  766. #endif
  767. return 0;
  768. }
  769. /*
  770. * MMC controller internal finite state machine reset
  771. *
  772. * Used to reset command or data internal state machines, using respectively
  773. * SRC or SRD bit of SYSCTL register
  774. */
  775. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
  776. {
  777. ulong start;
  778. mmc_reg_out(&mmc_base->sysctl, bit, bit);
  779. /*
  780. * CMD(DAT) lines reset procedures are slightly different
  781. * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
  782. * According to OMAP3 TRM:
  783. * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
  784. * returns to 0x0.
  785. * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
  786. * procedure steps must be as follows:
  787. * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
  788. * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
  789. * 2. Poll the SRC(SRD) bit until it is set to 0x1.
  790. * 3. Wait until the SRC (SRD) bit returns to 0x0
  791. * (reset procedure is completed).
  792. */
  793. #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  794. defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  795. if (!(readl(&mmc_base->sysctl) & bit)) {
  796. start = get_timer(0);
  797. while (!(readl(&mmc_base->sysctl) & bit)) {
  798. if (get_timer(0) - start > MMC_TIMEOUT_MS)
  799. return;
  800. }
  801. }
  802. #endif
  803. start = get_timer(0);
  804. while ((readl(&mmc_base->sysctl) & bit) != 0) {
  805. if (get_timer(0) - start > MAX_RETRY_MS) {
  806. printf("%s: timedout waiting for sysctl %x to clear\n",
  807. __func__, bit);
  808. return;
  809. }
  810. }
  811. }
  812. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  813. static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
  814. {
  815. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  816. struct omap_hsmmc_adma_desc *desc;
  817. u8 attr;
  818. desc = &priv->adma_desc_table[priv->desc_slot];
  819. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  820. if (!end)
  821. priv->desc_slot++;
  822. else
  823. attr |= ADMA_DESC_ATTR_END;
  824. desc->len = len;
  825. desc->addr = (u32)buf;
  826. desc->reserved = 0;
  827. desc->attr = attr;
  828. }
  829. static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
  830. struct mmc_data *data)
  831. {
  832. uint total_len = data->blocksize * data->blocks;
  833. uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
  834. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  835. int i = desc_count;
  836. char *buf;
  837. priv->desc_slot = 0;
  838. priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
  839. memalign(ARCH_DMA_MINALIGN, desc_count *
  840. sizeof(struct omap_hsmmc_adma_desc));
  841. if (data->flags & MMC_DATA_READ)
  842. buf = data->dest;
  843. else
  844. buf = (char *)data->src;
  845. while (--i) {
  846. omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
  847. buf += ADMA_MAX_LEN;
  848. total_len -= ADMA_MAX_LEN;
  849. }
  850. omap_hsmmc_adma_desc(mmc, buf, total_len, true);
  851. flush_dcache_range((long)priv->adma_desc_table,
  852. (long)priv->adma_desc_table +
  853. ROUND(desc_count *
  854. sizeof(struct omap_hsmmc_adma_desc),
  855. ARCH_DMA_MINALIGN));
  856. }
  857. static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
  858. {
  859. struct hsmmc *mmc_base;
  860. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  861. u32 val;
  862. char *buf;
  863. mmc_base = priv->base_addr;
  864. omap_hsmmc_prepare_adma_table(mmc, data);
  865. if (data->flags & MMC_DATA_READ)
  866. buf = data->dest;
  867. else
  868. buf = (char *)data->src;
  869. val = readl(&mmc_base->hctl);
  870. val |= DMA_SELECT;
  871. writel(val, &mmc_base->hctl);
  872. val = readl(&mmc_base->con);
  873. val |= DMA_MASTER;
  874. writel(val, &mmc_base->con);
  875. writel((u32)priv->adma_desc_table, &mmc_base->admasal);
  876. flush_dcache_range((u32)buf,
  877. (u32)buf +
  878. ROUND(data->blocksize * data->blocks,
  879. ARCH_DMA_MINALIGN));
  880. }
  881. static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
  882. {
  883. struct hsmmc *mmc_base;
  884. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  885. u32 val;
  886. mmc_base = priv->base_addr;
  887. val = readl(&mmc_base->con);
  888. val &= ~DMA_MASTER;
  889. writel(val, &mmc_base->con);
  890. val = readl(&mmc_base->hctl);
  891. val &= ~DMA_SELECT;
  892. writel(val, &mmc_base->hctl);
  893. kfree(priv->adma_desc_table);
  894. }
  895. #else
  896. #define omap_hsmmc_adma_desc
  897. #define omap_hsmmc_prepare_adma_table
  898. #define omap_hsmmc_prepare_data
  899. #define omap_hsmmc_dma_cleanup
  900. #endif
  901. #if !CONFIG_IS_ENABLED(DM_MMC)
  902. static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  903. struct mmc_data *data)
  904. {
  905. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  906. #else
  907. static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  908. struct mmc_data *data)
  909. {
  910. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  911. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  912. struct mmc *mmc = upriv->mmc;
  913. #endif
  914. struct hsmmc *mmc_base;
  915. unsigned int flags, mmc_stat;
  916. ulong start;
  917. priv->last_cmd = cmd->cmdidx;
  918. mmc_base = priv->base_addr;
  919. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  920. return 0;
  921. start = get_timer(0);
  922. while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
  923. if (get_timer(0) - start > MAX_RETRY_MS) {
  924. printf("%s: timedout waiting on cmd inhibit to clear\n",
  925. __func__);
  926. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  927. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  928. return -ETIMEDOUT;
  929. }
  930. }
  931. writel(0xFFFFFFFF, &mmc_base->stat);
  932. if (readl(&mmc_base->stat)) {
  933. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  934. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  935. }
  936. /*
  937. * CMDREG
  938. * CMDIDX[13:8] : Command index
  939. * DATAPRNT[5] : Data Present Select
  940. * ENCMDIDX[4] : Command Index Check Enable
  941. * ENCMDCRC[3] : Command CRC Check Enable
  942. * RSPTYP[1:0]
  943. * 00 = No Response
  944. * 01 = Length 136
  945. * 10 = Length 48
  946. * 11 = Length 48 Check busy after response
  947. */
  948. /* Delay added before checking the status of frq change
  949. * retry not supported by mmc.c(core file)
  950. */
  951. if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
  952. udelay(50000); /* wait 50 ms */
  953. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  954. flags = 0;
  955. else if (cmd->resp_type & MMC_RSP_136)
  956. flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
  957. else if (cmd->resp_type & MMC_RSP_BUSY)
  958. flags = RSP_TYPE_LGHT48B;
  959. else
  960. flags = RSP_TYPE_LGHT48;
  961. /* enable default flags */
  962. flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
  963. MSBS_SGLEBLK);
  964. flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
  965. if (cmd->resp_type & MMC_RSP_CRC)
  966. flags |= CCCE_CHECK;
  967. if (cmd->resp_type & MMC_RSP_OPCODE)
  968. flags |= CICE_CHECK;
  969. if (data) {
  970. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
  971. (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
  972. flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
  973. data->blocksize = 512;
  974. writel(data->blocksize | (data->blocks << 16),
  975. &mmc_base->blk);
  976. } else
  977. writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
  978. if (data->flags & MMC_DATA_READ)
  979. flags |= (DP_DATA | DDIR_READ);
  980. else
  981. flags |= (DP_DATA | DDIR_WRITE);
  982. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  983. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
  984. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  985. omap_hsmmc_prepare_data(mmc, data);
  986. flags |= DE_ENABLE;
  987. }
  988. #endif
  989. }
  990. mmc_enable_irq(mmc, cmd);
  991. writel(cmd->cmdarg, &mmc_base->arg);
  992. udelay(20); /* To fix "No status update" error on eMMC */
  993. writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
  994. start = get_timer(0);
  995. do {
  996. mmc_stat = readl(&mmc_base->stat);
  997. if (get_timer(start) > MAX_RETRY_MS) {
  998. printf("%s : timeout: No status update\n", __func__);
  999. return -ETIMEDOUT;
  1000. }
  1001. } while (!mmc_stat);
  1002. if ((mmc_stat & IE_CTO) != 0) {
  1003. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  1004. return -ETIMEDOUT;
  1005. } else if ((mmc_stat & ERRI_MASK) != 0)
  1006. return -1;
  1007. if (mmc_stat & CC_MASK) {
  1008. writel(CC_MASK, &mmc_base->stat);
  1009. if (cmd->resp_type & MMC_RSP_PRESENT) {
  1010. if (cmd->resp_type & MMC_RSP_136) {
  1011. /* response type 2 */
  1012. cmd->response[3] = readl(&mmc_base->rsp10);
  1013. cmd->response[2] = readl(&mmc_base->rsp32);
  1014. cmd->response[1] = readl(&mmc_base->rsp54);
  1015. cmd->response[0] = readl(&mmc_base->rsp76);
  1016. } else
  1017. /* response types 1, 1b, 3, 4, 5, 6 */
  1018. cmd->response[0] = readl(&mmc_base->rsp10);
  1019. }
  1020. }
  1021. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  1022. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
  1023. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  1024. u32 sz_mb, timeout;
  1025. if (mmc_stat & IE_ADMAE) {
  1026. omap_hsmmc_dma_cleanup(mmc);
  1027. return -EIO;
  1028. }
  1029. sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
  1030. timeout = sz_mb * DMA_TIMEOUT_PER_MB;
  1031. if (timeout < MAX_RETRY_MS)
  1032. timeout = MAX_RETRY_MS;
  1033. start = get_timer(0);
  1034. do {
  1035. mmc_stat = readl(&mmc_base->stat);
  1036. if (mmc_stat & TC_MASK) {
  1037. writel(readl(&mmc_base->stat) | TC_MASK,
  1038. &mmc_base->stat);
  1039. break;
  1040. }
  1041. if (get_timer(start) > timeout) {
  1042. printf("%s : DMA timeout: No status update\n",
  1043. __func__);
  1044. return -ETIMEDOUT;
  1045. }
  1046. } while (1);
  1047. omap_hsmmc_dma_cleanup(mmc);
  1048. return 0;
  1049. }
  1050. #endif
  1051. if (data && (data->flags & MMC_DATA_READ)) {
  1052. mmc_read_data(mmc_base, data->dest,
  1053. data->blocksize * data->blocks);
  1054. } else if (data && (data->flags & MMC_DATA_WRITE)) {
  1055. mmc_write_data(mmc_base, data->src,
  1056. data->blocksize * data->blocks);
  1057. }
  1058. return 0;
  1059. }
  1060. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
  1061. {
  1062. unsigned int *output_buf = (unsigned int *)buf;
  1063. unsigned int mmc_stat;
  1064. unsigned int count;
  1065. /*
  1066. * Start Polled Read
  1067. */
  1068. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1069. count /= 4;
  1070. while (size) {
  1071. ulong start = get_timer(0);
  1072. do {
  1073. mmc_stat = readl(&mmc_base->stat);
  1074. if (get_timer(0) - start > MAX_RETRY_MS) {
  1075. printf("%s: timedout waiting for status!\n",
  1076. __func__);
  1077. return -ETIMEDOUT;
  1078. }
  1079. } while (mmc_stat == 0);
  1080. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1081. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1082. if ((mmc_stat & ERRI_MASK) != 0)
  1083. return 1;
  1084. if (mmc_stat & BRR_MASK) {
  1085. unsigned int k;
  1086. writel(readl(&mmc_base->stat) | BRR_MASK,
  1087. &mmc_base->stat);
  1088. for (k = 0; k < count; k++) {
  1089. *output_buf = readl(&mmc_base->data);
  1090. output_buf++;
  1091. }
  1092. size -= (count*4);
  1093. }
  1094. if (mmc_stat & BWR_MASK)
  1095. writel(readl(&mmc_base->stat) | BWR_MASK,
  1096. &mmc_base->stat);
  1097. if (mmc_stat & TC_MASK) {
  1098. writel(readl(&mmc_base->stat) | TC_MASK,
  1099. &mmc_base->stat);
  1100. break;
  1101. }
  1102. }
  1103. return 0;
  1104. }
  1105. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1106. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1107. unsigned int size)
  1108. {
  1109. unsigned int *input_buf = (unsigned int *)buf;
  1110. unsigned int mmc_stat;
  1111. unsigned int count;
  1112. /*
  1113. * Start Polled Write
  1114. */
  1115. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1116. count /= 4;
  1117. while (size) {
  1118. ulong start = get_timer(0);
  1119. do {
  1120. mmc_stat = readl(&mmc_base->stat);
  1121. if (get_timer(0) - start > MAX_RETRY_MS) {
  1122. printf("%s: timedout waiting for status!\n",
  1123. __func__);
  1124. return -ETIMEDOUT;
  1125. }
  1126. } while (mmc_stat == 0);
  1127. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1128. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1129. if ((mmc_stat & ERRI_MASK) != 0)
  1130. return 1;
  1131. if (mmc_stat & BWR_MASK) {
  1132. unsigned int k;
  1133. writel(readl(&mmc_base->stat) | BWR_MASK,
  1134. &mmc_base->stat);
  1135. for (k = 0; k < count; k++) {
  1136. writel(*input_buf, &mmc_base->data);
  1137. input_buf++;
  1138. }
  1139. size -= (count*4);
  1140. }
  1141. if (mmc_stat & BRR_MASK)
  1142. writel(readl(&mmc_base->stat) | BRR_MASK,
  1143. &mmc_base->stat);
  1144. if (mmc_stat & TC_MASK) {
  1145. writel(readl(&mmc_base->stat) | TC_MASK,
  1146. &mmc_base->stat);
  1147. break;
  1148. }
  1149. }
  1150. return 0;
  1151. }
  1152. #else
  1153. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1154. unsigned int size)
  1155. {
  1156. return -ENOTSUPP;
  1157. }
  1158. #endif
  1159. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
  1160. {
  1161. writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
  1162. }
  1163. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
  1164. {
  1165. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  1166. }
  1167. static void omap_hsmmc_set_clock(struct mmc *mmc)
  1168. {
  1169. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1170. struct hsmmc *mmc_base;
  1171. unsigned int dsor = 0;
  1172. ulong start;
  1173. mmc_base = priv->base_addr;
  1174. omap_hsmmc_stop_clock(mmc_base);
  1175. /* TODO: Is setting DTO required here? */
  1176. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
  1177. (ICE_STOP | DTO_15THDTO));
  1178. if (mmc->clock != 0) {
  1179. dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
  1180. if (dsor > CLKD_MAX)
  1181. dsor = CLKD_MAX;
  1182. } else {
  1183. dsor = CLKD_MAX;
  1184. }
  1185. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  1186. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  1187. start = get_timer(0);
  1188. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  1189. if (get_timer(0) - start > MAX_RETRY_MS) {
  1190. printf("%s: timedout waiting for ics!\n", __func__);
  1191. return;
  1192. }
  1193. }
  1194. priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
  1195. mmc->clock = priv->clock;
  1196. omap_hsmmc_start_clock(mmc_base);
  1197. }
  1198. static void omap_hsmmc_set_bus_width(struct mmc *mmc)
  1199. {
  1200. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1201. struct hsmmc *mmc_base;
  1202. mmc_base = priv->base_addr;
  1203. /* configue bus width */
  1204. switch (mmc->bus_width) {
  1205. case 8:
  1206. writel(readl(&mmc_base->con) | DTW_8_BITMODE,
  1207. &mmc_base->con);
  1208. break;
  1209. case 4:
  1210. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1211. &mmc_base->con);
  1212. writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
  1213. &mmc_base->hctl);
  1214. break;
  1215. case 1:
  1216. default:
  1217. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1218. &mmc_base->con);
  1219. writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
  1220. &mmc_base->hctl);
  1221. break;
  1222. }
  1223. priv->bus_width = mmc->bus_width;
  1224. }
  1225. #if !CONFIG_IS_ENABLED(DM_MMC)
  1226. static int omap_hsmmc_set_ios(struct mmc *mmc)
  1227. {
  1228. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1229. #else
  1230. static int omap_hsmmc_set_ios(struct udevice *dev)
  1231. {
  1232. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1233. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1234. struct mmc *mmc = upriv->mmc;
  1235. #endif
  1236. struct hsmmc *mmc_base = priv->base_addr;
  1237. int ret = 0;
  1238. if (priv->bus_width != mmc->bus_width)
  1239. omap_hsmmc_set_bus_width(mmc);
  1240. if (priv->clock != mmc->clock)
  1241. omap_hsmmc_set_clock(mmc);
  1242. if (mmc->clk_disable)
  1243. omap_hsmmc_stop_clock(mmc_base);
  1244. else
  1245. omap_hsmmc_start_clock(mmc_base);
  1246. #if CONFIG_IS_ENABLED(DM_MMC)
  1247. if (priv->mode != mmc->selected_mode)
  1248. omap_hsmmc_set_timing(mmc);
  1249. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1250. if (priv->signal_voltage != mmc->signal_voltage)
  1251. ret = omap_hsmmc_set_signal_voltage(mmc);
  1252. #endif
  1253. #endif
  1254. return ret;
  1255. }
  1256. #ifdef OMAP_HSMMC_USE_GPIO
  1257. #if CONFIG_IS_ENABLED(DM_MMC)
  1258. static int omap_hsmmc_getcd(struct udevice *dev)
  1259. {
  1260. int value = -1;
  1261. #if CONFIG_IS_ENABLED(DM_GPIO)
  1262. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1263. value = dm_gpio_get_value(&priv->cd_gpio);
  1264. #endif
  1265. /* if no CD return as 1 */
  1266. if (value < 0)
  1267. return 1;
  1268. return value;
  1269. }
  1270. static int omap_hsmmc_getwp(struct udevice *dev)
  1271. {
  1272. int value = 0;
  1273. #if CONFIG_IS_ENABLED(DM_GPIO)
  1274. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1275. value = dm_gpio_get_value(&priv->wp_gpio);
  1276. #endif
  1277. /* if no WP return as 0 */
  1278. if (value < 0)
  1279. return 0;
  1280. return value;
  1281. }
  1282. #else
  1283. static int omap_hsmmc_getcd(struct mmc *mmc)
  1284. {
  1285. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1286. int cd_gpio;
  1287. /* if no CD return as 1 */
  1288. cd_gpio = priv->cd_gpio;
  1289. if (cd_gpio < 0)
  1290. return 1;
  1291. /* NOTE: assumes card detect signal is active-low */
  1292. return !gpio_get_value(cd_gpio);
  1293. }
  1294. static int omap_hsmmc_getwp(struct mmc *mmc)
  1295. {
  1296. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1297. int wp_gpio;
  1298. /* if no WP return as 0 */
  1299. wp_gpio = priv->wp_gpio;
  1300. if (wp_gpio < 0)
  1301. return 0;
  1302. /* NOTE: assumes write protect signal is active-high */
  1303. return gpio_get_value(wp_gpio);
  1304. }
  1305. #endif
  1306. #endif
  1307. #if CONFIG_IS_ENABLED(DM_MMC)
  1308. static const struct dm_mmc_ops omap_hsmmc_ops = {
  1309. .send_cmd = omap_hsmmc_send_cmd,
  1310. .set_ios = omap_hsmmc_set_ios,
  1311. #ifdef OMAP_HSMMC_USE_GPIO
  1312. .get_cd = omap_hsmmc_getcd,
  1313. .get_wp = omap_hsmmc_getwp,
  1314. #endif
  1315. #ifdef MMC_SUPPORTS_TUNING
  1316. .execute_tuning = omap_hsmmc_execute_tuning,
  1317. #endif
  1318. .wait_dat0 = omap_hsmmc_wait_dat0,
  1319. };
  1320. #else
  1321. static const struct mmc_ops omap_hsmmc_ops = {
  1322. .send_cmd = omap_hsmmc_send_cmd,
  1323. .set_ios = omap_hsmmc_set_ios,
  1324. .init = omap_hsmmc_init_setup,
  1325. #ifdef OMAP_HSMMC_USE_GPIO
  1326. .getcd = omap_hsmmc_getcd,
  1327. .getwp = omap_hsmmc_getwp,
  1328. #endif
  1329. };
  1330. #endif
  1331. #if !CONFIG_IS_ENABLED(DM_MMC)
  1332. int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
  1333. int wp_gpio)
  1334. {
  1335. struct mmc *mmc;
  1336. struct omap_hsmmc_data *priv;
  1337. struct mmc_config *cfg;
  1338. uint host_caps_val;
  1339. priv = calloc(1, sizeof(*priv));
  1340. if (priv == NULL)
  1341. return -1;
  1342. host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1343. switch (dev_index) {
  1344. case 0:
  1345. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1346. break;
  1347. #ifdef OMAP_HSMMC2_BASE
  1348. case 1:
  1349. priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
  1350. #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  1351. defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
  1352. defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
  1353. defined(CONFIG_HSMMC2_8BIT)
  1354. /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
  1355. host_caps_val |= MMC_MODE_8BIT;
  1356. #endif
  1357. break;
  1358. #endif
  1359. #ifdef OMAP_HSMMC3_BASE
  1360. case 2:
  1361. priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
  1362. #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
  1363. /* Enable 8-bit interface for eMMC on DRA7XX */
  1364. host_caps_val |= MMC_MODE_8BIT;
  1365. #endif
  1366. break;
  1367. #endif
  1368. default:
  1369. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1370. return 1;
  1371. }
  1372. #ifdef OMAP_HSMMC_USE_GPIO
  1373. /* on error gpio values are set to -1, which is what we want */
  1374. priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
  1375. priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
  1376. #endif
  1377. cfg = &priv->cfg;
  1378. cfg->name = "OMAP SD/MMC";
  1379. cfg->ops = &omap_hsmmc_ops;
  1380. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1381. cfg->host_caps = host_caps_val & ~host_caps_mask;
  1382. cfg->f_min = 400000;
  1383. if (f_max != 0)
  1384. cfg->f_max = f_max;
  1385. else {
  1386. if (cfg->host_caps & MMC_MODE_HS) {
  1387. if (cfg->host_caps & MMC_MODE_HS_52MHz)
  1388. cfg->f_max = 52000000;
  1389. else
  1390. cfg->f_max = 26000000;
  1391. } else
  1392. cfg->f_max = 20000000;
  1393. }
  1394. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1395. #if defined(CONFIG_OMAP34XX)
  1396. /*
  1397. * Silicon revs 2.1 and older do not support multiblock transfers.
  1398. */
  1399. if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
  1400. cfg->b_max = 1;
  1401. #endif
  1402. mmc = mmc_create(cfg, priv);
  1403. if (mmc == NULL)
  1404. return -1;
  1405. return 0;
  1406. }
  1407. #else
  1408. #ifdef CONFIG_IODELAY_RECALIBRATION
  1409. static struct pad_conf_entry *
  1410. omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
  1411. {
  1412. int index = 0;
  1413. struct pad_conf_entry *padconf;
  1414. padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
  1415. if (!padconf) {
  1416. debug("failed to allocate memory\n");
  1417. return 0;
  1418. }
  1419. while (index < count) {
  1420. padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
  1421. padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
  1422. index++;
  1423. }
  1424. return padconf;
  1425. }
  1426. static struct iodelay_cfg_entry *
  1427. omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
  1428. {
  1429. int index = 0;
  1430. struct iodelay_cfg_entry *iodelay;
  1431. iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
  1432. if (!iodelay) {
  1433. debug("failed to allocate memory\n");
  1434. return 0;
  1435. }
  1436. while (index < count) {
  1437. iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
  1438. iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
  1439. iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
  1440. index++;
  1441. }
  1442. return iodelay;
  1443. }
  1444. static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
  1445. const char *name, int *len)
  1446. {
  1447. const void *fdt = gd->fdt_blob;
  1448. int offset;
  1449. const fdt32_t *pinctrl;
  1450. offset = fdt_node_offset_by_phandle(fdt, phandle);
  1451. if (offset < 0) {
  1452. debug("failed to get pinctrl node %s.\n",
  1453. fdt_strerror(offset));
  1454. return 0;
  1455. }
  1456. pinctrl = fdt_getprop(fdt, offset, name, len);
  1457. if (!pinctrl) {
  1458. debug("failed to get property %s\n", name);
  1459. return 0;
  1460. }
  1461. return pinctrl;
  1462. }
  1463. static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
  1464. char *prop_name)
  1465. {
  1466. const void *fdt = gd->fdt_blob;
  1467. const __be32 *phandle;
  1468. int node = dev_of_offset(mmc->dev);
  1469. phandle = fdt_getprop(fdt, node, prop_name, NULL);
  1470. if (!phandle) {
  1471. debug("failed to get property %s\n", prop_name);
  1472. return 0;
  1473. }
  1474. return fdt32_to_cpu(*phandle);
  1475. }
  1476. static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
  1477. char *prop_name)
  1478. {
  1479. const void *fdt = gd->fdt_blob;
  1480. const __be32 *phandle;
  1481. int len;
  1482. int count;
  1483. int node = dev_of_offset(mmc->dev);
  1484. phandle = fdt_getprop(fdt, node, prop_name, &len);
  1485. if (!phandle) {
  1486. debug("failed to get property %s\n", prop_name);
  1487. return 0;
  1488. }
  1489. /* No manual mode iodelay values if count < 2 */
  1490. count = len / sizeof(*phandle);
  1491. if (count < 2)
  1492. return 0;
  1493. return fdt32_to_cpu(*(phandle + 1));
  1494. }
  1495. static struct pad_conf_entry *
  1496. omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
  1497. {
  1498. int len;
  1499. int count;
  1500. struct pad_conf_entry *padconf;
  1501. u32 phandle;
  1502. const fdt32_t *pinctrl;
  1503. phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
  1504. if (!phandle)
  1505. return ERR_PTR(-EINVAL);
  1506. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
  1507. &len);
  1508. if (!pinctrl)
  1509. return ERR_PTR(-EINVAL);
  1510. count = (len / sizeof(*pinctrl)) / 2;
  1511. padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
  1512. if (!padconf)
  1513. return ERR_PTR(-EINVAL);
  1514. *npads = count;
  1515. return padconf;
  1516. }
  1517. static struct iodelay_cfg_entry *
  1518. omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
  1519. {
  1520. int len;
  1521. int count;
  1522. struct iodelay_cfg_entry *iodelay;
  1523. u32 phandle;
  1524. const fdt32_t *pinctrl;
  1525. phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
  1526. /* Not all modes have manual mode iodelay values. So its not fatal */
  1527. if (!phandle)
  1528. return 0;
  1529. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
  1530. &len);
  1531. if (!pinctrl)
  1532. return ERR_PTR(-EINVAL);
  1533. count = (len / sizeof(*pinctrl)) / 3;
  1534. iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
  1535. if (!iodelay)
  1536. return ERR_PTR(-EINVAL);
  1537. *niodelay = count;
  1538. return iodelay;
  1539. }
  1540. static struct omap_hsmmc_pinctrl_state *
  1541. omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
  1542. {
  1543. int index;
  1544. int npads = 0;
  1545. int niodelays = 0;
  1546. const void *fdt = gd->fdt_blob;
  1547. int node = dev_of_offset(mmc->dev);
  1548. char prop_name[11];
  1549. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  1550. pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
  1551. malloc(sizeof(*pinctrl_state));
  1552. if (!pinctrl_state) {
  1553. debug("failed to allocate memory\n");
  1554. return 0;
  1555. }
  1556. index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
  1557. if (index < 0) {
  1558. debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
  1559. goto err_pinctrl_state;
  1560. }
  1561. sprintf(prop_name, "pinctrl-%d", index);
  1562. pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
  1563. &npads);
  1564. if (IS_ERR(pinctrl_state->padconf))
  1565. goto err_pinctrl_state;
  1566. pinctrl_state->npads = npads;
  1567. pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
  1568. &niodelays);
  1569. if (IS_ERR(pinctrl_state->iodelay))
  1570. goto err_padconf;
  1571. pinctrl_state->niodelays = niodelays;
  1572. return pinctrl_state;
  1573. err_padconf:
  1574. kfree(pinctrl_state->padconf);
  1575. err_pinctrl_state:
  1576. kfree(pinctrl_state);
  1577. return 0;
  1578. }
  1579. #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
  1580. do { \
  1581. struct omap_hsmmc_pinctrl_state *s = NULL; \
  1582. char str[20]; \
  1583. if (!(cfg->host_caps & capmask)) \
  1584. break; \
  1585. \
  1586. if (priv->hw_rev) { \
  1587. sprintf(str, "%s-%s", #mode, priv->hw_rev); \
  1588. s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
  1589. } \
  1590. \
  1591. if (!s) \
  1592. s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
  1593. \
  1594. if (!s && !optional) { \
  1595. debug("%s: no pinctrl for %s\n", \
  1596. mmc->dev->name, #mode); \
  1597. cfg->host_caps &= ~(capmask); \
  1598. } else { \
  1599. priv->mode##_pinctrl_state = s; \
  1600. } \
  1601. } while (0)
  1602. static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
  1603. {
  1604. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1605. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  1606. struct omap_hsmmc_pinctrl_state *default_pinctrl;
  1607. if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
  1608. return 0;
  1609. default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
  1610. if (!default_pinctrl) {
  1611. printf("no pinctrl state for default mode\n");
  1612. return -EINVAL;
  1613. }
  1614. priv->default_pinctrl_state = default_pinctrl;
  1615. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
  1616. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
  1617. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
  1618. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
  1619. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
  1620. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
  1621. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
  1622. OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
  1623. return 0;
  1624. }
  1625. #endif
  1626. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1627. #ifdef CONFIG_OMAP54XX
  1628. __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  1629. {
  1630. return NULL;
  1631. }
  1632. #endif
  1633. static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
  1634. {
  1635. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1636. struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
  1637. struct mmc_config *cfg = &plat->cfg;
  1638. #ifdef CONFIG_OMAP54XX
  1639. const struct mmc_platform_fixups *fixups;
  1640. #endif
  1641. const void *fdt = gd->fdt_blob;
  1642. int node = dev_of_offset(dev);
  1643. int ret;
  1644. plat->base_addr = map_physmem(devfdt_get_addr(dev),
  1645. sizeof(struct hsmmc *),
  1646. MAP_NOCACHE);
  1647. ret = mmc_of_parse(dev, cfg);
  1648. if (ret < 0)
  1649. return ret;
  1650. if (!cfg->f_max)
  1651. cfg->f_max = 52000000;
  1652. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1653. cfg->f_min = 400000;
  1654. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1655. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1656. if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
  1657. plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1658. if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
  1659. plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
  1660. if (of_data)
  1661. plat->controller_flags |= of_data->controller_flags;
  1662. #ifdef CONFIG_OMAP54XX
  1663. fixups = platform_fixups_mmc(devfdt_get_addr(dev));
  1664. if (fixups) {
  1665. plat->hw_rev = fixups->hw_rev;
  1666. cfg->host_caps &= ~fixups->unsupported_caps;
  1667. cfg->f_max = fixups->max_freq;
  1668. }
  1669. #endif
  1670. return 0;
  1671. }
  1672. #endif
  1673. #ifdef CONFIG_BLK
  1674. static int omap_hsmmc_bind(struct udevice *dev)
  1675. {
  1676. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1677. plat->mmc = calloc(1, sizeof(struct mmc));
  1678. return mmc_bind(dev, plat->mmc, &plat->cfg);
  1679. }
  1680. #endif
  1681. static int omap_hsmmc_probe(struct udevice *dev)
  1682. {
  1683. struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
  1684. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1685. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1686. struct mmc_config *cfg = &plat->cfg;
  1687. struct mmc *mmc;
  1688. #ifdef CONFIG_IODELAY_RECALIBRATION
  1689. int ret;
  1690. #endif
  1691. cfg->name = "OMAP SD/MMC";
  1692. priv->base_addr = plat->base_addr;
  1693. priv->controller_flags = plat->controller_flags;
  1694. priv->hw_rev = plat->hw_rev;
  1695. #ifdef CONFIG_BLK
  1696. mmc = plat->mmc;
  1697. #else
  1698. mmc = mmc_create(cfg, priv);
  1699. if (mmc == NULL)
  1700. return -1;
  1701. #endif
  1702. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1703. device_get_supply_regulator(dev, "pbias-supply",
  1704. &priv->pbias_supply);
  1705. #endif
  1706. #if defined(OMAP_HSMMC_USE_GPIO)
  1707. #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
  1708. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  1709. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  1710. #endif
  1711. #endif
  1712. mmc->dev = dev;
  1713. upriv->mmc = mmc;
  1714. #ifdef CONFIG_IODELAY_RECALIBRATION
  1715. ret = omap_hsmmc_get_pinctrl_state(mmc);
  1716. /*
  1717. * disable high speed modes for the platforms that require IO delay
  1718. * and for which we don't have this information
  1719. */
  1720. if ((ret < 0) &&
  1721. (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
  1722. priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
  1723. cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
  1724. UHS_CAPS);
  1725. }
  1726. #endif
  1727. return omap_hsmmc_init_setup(mmc);
  1728. }
  1729. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1730. static const struct omap_mmc_of_data dra7_mmc_of_data = {
  1731. .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
  1732. };
  1733. static const struct udevice_id omap_hsmmc_ids[] = {
  1734. { .compatible = "ti,omap3-hsmmc" },
  1735. { .compatible = "ti,omap4-hsmmc" },
  1736. { .compatible = "ti,am33xx-hsmmc" },
  1737. { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
  1738. { }
  1739. };
  1740. #endif
  1741. U_BOOT_DRIVER(omap_hsmmc) = {
  1742. .name = "omap_hsmmc",
  1743. .id = UCLASS_MMC,
  1744. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1745. .of_match = omap_hsmmc_ids,
  1746. .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
  1747. .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
  1748. #endif
  1749. #ifdef CONFIG_BLK
  1750. .bind = omap_hsmmc_bind,
  1751. #endif
  1752. .ops = &omap_hsmmc_ops,
  1753. .probe = omap_hsmmc_probe,
  1754. .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
  1755. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  1756. .flags = DM_FLAG_PRE_RELOC,
  1757. #endif
  1758. };
  1759. #endif