mxsmmc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 SSP MMC driver
  4. *
  5. * Copyright (C) 2019 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  9. * on behalf of DENX Software Engineering GmbH
  10. *
  11. * Based on code from LTIB:
  12. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  13. * Terry Lv
  14. *
  15. * Copyright 2007, Freescale Semiconductor, Inc
  16. * Andy Fleming
  17. *
  18. * Based vaguely on the pxa mmc code:
  19. * (C) Copyright 2003
  20. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  21. */
  22. #include <common.h>
  23. #include <log.h>
  24. #include <malloc.h>
  25. #include <mmc.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. #include <linux/errno.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/clock.h>
  31. #include <asm/arch/imx-regs.h>
  32. #include <asm/arch/sys_proto.h>
  33. #include <asm/mach-imx/dma.h>
  34. #include <bouncebuf.h>
  35. #define MXSMMC_MAX_TIMEOUT 10000
  36. #define MXSMMC_SMALL_TRANSFER 512
  37. #if !CONFIG_IS_ENABLED(DM_MMC)
  38. struct mxsmmc_priv {
  39. int id;
  40. int (*mmc_is_wp)(int);
  41. int (*mmc_cd)(int);
  42. struct mmc_config cfg; /* mmc configuration */
  43. struct mxs_dma_desc *desc;
  44. uint32_t buswidth;
  45. struct mxs_ssp_regs *regs;
  46. };
  47. #else /* CONFIG_IS_ENABLED(DM_MMC) */
  48. #include <dm/device.h>
  49. #include <dm/read.h>
  50. #include <dt-structs.h>
  51. #ifdef CONFIG_MX28
  52. #define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
  53. #else /* CONFIG_MX23 */
  54. #define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
  55. #endif
  56. struct mxsmmc_platdata {
  57. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  58. struct dtd_fsl_imx_mmc dtplat;
  59. #endif
  60. struct mmc_config cfg;
  61. struct mmc mmc;
  62. fdt_addr_t base;
  63. int non_removable;
  64. int buswidth;
  65. int dma_id;
  66. int clk_id;
  67. };
  68. struct mxsmmc_priv {
  69. int clkid;
  70. struct mxs_dma_desc *desc;
  71. u32 buswidth;
  72. struct mxs_ssp_regs *regs;
  73. unsigned int dma_channel;
  74. };
  75. #endif
  76. #if !CONFIG_IS_ENABLED(DM_MMC)
  77. static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  78. struct mmc_data *data);
  79. static int mxsmmc_cd(struct mxsmmc_priv *priv)
  80. {
  81. struct mxs_ssp_regs *ssp_regs = priv->regs;
  82. if (priv->mmc_cd)
  83. return priv->mmc_cd(priv->id);
  84. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  85. }
  86. static int mxsmmc_set_ios(struct mmc *mmc)
  87. {
  88. struct mxsmmc_priv *priv = mmc->priv;
  89. struct mxs_ssp_regs *ssp_regs = priv->regs;
  90. /* Set the clock speed */
  91. if (mmc->clock)
  92. mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
  93. switch (mmc->bus_width) {
  94. case 1:
  95. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  96. break;
  97. case 4:
  98. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  99. break;
  100. case 8:
  101. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  102. break;
  103. }
  104. /* Set the bus width */
  105. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  106. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  107. debug("MMC%d: Set %d bits bus width\n",
  108. mmc->block_dev.devnum, mmc->bus_width);
  109. return 0;
  110. }
  111. static int mxsmmc_init(struct mmc *mmc)
  112. {
  113. struct mxsmmc_priv *priv = mmc->priv;
  114. struct mxs_ssp_regs *ssp_regs = priv->regs;
  115. /* Reset SSP */
  116. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  117. /* Reconfigure the SSP block for MMC operation */
  118. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  119. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  120. SSP_CTRL1_DMA_ENABLE |
  121. SSP_CTRL1_POLARITY |
  122. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  123. SSP_CTRL1_DATA_CRC_IRQ_EN |
  124. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  125. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  126. SSP_CTRL1_RESP_ERR_IRQ_EN,
  127. &ssp_regs->hw_ssp_ctrl1_set);
  128. /* Set initial bit clock 400 KHz */
  129. mxs_set_ssp_busclock(priv->id, 400);
  130. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  131. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  132. udelay(200);
  133. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  134. return 0;
  135. }
  136. static const struct mmc_ops mxsmmc_ops = {
  137. .send_cmd = mxsmmc_send_cmd,
  138. .set_ios = mxsmmc_set_ios,
  139. .init = mxsmmc_init,
  140. };
  141. int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
  142. {
  143. struct mmc *mmc = NULL;
  144. struct mxsmmc_priv *priv = NULL;
  145. int ret;
  146. const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
  147. if (!mxs_ssp_bus_id_valid(id))
  148. return -ENODEV;
  149. priv = malloc(sizeof(struct mxsmmc_priv));
  150. if (!priv)
  151. return -ENOMEM;
  152. priv->desc = mxs_dma_desc_alloc();
  153. if (!priv->desc) {
  154. free(priv);
  155. return -ENOMEM;
  156. }
  157. ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
  158. if (ret)
  159. return ret;
  160. priv->mmc_is_wp = wp;
  161. priv->mmc_cd = cd;
  162. priv->id = id;
  163. priv->regs = mxs_ssp_regs_by_bus(id);
  164. priv->cfg.name = "MXS MMC";
  165. priv->cfg.ops = &mxsmmc_ops;
  166. priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  167. priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  168. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  169. /*
  170. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  171. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  172. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  173. * CLOCK_RATE could be any integer from 0 to 255.
  174. */
  175. priv->cfg.f_min = 400000;
  176. priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
  177. * 1000 / 2;
  178. priv->cfg.b_max = 0x20;
  179. mmc = mmc_create(&priv->cfg, priv);
  180. if (!mmc) {
  181. mxs_dma_desc_free(priv->desc);
  182. free(priv);
  183. return -ENOMEM;
  184. }
  185. return 0;
  186. }
  187. #endif /* CONFIG_IS_ENABLED(DM_MMC) */
  188. static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  189. {
  190. struct mxs_ssp_regs *ssp_regs = priv->regs;
  191. uint32_t *data_ptr;
  192. int timeout = MXSMMC_MAX_TIMEOUT;
  193. uint32_t reg;
  194. uint32_t data_count = data->blocksize * data->blocks;
  195. if (data->flags & MMC_DATA_READ) {
  196. data_ptr = (uint32_t *)data->dest;
  197. while (data_count && --timeout) {
  198. reg = readl(&ssp_regs->hw_ssp_status);
  199. if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  200. *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  201. data_count -= 4;
  202. timeout = MXSMMC_MAX_TIMEOUT;
  203. } else
  204. udelay(1000);
  205. }
  206. } else {
  207. data_ptr = (uint32_t *)data->src;
  208. timeout *= 100;
  209. while (data_count && --timeout) {
  210. reg = readl(&ssp_regs->hw_ssp_status);
  211. if (!(reg & SSP_STATUS_FIFO_FULL)) {
  212. writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  213. data_count -= 4;
  214. timeout = MXSMMC_MAX_TIMEOUT;
  215. } else
  216. udelay(1000);
  217. }
  218. }
  219. return timeout ? 0 : -ECOMM;
  220. }
  221. static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  222. {
  223. uint32_t data_count = data->blocksize * data->blocks;
  224. int dmach;
  225. struct mxs_dma_desc *desc = priv->desc;
  226. void *addr;
  227. unsigned int flags;
  228. struct bounce_buffer bbstate;
  229. memset(desc, 0, sizeof(struct mxs_dma_desc));
  230. desc->address = (dma_addr_t)desc;
  231. if (data->flags & MMC_DATA_READ) {
  232. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  233. addr = data->dest;
  234. flags = GEN_BB_WRITE;
  235. } else {
  236. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  237. addr = (void *)data->src;
  238. flags = GEN_BB_READ;
  239. }
  240. bounce_buffer_start(&bbstate, addr, data_count, flags);
  241. priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
  242. priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
  243. (data_count << MXS_DMA_DESC_BYTES_OFFSET);
  244. #if !CONFIG_IS_ENABLED(DM_MMC)
  245. dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
  246. #else
  247. dmach = priv->dma_channel;
  248. #endif
  249. mxs_dma_desc_append(dmach, priv->desc);
  250. if (mxs_dma_go(dmach)) {
  251. bounce_buffer_stop(&bbstate);
  252. return -ECOMM;
  253. }
  254. bounce_buffer_stop(&bbstate);
  255. return 0;
  256. }
  257. #if !CONFIG_IS_ENABLED(DM_MMC)
  258. /*
  259. * Sends a command out on the bus. Takes the mmc pointer,
  260. * a command pointer, and an optional data pointer.
  261. */
  262. static int
  263. mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  264. {
  265. struct mxsmmc_priv *priv = mmc->priv;
  266. struct mxs_ssp_regs *ssp_regs = priv->regs;
  267. #else
  268. static int
  269. mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
  270. {
  271. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  272. struct mxsmmc_priv *priv = dev_get_priv(dev);
  273. struct mxs_ssp_regs *ssp_regs = priv->regs;
  274. struct mmc *mmc = &plat->mmc;
  275. #endif
  276. uint32_t reg;
  277. int timeout;
  278. uint32_t ctrl0;
  279. int ret;
  280. #if !CONFIG_IS_ENABLED(DM_MMC)
  281. int devnum = mmc->block_dev.devnum;
  282. #else
  283. int devnum = mmc_get_blk_desc(mmc)->devnum;
  284. #endif
  285. debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
  286. /* Check bus busy */
  287. timeout = MXSMMC_MAX_TIMEOUT;
  288. while (--timeout) {
  289. udelay(1000);
  290. reg = readl(&ssp_regs->hw_ssp_status);
  291. if (!(reg &
  292. (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
  293. SSP_STATUS_CMD_BUSY))) {
  294. break;
  295. }
  296. }
  297. if (!timeout) {
  298. printf("MMC%d: Bus busy timeout!\n", devnum);
  299. return -ETIMEDOUT;
  300. }
  301. #if !CONFIG_IS_ENABLED(DM_MMC)
  302. /* See if card is present */
  303. if (!mxsmmc_cd(priv)) {
  304. printf("MMC%d: No card detected!\n", devnum);
  305. return -ENOMEDIUM;
  306. }
  307. #endif
  308. /* Start building CTRL0 contents */
  309. ctrl0 = priv->buswidth;
  310. /* Set up command */
  311. if (!(cmd->resp_type & MMC_RSP_CRC))
  312. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  313. if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
  314. ctrl0 |= SSP_CTRL0_GET_RESP;
  315. if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
  316. ctrl0 |= SSP_CTRL0_LONG_RESP;
  317. if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
  318. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  319. else
  320. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  321. /* Command index */
  322. reg = readl(&ssp_regs->hw_ssp_cmd0);
  323. reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
  324. reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
  325. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  326. reg |= SSP_CMD0_APPEND_8CYC;
  327. writel(reg, &ssp_regs->hw_ssp_cmd0);
  328. /* Command argument */
  329. writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
  330. /* Set up data */
  331. if (data) {
  332. /* READ or WRITE */
  333. if (data->flags & MMC_DATA_READ) {
  334. ctrl0 |= SSP_CTRL0_READ;
  335. #if !CONFIG_IS_ENABLED(DM_MMC)
  336. } else if (priv->mmc_is_wp &&
  337. priv->mmc_is_wp(devnum)) {
  338. printf("MMC%d: Can not write a locked card!\n", devnum);
  339. return -EOPNOTSUPP;
  340. #endif
  341. }
  342. ctrl0 |= SSP_CTRL0_DATA_XFER;
  343. reg = data->blocksize * data->blocks;
  344. #if defined(CONFIG_MX23)
  345. ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
  346. clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
  347. SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
  348. ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
  349. ((ffs(data->blocksize) - 1) <<
  350. SSP_CMD0_BLOCK_SIZE_OFFSET));
  351. #elif defined(CONFIG_MX28)
  352. writel(reg, &ssp_regs->hw_ssp_xfer_size);
  353. reg = ((data->blocks - 1) <<
  354. SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
  355. ((ffs(data->blocksize) - 1) <<
  356. SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
  357. writel(reg, &ssp_regs->hw_ssp_block_size);
  358. #endif
  359. }
  360. /* Kick off the command */
  361. ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
  362. writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
  363. /* Wait for the command to complete */
  364. timeout = MXSMMC_MAX_TIMEOUT;
  365. while (--timeout) {
  366. udelay(1000);
  367. reg = readl(&ssp_regs->hw_ssp_status);
  368. if (!(reg & SSP_STATUS_CMD_BUSY))
  369. break;
  370. }
  371. if (!timeout) {
  372. printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
  373. return -ETIMEDOUT;
  374. }
  375. /* Check command timeout */
  376. if (reg & SSP_STATUS_RESP_TIMEOUT) {
  377. debug("MMC%d: Command %d timeout (status 0x%08x)\n",
  378. devnum, cmd->cmdidx, reg);
  379. return -ETIMEDOUT;
  380. }
  381. /* Check command errors */
  382. if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
  383. printf("MMC%d: Command %d error (status 0x%08x)!\n",
  384. devnum, cmd->cmdidx, reg);
  385. return -ECOMM;
  386. }
  387. /* Copy response to response buffer */
  388. if (cmd->resp_type & MMC_RSP_136) {
  389. cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
  390. cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
  391. cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
  392. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
  393. } else
  394. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
  395. /* Return if no data to process */
  396. if (!data)
  397. return 0;
  398. if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
  399. ret = mxsmmc_send_cmd_pio(priv, data);
  400. if (ret) {
  401. printf("MMC%d: Data timeout with command %d "
  402. "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
  403. return ret;
  404. }
  405. } else {
  406. ret = mxsmmc_send_cmd_dma(priv, data);
  407. if (ret) {
  408. printf("MMC%d: DMA transfer failed\n", devnum);
  409. return ret;
  410. }
  411. }
  412. /* Check data errors */
  413. reg = readl(&ssp_regs->hw_ssp_status);
  414. if (reg &
  415. (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
  416. SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
  417. printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
  418. devnum, cmd->cmdidx, reg);
  419. return -ECOMM;
  420. }
  421. return 0;
  422. }
  423. #if CONFIG_IS_ENABLED(DM_MMC)
  424. /* Base numbers of i.MX2[38] clk for ssp0 IP block */
  425. #define MXS_SSP_IMX23_CLKID_SSP0 33
  426. #define MXS_SSP_IMX28_CLKID_SSP0 46
  427. static int mxsmmc_get_cd(struct udevice *dev)
  428. {
  429. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  430. struct mxsmmc_priv *priv = dev_get_priv(dev);
  431. struct mxs_ssp_regs *ssp_regs = priv->regs;
  432. if (plat->non_removable)
  433. return 1;
  434. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  435. }
  436. static int mxsmmc_set_ios(struct udevice *dev)
  437. {
  438. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  439. struct mxsmmc_priv *priv = dev_get_priv(dev);
  440. struct mxs_ssp_regs *ssp_regs = priv->regs;
  441. struct mmc *mmc = &plat->mmc;
  442. /* Set the clock speed */
  443. if (mmc->clock)
  444. mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
  445. switch (mmc->bus_width) {
  446. case 1:
  447. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  448. break;
  449. case 4:
  450. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  451. break;
  452. case 8:
  453. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  454. break;
  455. }
  456. /* Set the bus width */
  457. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  458. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  459. debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
  460. mmc->bus_width);
  461. return 0;
  462. }
  463. static int mxsmmc_init(struct udevice *dev)
  464. {
  465. struct mxsmmc_priv *priv = dev_get_priv(dev);
  466. struct mxs_ssp_regs *ssp_regs = priv->regs;
  467. /* Reset SSP */
  468. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  469. /* Reconfigure the SSP block for MMC operation */
  470. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  471. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  472. SSP_CTRL1_DMA_ENABLE |
  473. SSP_CTRL1_POLARITY |
  474. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  475. SSP_CTRL1_DATA_CRC_IRQ_EN |
  476. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  477. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  478. SSP_CTRL1_RESP_ERR_IRQ_EN,
  479. &ssp_regs->hw_ssp_ctrl1_set);
  480. /* Set initial bit clock 400 KHz */
  481. mxs_set_ssp_busclock(priv->clkid, 400);
  482. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  483. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  484. udelay(200);
  485. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  486. return 0;
  487. }
  488. static int mxsmmc_probe(struct udevice *dev)
  489. {
  490. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  491. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  492. struct mxsmmc_priv *priv = dev_get_priv(dev);
  493. struct blk_desc *bdesc;
  494. struct mmc *mmc;
  495. int ret, clkid;
  496. debug("%s: probe\n", __func__);
  497. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  498. struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
  499. struct phandle_1_arg *p1a = &dtplat->clocks[0];
  500. priv->buswidth = dtplat->bus_width;
  501. priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
  502. priv->dma_channel = dtplat->dmas[1];
  503. clkid = p1a->arg[0];
  504. plat->non_removable = dtplat->non_removable;
  505. debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
  506. priv->regs, priv->buswidth, clkid, plat->non_removable);
  507. #else
  508. priv->regs = (struct mxs_ssp_regs *)plat->base;
  509. priv->dma_channel = plat->dma_id;
  510. clkid = plat->clk_id;
  511. #endif
  512. #ifdef CONFIG_MX28
  513. priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
  514. #else /* CONFIG_MX23 */
  515. priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
  516. #endif
  517. mmc = &plat->mmc;
  518. mmc->cfg = &plat->cfg;
  519. mmc->dev = dev;
  520. priv->desc = mxs_dma_desc_alloc();
  521. if (!priv->desc) {
  522. printf("%s: Cannot allocate DMA descriptor\n", __func__);
  523. return -ENOMEM;
  524. }
  525. ret = mxs_dma_init_channel(priv->dma_channel);
  526. if (ret)
  527. return ret;
  528. plat->cfg.name = "MXS MMC";
  529. plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  530. plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  531. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  532. /*
  533. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  534. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  535. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  536. * CLOCK_RATE could be any integer from 0 to 255.
  537. */
  538. plat->cfg.f_min = 400000;
  539. plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
  540. plat->cfg.b_max = 0x20;
  541. bdesc = mmc_get_blk_desc(mmc);
  542. if (!bdesc) {
  543. printf("%s: No block device descriptor!\n", __func__);
  544. return -ENODEV;
  545. }
  546. if (plat->non_removable)
  547. bdesc->removable = 0;
  548. ret = mxsmmc_init(dev);
  549. if (ret)
  550. printf("%s: MMC%d init error %d\n", __func__,
  551. bdesc->devnum, ret);
  552. /* Set the initial clock speed */
  553. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  554. upriv->mmc = mmc;
  555. return 0;
  556. };
  557. #if CONFIG_IS_ENABLED(BLK)
  558. static int mxsmmc_bind(struct udevice *dev)
  559. {
  560. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  561. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  562. }
  563. #endif
  564. static const struct dm_mmc_ops mxsmmc_ops = {
  565. .get_cd = mxsmmc_get_cd,
  566. .send_cmd = mxsmmc_send_cmd,
  567. .set_ios = mxsmmc_set_ios,
  568. };
  569. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  570. static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
  571. {
  572. struct mxsmmc_platdata *plat = bus->platdata;
  573. u32 prop[2];
  574. int ret;
  575. plat->base = dev_read_addr(bus);
  576. plat->buswidth =
  577. dev_read_u32_default(bus, "bus-width", 1);
  578. plat->non_removable = dev_read_bool(bus, "non-removable");
  579. ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
  580. if (ret) {
  581. printf("%s: Reading 'dmas' property failed!\n", __func__);
  582. return ret;
  583. }
  584. plat->dma_id = prop[1];
  585. ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
  586. if (ret) {
  587. printf("%s: Reading 'clocks' property failed!\n", __func__);
  588. return ret;
  589. }
  590. plat->clk_id = prop[1];
  591. debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
  592. __func__, (uint)plat->base, plat->buswidth,
  593. plat->non_removable ? "non-removable" : NULL,
  594. plat->dma_id, plat->clk_id);
  595. return 0;
  596. }
  597. static const struct udevice_id mxsmmc_ids[] = {
  598. { .compatible = "fsl,imx23-mmc", },
  599. { .compatible = "fsl,imx28-mmc", },
  600. { /* sentinel */ }
  601. };
  602. #endif
  603. U_BOOT_DRIVER(fsl_imx23_mmc) = {
  604. .name = "fsl_imx23_mmc",
  605. .id = UCLASS_MMC,
  606. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  607. .of_match = mxsmmc_ids,
  608. .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
  609. #endif
  610. .ops = &mxsmmc_ops,
  611. #if CONFIG_IS_ENABLED(BLK)
  612. .bind = mxsmmc_bind,
  613. #endif
  614. .probe = mxsmmc_probe,
  615. .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
  616. .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
  617. };
  618. U_BOOT_DRIVER_ALIAS(fsl_imx23_mmc, fsl_imx28_mmc)
  619. #endif /* CONFIG_DM_MMC */